calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
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import "primitives/core.futil";
import "primitives/memories/comb.futil";
import "primitives/pipelined.futil";

component main() -> () {
    cells {
      @external m = comb_mem_d1(32, 1, 1);
      add = std_add(32);
      r0 = std_reg(1);
      r1 = std_reg(1);
    }
    wires {
        static<1> group one {
            add.left = m.read_data;
            add.right = 32'd1;
            m.write_data = add.out;
            m.addr0 = 1'd0;
            m.write_en = 1'd1;
        }
    }
    control {
        static repeat 2 {
            static repeat 2 {
                one;
            }
        }
    }
}