calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

import "primitives/core.futil";
import "primitives/memories/comb.futil";

component main(@go go: 1) -> (@done done: 1) {
  // ANCHOR: cells
  cells {
    @external mem = comb_mem_d1(32, 1, 1);
  }
  // ANCHOR_END: cells
  // ANCHOR: wires
  wires {
      mem.addr0 = 1'b0;
      mem.write_data = 32'd42;
      mem.write_en = 1'b1;
      done = mem.done;
  }
  // ANCHOR_END: wires
  control {}
}