calyx 0.7.1

Compiler Infrastructure for Hardware Accelerator Generation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

import "primitives/core.futil";
import "primitives/memories/comb.futil";

component main(@go go: 1) -> (@done done: 1) {
  // ANCHOR: cells
  cells {
    @external(1) mem = comb_mem_d1(32, 1, 1);
    val = std_reg(32);
    add = std_add(32);
  }
  // ANCHOR_END: cells
  // ANCHOR: wires
  wires {
  // ANCHOR: write
    group write {
      mem.addr0 = 1'b0;
      mem.write_en = 1'b1;
      mem.write_data = val.out;
      write[done] = mem.done;
    }
  // ANCHOR_END: write
  // ANCHOR: read
    group read {
      mem.addr0 = 1'b0;
      val.in = mem.read_data;
      val.write_en = 1'b1;
      read[done] = val.done;
    }
  // ANCHOR_END: read
  // ANCHOR: upd
    group upd {
      add.left = val.out;
      add.right = 32'd4;
      val.in = add.out;
      val.write_en = 1'b1;
      upd[done] = val.done;
    }
  // ANCHOR_END: upd
  }
  // ANCHOR_END: wires
  // ANCHOR: control
  control {
    seq {
      read;
      upd;
      write;
    }
  }
  // ANCHOR_END: control
}