bl602-pac 0.0.0

Embedded Rust's Peripheral Access Crate for BL602 RISC-V WiFi microcontroller
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185

#[doc = "Register `adda2` reader"]
pub struct R(crate::R<ADDA2_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<ADDA2_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<ADDA2_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<ADDA2_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `adda2` writer"]
pub struct W(crate::W<ADDA2_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<ADDA2_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<ADDA2_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<ADDA2_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `adc_vref_sel` reader - "]
pub type ADC_VREF_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `adc_vref_sel` writer - "]
pub type ADC_VREF_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDA2_SPEC, u8, u8, 2, O>;
#[doc = "Field `adc_dly_ctl` reader - "]
pub type ADC_DLY_CTL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `adc_dly_ctl` writer - "]
pub type ADC_DLY_CTL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDA2_SPEC, u8, u8, 2, O>;
#[doc = "Field `adc_dvdd_sel` reader - "]
pub type ADC_DVDD_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `adc_dvdd_sel` writer - "]
pub type ADC_DVDD_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDA2_SPEC, u8, u8, 2, O>;
#[doc = "Field `adc_sar_ascal_en` reader - "]
pub type ADC_SAR_ASCAL_EN_R = crate::BitReader<bool>;
#[doc = "Field `adc_sar_ascal_en` writer - "]
pub type ADC_SAR_ASCAL_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDA2_SPEC, bool, O>;
#[doc = "Field `adc_gt_rm` reader - "]
pub type ADC_GT_RM_R = crate::BitReader<bool>;
#[doc = "Field `adc_gt_rm` writer - "]
pub type ADC_GT_RM_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDA2_SPEC, bool, O>;
#[doc = "Field `adc_clk_sync_inv` reader - "]
pub type ADC_CLK_SYNC_INV_R = crate::BitReader<bool>;
#[doc = "Field `adc_clk_sync_inv` writer - "]
pub type ADC_CLK_SYNC_INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDA2_SPEC, bool, O>;
#[doc = "Field `adc_clk_inv` reader - "]
pub type ADC_CLK_INV_R = crate::BitReader<bool>;
#[doc = "Field `adc_clk_inv` writer - "]
pub type ADC_CLK_INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDA2_SPEC, bool, O>;
#[doc = "Field `adc_clk_div_sel` reader - "]
pub type ADC_CLK_DIV_SEL_R = crate::BitReader<bool>;
#[doc = "Field `adc_clk_div_sel` writer - "]
pub type ADC_CLK_DIV_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDA2_SPEC, bool, O>;
impl R {
    #[doc = "Bits 0:1"]
    #[inline(always)]
    pub fn adc_vref_sel(&self) -> ADC_VREF_SEL_R {
        ADC_VREF_SEL_R::new((self.bits & 3) as u8)
    }
    #[doc = "Bits 4:5"]
    #[inline(always)]
    pub fn adc_dly_ctl(&self) -> ADC_DLY_CTL_R {
        ADC_DLY_CTL_R::new(((self.bits >> 4) & 3) as u8)
    }
    #[doc = "Bits 8:9"]
    #[inline(always)]
    pub fn adc_dvdd_sel(&self) -> ADC_DVDD_SEL_R {
        ADC_DVDD_SEL_R::new(((self.bits >> 8) & 3) as u8)
    }
    #[doc = "Bit 12"]
    #[inline(always)]
    pub fn adc_sar_ascal_en(&self) -> ADC_SAR_ASCAL_EN_R {
        ADC_SAR_ASCAL_EN_R::new(((self.bits >> 12) & 1) != 0)
    }
    #[doc = "Bit 16"]
    #[inline(always)]
    pub fn adc_gt_rm(&self) -> ADC_GT_RM_R {
        ADC_GT_RM_R::new(((self.bits >> 16) & 1) != 0)
    }
    #[doc = "Bit 20"]
    #[inline(always)]
    pub fn adc_clk_sync_inv(&self) -> ADC_CLK_SYNC_INV_R {
        ADC_CLK_SYNC_INV_R::new(((self.bits >> 20) & 1) != 0)
    }
    #[doc = "Bit 24"]
    #[inline(always)]
    pub fn adc_clk_inv(&self) -> ADC_CLK_INV_R {
        ADC_CLK_INV_R::new(((self.bits >> 24) & 1) != 0)
    }
    #[doc = "Bit 28"]
    #[inline(always)]
    pub fn adc_clk_div_sel(&self) -> ADC_CLK_DIV_SEL_R {
        ADC_CLK_DIV_SEL_R::new(((self.bits >> 28) & 1) != 0)
    }
}
impl W {
    #[doc = "Bits 0:1"]
    #[inline(always)]
    #[must_use]
    pub fn adc_vref_sel(&mut self) -> ADC_VREF_SEL_W<0> {
        ADC_VREF_SEL_W::new(self)
    }
    #[doc = "Bits 4:5"]
    #[inline(always)]
    #[must_use]
    pub fn adc_dly_ctl(&mut self) -> ADC_DLY_CTL_W<4> {
        ADC_DLY_CTL_W::new(self)
    }
    #[doc = "Bits 8:9"]
    #[inline(always)]
    #[must_use]
    pub fn adc_dvdd_sel(&mut self) -> ADC_DVDD_SEL_W<8> {
        ADC_DVDD_SEL_W::new(self)
    }
    #[doc = "Bit 12"]
    #[inline(always)]
    #[must_use]
    pub fn adc_sar_ascal_en(&mut self) -> ADC_SAR_ASCAL_EN_W<12> {
        ADC_SAR_ASCAL_EN_W::new(self)
    }
    #[doc = "Bit 16"]
    #[inline(always)]
    #[must_use]
    pub fn adc_gt_rm(&mut self) -> ADC_GT_RM_W<16> {
        ADC_GT_RM_W::new(self)
    }
    #[doc = "Bit 20"]
    #[inline(always)]
    #[must_use]
    pub fn adc_clk_sync_inv(&mut self) -> ADC_CLK_SYNC_INV_W<20> {
        ADC_CLK_SYNC_INV_W::new(self)
    }
    #[doc = "Bit 24"]
    #[inline(always)]
    #[must_use]
    pub fn adc_clk_inv(&mut self) -> ADC_CLK_INV_W<24> {
        ADC_CLK_INV_W::new(self)
    }
    #[doc = "Bit 28"]
    #[inline(always)]
    #[must_use]
    pub fn adc_clk_div_sel(&mut self) -> ADC_CLK_DIV_SEL_W<28> {
        ADC_CLK_DIV_SEL_W::new(self)
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "adda2.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adda2](index.html) module"]
pub struct ADDA2_SPEC;
impl crate::RegisterSpec for ADDA2_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [adda2::R](R) reader structure"]
impl crate::Readable for ADDA2_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [adda2::W](W) writer structure"]
impl crate::Writable for ADDA2_SPEC {
    type Writer = W;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets adda2 to value 0"]
impl crate::Resettable for ADDA2_SPEC {
    const RESET_VALUE: Self::Ux = 0;
}