Struct Sim 

pub struct Sim { /* private fields */ }

Simulator state for one FrozenHir circuit.

Implementations

impl Sim

pub fn new(hir: FrozenHir) -> Self

pub fn with_engine(hir: FrozenHir, engine: TickEngine) -> Self

pub fn engine(&self) -> TickEngine

pub fn enable_vcd(&mut self, path: impl AsRef<Path>) -> Result<()>

pub fn enable_fst(&mut self, path: impl AsRef<Path>) -> Result<(), FstError>

Optional FST: still dumps VCD, then converts with vcd2fst (AD-24).

pub fn enable_fst_with( &mut self, path: impl AsRef<Path>, converter: impl AsRef<Path>, ) -> Result<(), FstError>

Same as enable_fst with an explicit converter (tests / RHDL_VCD2FST).

pub fn finish_waves(&mut self) -> Result<(), FstError>

Flush VCD and, if FST was requested, run the documented converter.

pub fn set_inputs(&mut self, inputs: PortValues)

pub fn ports(&self) -> &PortValues

pub fn tick(&mut self)

One rising edge of the module Clock (AD-15). Driven by FrozenHir assigns.

pub fn coverage_report(&self) -> String