bender 0.32.0

A dependency management tool for hardware projects.
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# {{ HEADER_AUTOGEN }}
set ROOT "{{ root }}"
{# Separate compilation: one block per source group -#}
{% if compilation_mode == 'separate' -%}
{%- for group in srcs %}{% if group.file_type != '' %}
{% if source_annotations %}# {{ group.metadata }}
{% endif -%}
{%- if abort_on_error %}if {[catch { {% endif -%}
{%- if group.file_type == 'verilog' %}vlog -incr -sv \
    {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
    {% endfor -%}
{%- for define in group.defines %}"+define+{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}" \
    {% endfor -%}
{%- for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
    {% endfor -%}
{%- elif group.file_type == 'vhdl' %}vcom -2008 \
    {% for tmp_arg in vcom_args %}{{ tmp_arg }} \
    {% endfor -%}
{%- endif -%}
{%- for file in group.files -%}
{%- if source_annotations %}{% if file.comment %}# {{ file.comment }}
    {% endif %}{% endif %}"{{ file.file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
    {% endif -%}
{%- endfor -%}
{%- if abort_on_error %}\
}]} {return 1}{% endif %}
{% endif %}{% endfor -%}
{# Common compilation: all files in one block -#}
{%- else -%}
{# Verilog sources -#}
{%- for file in all_verilog %}{% if loop.first -%}
{%- if abort_on_error %}if {[catch { {% endif -%}
vlog -incr -sv \
    {% for tmp_arg in vlog_args %}{{ tmp_arg }} \
    {% endfor -%}
{%- for define in all_defines %}"+define+{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}" \
    {% endfor -%}
{%- for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
    {% endfor -%}
{%- endif %}{% if source_annotations %}{% if file.comment %}# {{ file.comment }}
    {% endif %}{% endif %}"{{ file.file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
    {% endif -%}
{%- if loop.last %}{% if abort_on_error %} \
}]} {return 1}{% endif %}
{% endif %}{% endfor -%}
{# VHDL sources -#}
{%- for file in all_vhdl %}{% if loop.first -%}
{%- if abort_on_error %}if {[catch { {% endif -%}
vcom -2008 \
    {% for tmp_arg in vcom_args %}{{ tmp_arg }} \
    {% endfor -%}
{%- endif %}{% if source_annotations %}{% if file.comment %}# {{ file.comment }}
    {% endif %}{% endif %}"{{ file.file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
    {% endif -%}
{%- if loop.last %}{% if abort_on_error %} \
}]} {return 1}{% endif %}
{% endif %}{% endfor %}{% endif %}