bender 0.32.0

A dependency management tool for hardware projects.
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# {{HEADER_AUTOGEN}}
set ROOT "{{ root }}"
set search_path_initial $search_path
{# Separate compilation: one block per source group -#}
{% if compilation_mode == 'separate' -%}
{%- for group in srcs %}{% if group.file_type != '' %}{% if source_annotations %}
# {{ group.metadata }}{% endif %}
set search_path $search_path_initial
{% for incdir in group.incdirs -%}
lappend search_path "{{ incdir | replace(from=root, to='$ROOT') }}"
{% endfor %}
{% if abort_on_error %}if {0 == [{% endif -%}
analyze -format {% if group.file_type == 'verilog' %}sv{% elif group.file_type == 'vhdl' %}vhdl{% endif %} \
{% if group.file_type == 'verilog' -%}
{%- for tmp_arg in verilog_args %}{{ tmp_arg }} \
{% endfor -%}
{%- else -%}
{%- for tmp_arg in vhdl_args %}{{ tmp_arg }} \
{% endfor -%}
{%- endif -%}
{%- for define in group.defines -%}
{%- if loop.first %}-define { \
        {% endif %}{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
    } \
    {% else %} \
        {% endif %}{% endfor %}[list \
    {% for file in group.files -%}
{%- if source_annotations %}{% if file.comment %}{{ '    ' }}# {{ file.comment }}
{% endif %}{% endif %}{{ '    ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \
    {% endfor %}]
{% if abort_on_error %}]} {return 1}{% endif %}
{% endif %}{% endfor %}
{# Common compilation: all files in one block -#}
{% else -%}
{# Verilog sources -#}
{%- for file in all_verilog -%}
{%- if loop.first %}set search_path $search_path_initial
{% for incdir in all_incdirs -%}
lappend search_path "{{ incdir | replace(from=root, to='$ROOT') }}"
{% endfor %}
{% if abort_on_error %}if {0 == [{% endif -%}
analyze -format sv \
{% for tmp_arg in verilog_args %}{{ tmp_arg }} \
{% endfor -%}
    {%- for define in all_defines -%}
{%- if loop.first %}-define { \
        {% endif %}{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}{% if loop.last %} \
    } \
    {% else %} \
        {% endif %}{% endfor %}[list \
    {% endif %}{% if source_annotations %}{% if file.comment %}{{ '    ' }}# {{ file.comment }}
    {% endif %}{% endif %}{{ '    ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \
    {% if loop.last %}]
{% if abort_on_error %}]} {return 1}{% endif %}
{% endif %}{% endfor %}
{# VHDL sources -#}
{% for file in all_vhdl %}{% if loop.first -%}
{%- if abort_on_error %}if {0 == [{% endif -%}
analyze -format vhdl \
{% for tmp_arg in vhdl_args %}{{ tmp_arg }} \
{% endfor -%}
    [list \
    {% endif %}{% if source_annotations %}{% if file.comment %}{{ '    ' }}# {{ file.comment }}
    {% endif %}{% endif %}{{ '    ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \
    {% if loop.last %}]
{% if abort_on_error %}]} {return 1}{% endif %}
{% endif %}{% endfor %}
{% endif %}set search_path $search_path_initial