#[doc = "Register `CONFIG_REG_0` reader"]
pub type R = crate::R<ConfigReg0Spec>;
#[doc = "Register `CONFIG_REG_0` writer"]
pub type W = crate::W<ConfigReg0Spec>;
#[doc = "Field `CFG_1LVDS_0CSI` reader - 0:0\\]
0 : Send data over CSI-2 1 : Send data over LVDS"]
pub type Cfg1lvds0csiR = crate::BitReader;
#[doc = "Field `CFG_1LVDS_0CSI` writer - 0:0\\]
0 : Send data over CSI-2 1 : Send data over LVDS"]
pub type Cfg1lvds0csiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CFG_ECC_EN` reader - 1:1\\]
0 : Disable ECC on the CBUF FIFO 1 : Enable ECC on the CBUF FIFO"]
pub type CfgEccEnR = crate::BitReader;
#[doc = "Field `CFG_ECC_EN` writer - 1:1\\]
0 : Disable ECC on the CBUF FIFO 1 : Enable ECC on the CBUF FIFO"]
pub type CfgEccEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cftrigen` reader - 2:2\\]
Select Frame Start Trigger Source 0 : Frame trigger will be generated by HW 1 : Frame trigger will be generated by SW"]
pub type CftrigenR = crate::BitReader;
#[doc = "Field `cftrigen` writer - 2:2\\]
Select Frame Start Trigger Source 0 : Frame trigger will be generated by HW 1 : Frame trigger will be generated by SW"]
pub type CftrigenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CFG_SW_TRIG_EN` reader - 3:3\\]
Select Chirp Available Trigger Source 0 : Chirp Available trigger will be generated by HW 1 : Chirp Available trigger will be generated by SW"]
pub type CfgSwTrigEnR = crate::BitReader;
#[doc = "Field `CFG_SW_TRIG_EN` writer - 3:3\\]
Select Chirp Available Trigger Source 0 : Chirp Available trigger will be generated by HW 1 : Chirp Available trigger will be generated by SW"]
pub type CfgSwTrigEnW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `NU1` reader - "]
pub type Nu1R = crate::FieldReader;
#[doc = "Field `NU1` writer - "]
pub type Nu1W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `ccfwlen` reader - 8:8\\]
TI Internal Feature. Debug only. CSI2 only Programming : CFG_CSI2_FIFO_WORDS_LOAD_SW_EN. This is a Debug feature. Not requred in Programming model When CFG_CSI2_FIFO_WORDS_PROCESSING_EN==1 and CFG_CSI2_FIFO_WORDS_LOAD_SW_EN==1, then a fixed fifo_free_words from CSI2 is not used. Program the CFG_FIFO_FREE_THRESHOLD0 to 0x4"]
pub type CcfwlenR = crate::BitReader;
#[doc = "Field `ccfwlen` writer - 8:8\\]
TI Internal Feature. Debug only. CSI2 only Programming : CFG_CSI2_FIFO_WORDS_LOAD_SW_EN. This is a Debug feature. Not requred in Programming model When CFG_CSI2_FIFO_WORDS_PROCESSING_EN==1 and CFG_CSI2_FIFO_WORDS_LOAD_SW_EN==1, then a fixed fifo_free_words from CSI2 is not used. Program the CFG_FIFO_FREE_THRESHOLD0 to 0x4"]
pub type CcfwlenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `crdthsel` reader - 9:9\\]
TI Internal Feature. Debug only. CSI2 only Programming : CFG_RDTHRESHOLD_SEL . This is a Debug feature. Not requred in Programming model 0 : The read threshold is selected based on the Write Side parsing engine 1 : The read threshold is selected based on the Read Side parsing engine."]
pub type CrdthselR = crate::BitReader;
#[doc = "Field `crdthsel` writer - 9:9\\]
TI Internal Feature. Debug only. CSI2 only Programming : CFG_RDTHRESHOLD_SEL . This is a Debug feature. Not requred in Programming model 0 : The read threshold is selected based on the Write Side parsing engine 1 : The read threshold is selected based on the Read Side parsing engine."]
pub type CrdthselW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cvc0en` reader - 11:10\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 0 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 0 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 0 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 0 is generated at end of Frame"]
pub type Cvc0enR = crate::FieldReader;
#[doc = "Field `cvc0en` writer - 11:10\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 0 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 0 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 0 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 0 is generated at end of Frame"]
pub type Cvc0enW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `cvc1en` reader - 13:12\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 1 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 1 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 1 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 1 is generated at end of Frame"]
pub type Cvc1enR = crate::FieldReader;
#[doc = "Field `cvc1en` writer - 13:12\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 1 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 1 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 1 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 1 is generated at end of Frame"]
pub type Cvc1enW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `cvc2en` reader - 15:14\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 2 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 2 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 2 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 2 is generated at end of Frame"]
pub type Cvc2enR = crate::FieldReader;
#[doc = "Field `cvc2en` writer - 15:14\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 2 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 2 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 2 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 2 is generated at end of Frame"]
pub type Cvc2enW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `cvc3en` reader - 17:16\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 3 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 3 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 3 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 3 is generated at end of Frame"]
pub type Cvc3enR = crate::FieldReader;
#[doc = "Field `cvc3en` writer - 17:16\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 3 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 3 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 3 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 3 is generated at end of Frame"]
pub type Cvc3enW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
#[doc = "Field `ccfwpen` reader - 18:18\\]
TI Internal Feature. Debug only. CSI2 only Programming : CFG_CSI2_FIFO_WORDS_PROCESSING_EN 0 : Use the fifo_free_words directly from CSI2 by vbusp_mstr to decide how many more words to send. 1 : Process the fifo_free_words and use it by vbusp_mstr to decide how many more words to send."]
pub type CcfwpenR = crate::BitReader;
#[doc = "Field `ccfwpen` writer - 18:18\\]
TI Internal Feature. Debug only. CSI2 only Programming : CFG_CSI2_FIFO_WORDS_PROCESSING_EN 0 : Use the fifo_free_words directly from CSI2 by vbusp_mstr to decide how many more words to send. 1 : Process the fifo_free_words and use it by vbusp_mstr to decide how many more words to send."]
pub type CcfwpenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `dbusen` reader - 19:19\\]
TC2 Mode selection. TI Internal feature. 0 : Normal 1 : When in TC2 mode, setting this bit will enable debug bus to sent via LVDS"]
pub type DbusenR = crate::BitReader;
#[doc = "Field `dbusen` writer - 19:19\\]
TC2 Mode selection. TI Internal feature. 0 : Normal 1 : When in TC2 mode, setting this bit will enable debug bus to sent via LVDS"]
pub type DbusenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CFG_VBUSP_BURST_EN` reader - 23:20\\]
TI Internal Feature. Only required for 900 Mbps 4 lane trasnmission CSI2 only Programming : 0xA : Burst Enable. Set this only for transmission at 900 Mbps Others : Burst disable."]
pub type CfgVbuspBurstEnR = crate::FieldReader;
#[doc = "Field `CFG_VBUSP_BURST_EN` writer - 23:20\\]
TI Internal Feature. Only required for 900 Mbps 4 lane trasnmission CSI2 only Programming : 0xA : Burst Enable. Set this only for transmission at 900 Mbps Others : Burst disable."]
pub type CfgVbuspBurstEnW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
#[doc = "Field `CFG_CHIRP_AVAIL_TRIG` reader - 24:24\\]
SW Trigger generation : Write 1 to this bit to generate a Chirp Available SW Trigger"]
pub type CfgChirpAvailTrigR = crate::BitReader;
#[doc = "Field `CFG_CHIRP_AVAIL_TRIG` writer - 24:24\\]
SW Trigger generation : Write 1 to this bit to generate a Chirp Available SW Trigger"]
pub type CfgChirpAvailTrigW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CFG_FRAME_START_TRIG` reader - 25:25\\]
SW Trigger generation : Write 1 to this bit to generate a Frame Start SW Trigger"]
pub type CfgFrameStartTrigR = crate::BitReader;
#[doc = "Field `CFG_FRAME_START_TRIG` writer - 25:25\\]
SW Trigger generation : Write 1 to this bit to generate a Frame Start SW Trigger"]
pub type CfgFrameStartTrigW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cswlrst` reader - 26:26\\]
TI Internal Feature. LVDS logic SW Reset. Debug feature. 1 => RESET the FSM 0 => RELEASE RESET"]
pub type CswlrstR = crate::BitReader;
#[doc = "Field `cswlrst` writer - 26:26\\]
TI Internal Feature. LVDS logic SW Reset. Debug feature. 1 => RESET the FSM 0 => RELEASE RESET"]
pub type CswlrstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cswcrst` reader - 27:27\\]
CBUFF controller SW Reset 1 => RESET the CBUFF Controller 0 => RELEASE RESET for CBUFF Controller"]
pub type CswcrstR = crate::BitReader;
#[doc = "Field `cswcrst` writer - 27:27\\]
CBUFF controller SW Reset 1 => RESET the CBUFF Controller 0 => RELEASE RESET for CBUFF Controller"]
pub type CswcrstW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `dbussel` reader - 31:28\\]
TI Internal feature. 1 : This selects the debug bus mode transmission on LVDS"]
pub type DbusselR = crate::FieldReader;
#[doc = "Field `dbussel` writer - 31:28\\]
TI Internal feature. 1 : This selects the debug bus mode transmission on LVDS"]
pub type DbusselW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
impl R {
#[doc = "Bit 0 - 0:0\\]
0 : Send data over CSI-2 1 : Send data over LVDS"]
#[inline(always)]
pub fn cfg_1lvds_0csi(&self) -> Cfg1lvds0csiR {
Cfg1lvds0csiR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - 1:1\\]
0 : Disable ECC on the CBUF FIFO 1 : Enable ECC on the CBUF FIFO"]
#[inline(always)]
pub fn cfg_ecc_en(&self) -> CfgEccEnR {
CfgEccEnR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - 2:2\\]
Select Frame Start Trigger Source 0 : Frame trigger will be generated by HW 1 : Frame trigger will be generated by SW"]
#[inline(always)]
pub fn cftrigen(&self) -> CftrigenR {
CftrigenR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - 3:3\\]
Select Chirp Available Trigger Source 0 : Chirp Available trigger will be generated by HW 1 : Chirp Available trigger will be generated by SW"]
#[inline(always)]
pub fn cfg_sw_trig_en(&self) -> CfgSwTrigEnR {
CfgSwTrigEnR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:7"]
#[inline(always)]
pub fn nu1(&self) -> Nu1R {
Nu1R::new(((self.bits >> 4) & 0x0f) as u8)
}
#[doc = "Bit 8 - 8:8\\]
TI Internal Feature. Debug only. CSI2 only Programming : CFG_CSI2_FIFO_WORDS_LOAD_SW_EN. This is a Debug feature. Not requred in Programming model When CFG_CSI2_FIFO_WORDS_PROCESSING_EN==1 and CFG_CSI2_FIFO_WORDS_LOAD_SW_EN==1, then a fixed fifo_free_words from CSI2 is not used. Program the CFG_FIFO_FREE_THRESHOLD0 to 0x4"]
#[inline(always)]
pub fn ccfwlen(&self) -> CcfwlenR {
CcfwlenR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - 9:9\\]
TI Internal Feature. Debug only. CSI2 only Programming : CFG_RDTHRESHOLD_SEL . This is a Debug feature. Not requred in Programming model 0 : The read threshold is selected based on the Write Side parsing engine 1 : The read threshold is selected based on the Read Side parsing engine."]
#[inline(always)]
pub fn crdthsel(&self) -> CrdthselR {
CrdthselR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bits 10:11 - 11:10\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 0 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 0 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 0 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 0 is generated at end of Frame"]
#[inline(always)]
pub fn cvc0en(&self) -> Cvc0enR {
Cvc0enR::new(((self.bits >> 10) & 3) as u8)
}
#[doc = "Bits 12:13 - 13:12\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 1 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 1 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 1 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 1 is generated at end of Frame"]
#[inline(always)]
pub fn cvc1en(&self) -> Cvc1enR {
Cvc1enR::new(((self.bits >> 12) & 3) as u8)
}
#[doc = "Bits 14:15 - 15:14\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 2 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 2 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 2 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 2 is generated at end of Frame"]
#[inline(always)]
pub fn cvc2en(&self) -> Cvc2enR {
Cvc2enR::new(((self.bits >> 14) & 3) as u8)
}
#[doc = "Bits 16:17 - 17:16\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 3 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 3 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 3 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 3 is generated at end of Frame"]
#[inline(always)]
pub fn cvc3en(&self) -> Cvc3enR {
Cvc3enR::new(((self.bits >> 16) & 3) as u8)
}
#[doc = "Bit 18 - 18:18\\]
TI Internal Feature. Debug only. CSI2 only Programming : CFG_CSI2_FIFO_WORDS_PROCESSING_EN 0 : Use the fifo_free_words directly from CSI2 by vbusp_mstr to decide how many more words to send. 1 : Process the fifo_free_words and use it by vbusp_mstr to decide how many more words to send."]
#[inline(always)]
pub fn ccfwpen(&self) -> CcfwpenR {
CcfwpenR::new(((self.bits >> 18) & 1) != 0)
}
#[doc = "Bit 19 - 19:19\\]
TC2 Mode selection. TI Internal feature. 0 : Normal 1 : When in TC2 mode, setting this bit will enable debug bus to sent via LVDS"]
#[inline(always)]
pub fn dbusen(&self) -> DbusenR {
DbusenR::new(((self.bits >> 19) & 1) != 0)
}
#[doc = "Bits 20:23 - 23:20\\]
TI Internal Feature. Only required for 900 Mbps 4 lane trasnmission CSI2 only Programming : 0xA : Burst Enable. Set this only for transmission at 900 Mbps Others : Burst disable."]
#[inline(always)]
pub fn cfg_vbusp_burst_en(&self) -> CfgVbuspBurstEnR {
CfgVbuspBurstEnR::new(((self.bits >> 20) & 0x0f) as u8)
}
#[doc = "Bit 24 - 24:24\\]
SW Trigger generation : Write 1 to this bit to generate a Chirp Available SW Trigger"]
#[inline(always)]
pub fn cfg_chirp_avail_trig(&self) -> CfgChirpAvailTrigR {
CfgChirpAvailTrigR::new(((self.bits >> 24) & 1) != 0)
}
#[doc = "Bit 25 - 25:25\\]
SW Trigger generation : Write 1 to this bit to generate a Frame Start SW Trigger"]
#[inline(always)]
pub fn cfg_frame_start_trig(&self) -> CfgFrameStartTrigR {
CfgFrameStartTrigR::new(((self.bits >> 25) & 1) != 0)
}
#[doc = "Bit 26 - 26:26\\]
TI Internal Feature. LVDS logic SW Reset. Debug feature. 1 => RESET the FSM 0 => RELEASE RESET"]
#[inline(always)]
pub fn cswlrst(&self) -> CswlrstR {
CswlrstR::new(((self.bits >> 26) & 1) != 0)
}
#[doc = "Bit 27 - 27:27\\]
CBUFF controller SW Reset 1 => RESET the CBUFF Controller 0 => RELEASE RESET for CBUFF Controller"]
#[inline(always)]
pub fn cswcrst(&self) -> CswcrstR {
CswcrstR::new(((self.bits >> 27) & 1) != 0)
}
#[doc = "Bits 28:31 - 31:28\\]
TI Internal feature. 1 : This selects the debug bus mode transmission on LVDS"]
#[inline(always)]
pub fn dbussel(&self) -> DbusselR {
DbusselR::new(((self.bits >> 28) & 0x0f) as u8)
}
}
impl W {
#[doc = "Bit 0 - 0:0\\]
0 : Send data over CSI-2 1 : Send data over LVDS"]
#[inline(always)]
#[must_use]
pub fn cfg_1lvds_0csi(&mut self) -> Cfg1lvds0csiW<ConfigReg0Spec> {
Cfg1lvds0csiW::new(self, 0)
}
#[doc = "Bit 1 - 1:1\\]
0 : Disable ECC on the CBUF FIFO 1 : Enable ECC on the CBUF FIFO"]
#[inline(always)]
#[must_use]
pub fn cfg_ecc_en(&mut self) -> CfgEccEnW<ConfigReg0Spec> {
CfgEccEnW::new(self, 1)
}
#[doc = "Bit 2 - 2:2\\]
Select Frame Start Trigger Source 0 : Frame trigger will be generated by HW 1 : Frame trigger will be generated by SW"]
#[inline(always)]
#[must_use]
pub fn cftrigen(&mut self) -> CftrigenW<ConfigReg0Spec> {
CftrigenW::new(self, 2)
}
#[doc = "Bit 3 - 3:3\\]
Select Chirp Available Trigger Source 0 : Chirp Available trigger will be generated by HW 1 : Chirp Available trigger will be generated by SW"]
#[inline(always)]
#[must_use]
pub fn cfg_sw_trig_en(&mut self) -> CfgSwTrigEnW<ConfigReg0Spec> {
CfgSwTrigEnW::new(self, 3)
}
#[doc = "Bits 4:7"]
#[inline(always)]
#[must_use]
pub fn nu1(&mut self) -> Nu1W<ConfigReg0Spec> {
Nu1W::new(self, 4)
}
#[doc = "Bit 8 - 8:8\\]
TI Internal Feature. Debug only. CSI2 only Programming : CFG_CSI2_FIFO_WORDS_LOAD_SW_EN. This is a Debug feature. Not requred in Programming model When CFG_CSI2_FIFO_WORDS_PROCESSING_EN==1 and CFG_CSI2_FIFO_WORDS_LOAD_SW_EN==1, then a fixed fifo_free_words from CSI2 is not used. Program the CFG_FIFO_FREE_THRESHOLD0 to 0x4"]
#[inline(always)]
#[must_use]
pub fn ccfwlen(&mut self) -> CcfwlenW<ConfigReg0Spec> {
CcfwlenW::new(self, 8)
}
#[doc = "Bit 9 - 9:9\\]
TI Internal Feature. Debug only. CSI2 only Programming : CFG_RDTHRESHOLD_SEL . This is a Debug feature. Not requred in Programming model 0 : The read threshold is selected based on the Write Side parsing engine 1 : The read threshold is selected based on the Read Side parsing engine."]
#[inline(always)]
#[must_use]
pub fn crdthsel(&mut self) -> CrdthselW<ConfigReg0Spec> {
CrdthselW::new(self, 9)
}
#[doc = "Bits 10:11 - 11:10\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 0 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 0 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 0 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 0 is generated at end of Frame"]
#[inline(always)]
#[must_use]
pub fn cvc0en(&mut self) -> Cvc0enW<ConfigReg0Spec> {
Cvc0enW::new(self, 10)
}
#[doc = "Bits 12:13 - 13:12\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 1 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 1 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 1 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 1 is generated at end of Frame"]
#[inline(always)]
#[must_use]
pub fn cvc1en(&mut self) -> Cvc1enW<ConfigReg0Spec> {
Cvc1enW::new(self, 12)
}
#[doc = "Bits 14:15 - 15:14\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 2 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 2 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 2 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 2 is generated at end of Frame"]
#[inline(always)]
#[must_use]
pub fn cvc2en(&mut self) -> Cvc2enW<ConfigReg0Spec> {
Cvc2enW::new(self, 14)
}
#[doc = "Bits 16:17 - 17:16\\]
CSI2 only Programming : 0 : No Vsync packet is sent at Frame boundary 1 : A VSYNC Start packet on Virtual Channel 3 is generated at beginning of Frame 2 : A VSYNC End packet on Virtual Channel 3 is generated at end of Frame 3 : A VSYNC Start packet on Virtual Channel 3 is generated at beginning of Frame and a VSYNC End packet on Virtual Channel 3 is generated at end of Frame"]
#[inline(always)]
#[must_use]
pub fn cvc3en(&mut self) -> Cvc3enW<ConfigReg0Spec> {
Cvc3enW::new(self, 16)
}
#[doc = "Bit 18 - 18:18\\]
TI Internal Feature. Debug only. CSI2 only Programming : CFG_CSI2_FIFO_WORDS_PROCESSING_EN 0 : Use the fifo_free_words directly from CSI2 by vbusp_mstr to decide how many more words to send. 1 : Process the fifo_free_words and use it by vbusp_mstr to decide how many more words to send."]
#[inline(always)]
#[must_use]
pub fn ccfwpen(&mut self) -> CcfwpenW<ConfigReg0Spec> {
CcfwpenW::new(self, 18)
}
#[doc = "Bit 19 - 19:19\\]
TC2 Mode selection. TI Internal feature. 0 : Normal 1 : When in TC2 mode, setting this bit will enable debug bus to sent via LVDS"]
#[inline(always)]
#[must_use]
pub fn dbusen(&mut self) -> DbusenW<ConfigReg0Spec> {
DbusenW::new(self, 19)
}
#[doc = "Bits 20:23 - 23:20\\]
TI Internal Feature. Only required for 900 Mbps 4 lane trasnmission CSI2 only Programming : 0xA : Burst Enable. Set this only for transmission at 900 Mbps Others : Burst disable."]
#[inline(always)]
#[must_use]
pub fn cfg_vbusp_burst_en(&mut self) -> CfgVbuspBurstEnW<ConfigReg0Spec> {
CfgVbuspBurstEnW::new(self, 20)
}
#[doc = "Bit 24 - 24:24\\]
SW Trigger generation : Write 1 to this bit to generate a Chirp Available SW Trigger"]
#[inline(always)]
#[must_use]
pub fn cfg_chirp_avail_trig(&mut self) -> CfgChirpAvailTrigW<ConfigReg0Spec> {
CfgChirpAvailTrigW::new(self, 24)
}
#[doc = "Bit 25 - 25:25\\]
SW Trigger generation : Write 1 to this bit to generate a Frame Start SW Trigger"]
#[inline(always)]
#[must_use]
pub fn cfg_frame_start_trig(&mut self) -> CfgFrameStartTrigW<ConfigReg0Spec> {
CfgFrameStartTrigW::new(self, 25)
}
#[doc = "Bit 26 - 26:26\\]
TI Internal Feature. LVDS logic SW Reset. Debug feature. 1 => RESET the FSM 0 => RELEASE RESET"]
#[inline(always)]
#[must_use]
pub fn cswlrst(&mut self) -> CswlrstW<ConfigReg0Spec> {
CswlrstW::new(self, 26)
}
#[doc = "Bit 27 - 27:27\\]
CBUFF controller SW Reset 1 => RESET the CBUFF Controller 0 => RELEASE RESET for CBUFF Controller"]
#[inline(always)]
#[must_use]
pub fn cswcrst(&mut self) -> CswcrstW<ConfigReg0Spec> {
CswcrstW::new(self, 27)
}
#[doc = "Bits 28:31 - 31:28\\]
TI Internal feature. 1 : This selects the debug bus mode transmission on LVDS"]
#[inline(always)]
#[must_use]
pub fn dbussel(&mut self) -> DbusselW<ConfigReg0Spec> {
DbusselW::new(self, 28)
}
}
#[doc = "Basic Config register\n\nYou can [`read`](crate::Reg::read) this register and get [`config_reg_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config_reg_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ConfigReg0Spec;
impl crate::RegisterSpec for ConfigReg0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`config_reg_0::R`](R) reader structure"]
impl crate::Readable for ConfigReg0Spec {}
#[doc = "`write(|w| ..)` method takes [`config_reg_0::W`](W) writer structure"]
impl crate::Writable for ConfigReg0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CONFIG_REG_0 to value 0"]
impl crate::Resettable for ConfigReg0Spec {
const RESET_VALUE: u32 = 0;
}