aarch32-cpu 0.3.0

CPU support for AArch32 Arm Processors
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

//! Code for managing TLBIALL (*TLB Invalidate All Register*)

use crate::register::SysReg;

/// TLBIALL (*TLB Invalidate All Register*)
pub struct TlbIAll;

impl SysReg for TlbIAll {
    const CP: u32 = 15;
    const CRN: u32 = 8;
    const OP1: u32 = 0;
    const CRM: u32 = 7;
    const OP2: u32 = 0;
}

impl crate::register::SysRegWrite for TlbIAll {}

impl TlbIAll {
    #[inline]
    /// Writes 0 to TLBIALL (*TLB Invalidate All Register*) to trigger operation
    pub fn write() {
        unsafe { <Self as crate::register::SysRegWrite>::write_raw(0) }
    }
}