aarch32-cpu 0.3.0

CPU support for AArch32 Arm Processors
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

//! Code for managing CLIDR (*Cache Level ID Register*)

use crate::register::{SysReg, SysRegRead};

/// CLIDR (*Cache Level ID Register*)
#[derive(Debug, Copy, Clone)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
pub struct Clidr(pub u32);

impl SysReg for Clidr {
    const CP: u32 = 15;
    const CRN: u32 = 0;
    const OP1: u32 = 1;
    const CRM: u32 = 0;
    const OP2: u32 = 1;
}

impl crate::register::SysRegRead for Clidr {}

impl Clidr {
    #[inline]
    /// Reads CLIDR (*Cache Level ID Register*)
    pub fn read() -> Clidr {
        Self(<Self as SysRegRead>::read_raw())
    }
}