Struct cc2538::aes::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub dmac_ch0_ctrl: DMAC_CH0_CTRL,
    pub dmac_ch0_extaddr: DMAC_CH0_EXTADDR,
    pub dmac_ch0_dmalength: DMAC_CH0_DMALENGTH,
    pub dmac_status: DMAC_STATUS,
    pub dmac_swres: DMAC_SWRES,
    pub dmac_ch1_ctrl: DMAC_CH1_CTRL,
    pub dmac_ch1_extaddr: DMAC_CH1_EXTADDR,
    pub dmac_ch1_dmalength: DMAC_CH1_DMALENGTH,
    pub dmac_mst_runparams: DMAC_MST_RUNPARAMS,
    pub dmac_persr: DMAC_PERSR,
    pub dmac_options: DMAC_OPTIONS,
    pub dmac_version: DMAC_VERSION,
    pub key_store_write_area: KEY_STORE_WRITE_AREA,
    pub key_store_written_area: KEY_STORE_WRITTEN_AREA,
    pub key_store_size: KEY_STORE_SIZE,
    pub key_store_read_area: KEY_STORE_READ_AREA,
    pub aes_key2_0: AES_KEY2_0,
    pub aes_key2_1: AES_KEY2_1,
    pub aes_key2_2: AES_KEY2_2,
    pub aes_key2_3: AES_KEY2_3,
    pub aes_key3_0: AES_KEY3_0,
    pub aes_key3_1: AES_KEY3_1,
    pub aes_key3_2: AES_KEY3_2,
    pub aes_key3_3: AES_KEY3_3,
    pub aes_iv_0: AES_IV_0,
    pub aes_iv_1: AES_IV_1,
    pub aes_iv_2: AES_IV_2,
    pub aes_iv_3: AES_IV_3,
    pub aes_ctrl: AES_CTRL,
    pub aes_c_length_0: AES_C_LENGTH_0,
    pub aes_c_length_1: AES_C_LENGTH_1,
    pub aes_auth_length: AES_AUTH_LENGTH,
    pub aes_data_in_out_0: AES_DATA_IN_OUT_0,
    pub aes_data_in_out_1: AES_DATA_IN_OUT_1,
    pub aes_data_in_out_2: AES_DATA_IN_OUT_2,
    pub aes_data_in_out_3: AES_DATA_IN_OUT_3,
    pub aes_tag_out_0: AES_TAG_OUT_0,
    pub aes_tag_out_1: AES_TAG_OUT_1,
    pub aes_tag_out_2: AES_TAG_OUT_2,
    pub aes_tag_out_3: AES_TAG_OUT_3,
    pub hash_data_in_0: HASH_DATA_IN_0,
    pub hash_data_in_1: HASH_DATA_IN_1,
    pub hash_data_in_2: HASH_DATA_IN_2,
    pub hash_data_in_3: HASH_DATA_IN_3,
    pub hash_data_in_4: HASH_DATA_IN_4,
    pub hash_data_in_5: HASH_DATA_IN_5,
    pub hash_data_in_6: HASH_DATA_IN_6,
    pub hash_data_in_7: HASH_DATA_IN_7,
    pub hash_data_in_8: HASH_DATA_IN_8,
    pub hash_data_in_9: HASH_DATA_IN_9,
    pub hash_data_in_10: HASH_DATA_IN_10,
    pub hash_data_in_11: HASH_DATA_IN_11,
    pub hash_data_in_12: HASH_DATA_IN_12,
    pub hash_data_in_13: HASH_DATA_IN_13,
    pub hash_data_in_14: HASH_DATA_IN_14,
    pub hash_data_in_15: HASH_DATA_IN_15,
    pub hash_io_buf_ctrl: HASH_IO_BUF_CTRL,
    pub hash_mode_in: HASH_MODE_IN,
    pub hash_length_in_l: HASH_LENGTH_IN_L,
    pub hash_length_in_h: HASH_LENGTH_IN_H,
    pub hash_digest_a: HASH_DIGEST_A,
    pub hash_digest_b: HASH_DIGEST_B,
    pub hash_digest_c: HASH_DIGEST_C,
    pub hash_digest_d: HASH_DIGEST_D,
    pub hash_digest_e: HASH_DIGEST_E,
    pub hash_digest_f: HASH_DIGEST_F,
    pub hash_digest_g: HASH_DIGEST_G,
    pub hash_digest_h: HASH_DIGEST_H,
    pub ctrl_alg_sel: CTRL_ALG_SEL,
    pub ctrl_prot_en: CTRL_PROT_EN,
    pub ctrl_sw_reset: CTRL_SW_RESET,
    pub ctrl_int_cfg: CTRL_INT_CFG,
    pub ctrl_int_en: CTRL_INT_EN,
    pub ctrl_int_clr: CTRL_INT_CLR,
    pub ctrl_int_set: CTRL_INT_SET,
    pub ctrl_int_stat: CTRL_INT_STAT,
    pub ctrl_options: CTRL_OPTIONS,
    pub ctrl_version: CTRL_VERSION,
    // some fields omitted
}

Register block

Fields

dmac_ch0_ctrl: DMAC_CH0_CTRL

0x00 - Channel control This register is used for channel enabling and priority selection. When a channel is disabled, it becomes inactive only when all ongoing requests are finished.

dmac_ch0_extaddr: DMAC_CH0_EXTADDR

0x04 - Channel external address

dmac_ch0_dmalength: DMAC_CH0_DMALENGTH

0x0c - Channel DMA length

dmac_status: DMAC_STATUS

0x18 - DMAC status This register provides the actual state of each DMA channel. It also reports port errors in case these were received by the master interface module during the data transfer.

dmac_swres: DMAC_SWRES

0x1c - DMAC software reset register Software reset is used to reset the DMAC to stop all transfers and clears the port error status register. After the software reset is performed, all the channels are disabled and no new requests are performed by the channels. The DMAC waits for the existing (active) requests to finish and accordingly sets the DMAC status registers.

dmac_ch1_ctrl: DMAC_CH1_CTRL

0x20 - Channel control This register is used for channel enabling and priority selection. When a channel is disabled, it becomes inactive only when all ongoing requests are finished.

dmac_ch1_extaddr: DMAC_CH1_EXTADDR

0x24 - Channel external address

dmac_ch1_dmalength: DMAC_CH1_DMALENGTH

0x2c - Channel DMA length

dmac_mst_runparams: DMAC_MST_RUNPARAMS

0x78 - DMAC master run-time parameters This register defines all the run-time parameters for the AHB master interface port. These parameters are required for the proper functioning of the EIP-101m AHB master adapter.

dmac_persr: DMAC_PERSR

0x7c - DMAC port error raw status register This register provides the actual status of individual port errors. It also indicates which channel is serviced by an external AHB port (which is frozen by a port error). A port error aborts operations on all serviced channels (channel enable bit is forced to 0) and prevents further transfers via that port until the error is cleared by writing to the DMAC_SWRES register.

dmac_options: DMAC_OPTIONS

0xf8 - DMAC options register These registers contain information regarding the different options configured in this DMAC.

dmac_version: DMAC_VERSION

0xfc - DMAC version register This register contains an indication (or signature) of the EIP type of this DMAC, as well as the hardware version/patch numbers.

key_store_write_area: KEY_STORE_WRITE_AREA

0x400 - Key store write area register This register defines where the keys should be written in the key store RAM. After writing this register, the key store module is ready to receive the keys through a DMA operation. In case the key data transfer triggered an error in the key store, the error will be available in the interrupt status register after the DMA is finished. The key store write-error is asserted when the programmed/selected area is not completely written. This error is also asserted when the DMA operation writes to ram areas that are not selected. The key store RAM is divided into 8 areas of 128 bits. 192-bit keys written in the key store RAM should start on boundaries of 256 bits. This means that writing a 192-bit key to the key store RAM must be done by writing 256 bits of data with the 64 most-significant bits set to 0. These bits are ignored by the AES engine.

key_store_written_area: KEY_STORE_WRITTEN_AREA

0x404 - Key store written area register This register shows which areas of the key store RAM contain valid written keys. When a new key needs to be written to the key store, on a location that is already occupied by a valid key, this key area must be cleared first. This can be done by writing this register before the new key is written to the key store memory. Attempting to write to a key area that already contains a valid key is not allowed and results in an error.

key_store_size: KEY_STORE_SIZE

0x408 - Key store size register This register defines the size of the keys that are written with DMA. This register should be configured before writing to the KEY_STORE_WRITE_AREA register.

key_store_read_area: KEY_STORE_READ_AREA

0x40c - Key store read area register This register selects the key store RAM area from where the key needs to be read that will be used for an AES operation. The operation directly starts after writing this register. When the operation is finished, the status of the key store read operation is available in the interrupt status register. Key store read error is asserted when a RAM area is selected which does not contain valid written key.

aes_key2_0: AES_KEY2_0

0x500 - AES_KEY2_0 / AES_GHASH_H_IN_0 Second Key / GHASH Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register.

aes_key2_1: AES_KEY2_1

0x504 - AES_KEY2_1 / AES_GHASH_H_IN_1 Second Key / GHASH Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register.

aes_key2_2: AES_KEY2_2

0x508 - AES_KEY2_2 / AES_GHASH_H_IN_2 Second Key / GHASH Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register.

aes_key2_3: AES_KEY2_3

0x50c - AES_KEY2_3 / AES_GHASH_H_IN_3 Second Key / GHASH Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register.

aes_key3_0: AES_KEY3_0

0x510 - AES_KEY3_0 / AES_KEY2_4 Third Key / Second Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register.

aes_key3_1: AES_KEY3_1

0x514 - AES_KEY3_1 / AES_KEY2_5 Third Key / Second Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register.

aes_key3_2: AES_KEY3_2

0x518 - AES_KEY3_2 / AES_KEY2_6 Third Key / Second Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register.

aes_key3_3: AES_KEY3_3

0x51c - AES_KEY3_3 / AES_KEY2_7 Third Key / Second Key (internal, but clearable) The following registers are not accessible through the host for reading and writing. They are used to store internally calculated key information and intermediate results. However, when the host performs a write to the any of the respective AES_KEY2_n or AES_KEY3_n addresses, respectively the whole 128-bit AES_KEY2_n or AES_KEY3_n register is cleared to 0s. The AES_GHASH_H_IN_n registers (required for GHASH, which is part of GCM) are mapped to the AES_KEY2_n registers. The (intermediate) authentication result for GCM and CCM is stored in the AES_KEY3_n register.

aes_iv_0: AES_IV_0

0x540 - AES initialization vector registers These registers are used to provide and read the IV from the AES engine.

aes_iv_1: AES_IV_1

0x544 - AES initialization vector registers These registers are used to provide and read the IV from the AES engine.

aes_iv_2: AES_IV_2

0x548 - AES initialization vector registers These registers are used to provide and read the IV from the AES engine.

aes_iv_3: AES_IV_3

0x54c - AES initialization vector registers These registers are used to provide and read the IV from the AES engine.

aes_ctrl: AES_CTRL

0x550 - AES input/output buffer control and mode register This register specifies the AES mode of operation for the EIP-120t. Electronic codebook (ECB) mode is automatically selected if bits [28:5] of this register are all 0.

aes_c_length_0: AES_C_LENGTH_0

0x554 - AES crypto length registers (LSW) These registers are used to write the Length values to the EIP-120t. While processing, the length values decrement to 0. If both lengths are 0, the data stream is finished and a new context is requested. For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need to be processed with the same key. Writing 0 length results in continued data requests until a new context is written. For the other modes (CBC-MAC, GCM, and CCM) no (new) data requests are done if the length decrements to or equals 0. It is advised to write a new length per packet. If the length registers decrement to 0, no new data is processed until a new context or length value is written. When writing a new mode without writing the length registers, the length register values from the previous context is reused.

aes_c_length_1: AES_C_LENGTH_1

0x558 - AES crypto length registers (MSW) These registers are used to write the Length values to the EIP-120t. While processing, the length values decrement to 0. If both lengths are 0, the data stream is finished and a new context is requested. For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need to be processed with the same key. Writing 0 length results in continued data requests until a new context is written. For the other modes (CBC-MAC, GCM and CCM) no (new) data requests are done if the length decrements to or equals 0. It is advised to write a new length per packet. If the length registers decrement to 0, no new data is processed until a new context or length value is written. When writing a new mode without writing the length registers, the length register values from the previous context is reused.

aes_auth_length: AES_AUTH_LENGTH

0x55c - Authentication length register

aes_data_in_out_0: AES_DATA_IN_OUT_0

0x560 - Data input/output registers The data registers are typically accessed through the DMA and not with host writes and/or reads. However, for debugging purposes the data input/output registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface.

aes_data_in_out_1: AES_DATA_IN_OUT_1

0x564 - Data Input/Output Registers The data registers are typically accessed via DMA and not with host writes and/or reads. However, for debugging purposes the Data Input/Output Registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface.

aes_data_in_out_2: AES_DATA_IN_OUT_2

0x568 - Data Input/Output Registers The data registers are typically accessed via DMA and not with host writes and/or reads. However, for debugging purposes the Data Input/Output Registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface.

aes_data_in_out_3: AES_DATA_IN_OUT_3

0x56c - Data Input/Output Registers The data registers are typically accessed via DMA and not with host writes and/or reads. However, for debugging purposes the Data Input/Output Registers can be accessed via host write and read operations. The registers are used to buffer the input/output data blocks to/from the EIP-120t. Note: The data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes (both DMA and host) to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written before starting an operation. The data output buffer contains valid data on completion of an operation. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers; these can be mixed with other host transfers over the external interface.

aes_tag_out_0: AES_TAG_OUT_0

0x570 - TAG registers The tag registers can be accessed via DMA or directly with host reads. These registers buffer the TAG from the EIP-120t. The registers are shared with the intermediate authentication result registers, but cannot be read until the processing is finished. While processing, a read from these registers returns 0s. If an operation does not return a TAG, reading from these registers returns an IV. If an operation returns a TAG plus an IV and both need to be read by the host, the host must first read the TAG followed by the IV. Reading these in reverse order will return the IV twice.

aes_tag_out_1: AES_TAG_OUT_1

0x574 - TAG registers The tag registers can be accessed via DMA or directly with host reads. These registers buffer the TAG from the EIP-120t. The registers are shared with the intermediate authentication result registers, but cannot be read until the processing is finished. While processing, a read from these registers returns 0s. If an operation does not return a TAG, reading from these registers returns an IV. If an operation returns a TAG plus an IV and both need to be read by the host, the host must first read the TAG followed by the IV. Reading these in reverse order returns the IV twice.

aes_tag_out_2: AES_TAG_OUT_2

0x578 - TAG registers The tag registers can be accessed via DMA or directly with host reads. These registers buffer the TAG from the EIP-120t. The registers are shared with the intermediate authentication result registers, but cannot be read until the processing is finished. While processing, a read from these registers returns 0s. If an operation does not return a TAG, reading from these registers returns an IV. If an operation returns a TAG plus an IV and both need to be read by the host, the host must first read the TAG followed by the IV. Reading these in reverse order returns the IV twice.

aes_tag_out_3: AES_TAG_OUT_3

0x57c - TAG registers The tag registers can be accessed via DMA or directly with host reads. These registers buffer the TAG from the EIP-120t. The registers are shared with the intermediate authentication result registers, but cannot be read until the processing is finished. While processing, a read from these registers returns 0s. If an operation does not return a TAG, reading from these registers returns an IV. If an operation returns a TAG plus an IV and both need to be read by the host, the host must first read the TAG followed by the IV. Reading these in reverse order returns the IV twice.

hash_data_in_0: HASH_DATA_IN_0

0x600 - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_data_in_1: HASH_DATA_IN_1

0x604 - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_data_in_2: HASH_DATA_IN_2

0x608 - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_data_in_3: HASH_DATA_IN_3

0x60c - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_data_in_4: HASH_DATA_IN_4

0x610 - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_data_in_5: HASH_DATA_IN_5

0x614 - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_data_in_6: HASH_DATA_IN_6

0x618 - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_data_in_7: HASH_DATA_IN_7

0x61c - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_data_in_8: HASH_DATA_IN_8

0x620 - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_data_in_9: HASH_DATA_IN_9

0x624 - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_data_in_10: HASH_DATA_IN_10

0x628 - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_data_in_11: HASH_DATA_IN_11

0x62c - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_data_in_12: HASH_DATA_IN_12

0x630 - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_data_in_13: HASH_DATA_IN_13

0x634 - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_data_in_14: HASH_DATA_IN_14

0x638 - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_data_in_15: HASH_DATA_IN_15

0x63c - HASH data input registers The data input registers should be used to provide input data to the hash module through the slave interface.

hash_io_buf_ctrl: HASH_IO_BUF_CTRL

0x640 - Input/output buffer control and status register This register pair shares a single address location and contains bits that control and monitor the data flow between the host and the hash engine.

hash_mode_in: HASH_MODE_IN

0x644 - Hash mode register

hash_length_in_l: HASH_LENGTH_IN_L

0x648 - Hash length register

hash_length_in_h: HASH_LENGTH_IN_H

0x64c - Hash length register

hash_digest_a: HASH_DIGEST_A

0x650 - Hash digest registers The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hash_digest_b: HASH_DIGEST_B

0x654 - Hash digest registers The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hash_digest_c: HASH_DIGEST_C

0x658 - Hash digest registers The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hash_digest_d: HASH_DIGEST_D

0x65c - Hash digest registers The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hash_digest_e: HASH_DIGEST_E

0x660 - Hash digest registers The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hash_digest_f: HASH_DIGEST_F

0x664 - Hash digest registers The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hash_digest_g: HASH_DIGEST_G

0x668 - Hash digest registers The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

hash_digest_h: HASH_DIGEST_H

0x66c - Hash digest registers The hash digest registers consist of eight 32-bit registers, named HASH_DIGEST_A to HASH_DIGEST_H. After processing a message, the output digest can be read from these registers. These registers can be written with an intermediate hash result for continued hash operations.

ctrl_alg_sel: CTRL_ALG_SEL

0x700 - Algorithm select This algorithm selection register configures the internal destination of the DMA controller.

ctrl_prot_en: CTRL_PROT_EN

0x704 - Master PROT privileged access enable This register enables the second bit (bit [1]) of the AHB HPROT bus of the AHB master interface when a read action of key(s) is performed on the AHB master interface for writing keys into the store module.

ctrl_sw_reset: CTRL_SW_RESET

0x740 - Software reset

ctrl_int_cfg: CTRL_INT_CFG

0x780 - Interrupt configuration

ctrl_int_en: CTRL_INT_EN

0x784 - Interrupt enable

ctrl_int_clr: CTRL_INT_CLR

0x788 - Interrupt clear

ctrl_int_set: CTRL_INT_SET

0x78c - Interrupt set

ctrl_int_stat: CTRL_INT_STAT

0x790 - Interrupt status

ctrl_options: CTRL_OPTIONS

0x7f8 - Options register

ctrl_version: CTRL_VERSION

0x7fc - Version register