RegisterBlock

bl602_pac::glb

Struct RegisterBlock 

Source 
pub struct RegisterBlock {
Show 73 fields
    pub clk_cfg0: CLK_CFG0,
    pub clk_cfg1: CLK_CFG1,
    pub clk_cfg2: CLK_CFG2,
    pub clk_cfg3: CLK_CFG3,
    pub swrst_cfg0: SWRST_CFG0,
    pub swrst_cfg1: SWRST_CFG1,
    pub swrst_cfg2: SWRST_CFG2,
    pub swrst_cfg3: SWRST_CFG3,
    pub cgen_cfg0: CGEN_CFG0,
    pub cgen_cfg1: CGEN_CFG1,
    pub cgen_cfg2: CGEN_CFG2,
    pub cgen_cfg3: CGEN_CFG3,
    pub mbist_ctl: MBIST_CTL,
    pub mbist_stat: MBIST_STAT,
    pub bmx_cfg1: BMX_CFG1,
    pub bmx_cfg2: BMX_CFG2,
    pub bmx_err_addr: BMX_ERR_ADDR,
    pub bmx_dbg_out: BMX_DBG_OUT,
    pub rsv0: RSV0,
    pub rsv1: RSV1,
    pub rsv2: RSV2,
    pub rsv3: RSV3,
    pub sram_ret: SRAM_RET,
    pub sram_slp: SRAM_SLP,
    pub sram_parm: SRAM_PARM,
    pub seam_misc: SEAM_MISC,
    pub glb_parm: GLB_PARM,
    pub cpu_clk_cfg: CPU_CLK_CFG,
    pub gpadc_32m_src_ctrl: GPADC_32M_SRC_CTRL,
    pub dig32k_wakeup_ctrl: DIG32K_WAKEUP_CTRL,
    pub wifi_bt_coex_ctrl: WIFI_BT_COEX_CTRL,
    pub uart_sig_sel_0: UART_SIG_SEL_0,
    pub dbg_sel_ll: DBG_SEL_LL,
    pub dbg_sel_lh: DBG_SEL_LH,
    pub dbg_sel_hl: DBG_SEL_HL,
    pub dbg_sel_hh: DBG_SEL_HH,
    pub debug: DEBUG,
    pub gpio_cfgctl0: GPIO_CFGCTL0,
    pub gpio_cfgctl1: GPIO_CFGCTL1,
    pub gpio_cfgctl2: GPIO_CFGCTL2,
    pub gpio_cfgctl3: GPIO_CFGCTL3,
    pub gpio_cfgctl4: GPIO_CFGCTL4,
    pub gpio_cfgctl5: GPIO_CFGCTL5,
    pub gpio_cfgctl6: GPIO_CFGCTL6,
    pub gpio_cfgctl7: GPIO_CFGCTL7,
    pub gpio_cfgctl8: GPIO_CFGCTL8,
    pub gpio_cfgctl9: GPIO_CFGCTL9,
    pub gpio_cfgctl10: GPIO_CFGCTL10,
    pub gpio_cfgctl11: GPIO_CFGCTL11,
    pub gpio_cfgctl12: GPIO_CFGCTL12,
    pub gpio_cfgctl13: GPIO_CFGCTL13,
    pub gpio_cfgctl14: GPIO_CFGCTL14,
    pub gpio_cfgctl30: GPIO_CFGCTL30,
    pub gpio_cfgctl31: GPIO_CFGCTL31,
    pub gpio_cfgctl32: GPIO_CFGCTL32,
    pub gpio_cfgctl33: GPIO_CFGCTL33,
    pub gpio_cfgctl34: GPIO_CFGCTL34,
    pub gpio_cfgctl35: GPIO_CFGCTL35,
    pub gpio_int_mask1: GPIO_INT_MASK1,
    pub gpio_int_stat1: GPIO_INT_STAT1,
    pub gpio_int_clr1: GPIO_INT_CLR1,
    pub gpio_int_mode_set1: GPIO_INT_MODE_SET1,
    pub gpio_int_mode_set2: GPIO_INT_MODE_SET2,
    pub gpio_int_mode_set3: GPIO_INT_MODE_SET3,
    pub led_driver: LED_DRIVER,
    pub gpdac_ctrl: GPDAC_CTRL,
    pub gpdac_actrl: GPDAC_ACTRL,
    pub gpdac_bctrl: GPDAC_BCTRL,
    pub gpdac_data: GPDAC_DATA,
    pub tzc_glb_ctrl_0: TZC_GLB_CTRL_0,
    pub tzc_glb_ctrl_1: TZC_GLB_CTRL_1,
    pub tzc_glb_ctrl_2: TZC_GLB_CTRL_2,
    pub tzc_glb_ctrl_3: TZC_GLB_CTRL_3,
    /* private fields */

}
Expand description

Register block

Fields§

§clk_cfg0: CLK_CFG0

0x00 - Clock configuration for processor and bus

§clk_cfg1: CLK_CFG1

0x04 - clk_cfg1.

§clk_cfg2: CLK_CFG2

0x08 - Clock configuration for UART and Flash

§clk_cfg3: CLK_CFG3

0x0c - Clock configuration for I2C and SPI

§swrst_cfg0: SWRST_CFG0

0x10 - swrst_cfg0.

§swrst_cfg1: SWRST_CFG1

0x14 - swrst_cfg1.

§swrst_cfg2: SWRST_CFG2

0x18 - swrst_cfg2.

§swrst_cfg3: SWRST_CFG3

0x1c - swrst_cfg3.

§cgen_cfg0: CGEN_CFG0

0x20 - cgen_cfg0.

§cgen_cfg1: CGEN_CFG1

0x24 - cgen_cfg1.

§cgen_cfg2: CGEN_CFG2

0x28 - cgen_cfg2.

§cgen_cfg3: CGEN_CFG3

0x2c - cgen_cfg3.

§mbist_ctl: MBIST_CTL

0x30 - MBIST_CTL.

§mbist_stat: MBIST_STAT

0x34 - MBIST_STAT.

§bmx_cfg1: BMX_CFG1

0x50 - bmx_cfg1.

§bmx_cfg2: BMX_CFG2

0x54 - bmx_cfg2.

§bmx_err_addr: BMX_ERR_ADDR

0x58 - bmx_err_addr.

§bmx_dbg_out: BMX_DBG_OUT

0x5c - bmx_dbg_out.

§rsv0: RSV0

0x60 - rsv0.

§rsv1: RSV1

0x64 - rsv1.

§rsv2: RSV2

0x68 - rsv2.

§rsv3: RSV3

0x6c - rsv3.

§sram_ret: SRAM_RET

0x70 - sram_ret.

§sram_slp: SRAM_SLP

0x74 - sram_slp.

§sram_parm: SRAM_PARM

0x78 - sram_parm.

§seam_misc: SEAM_MISC

0x7c - seam_misc.

§glb_parm: GLB_PARM

0x80 - glb_parm.

§cpu_clk_cfg: CPU_CLK_CFG

0x90 - CPU_CLK_CFG.

§gpadc_32m_src_ctrl: GPADC_32M_SRC_CTRL

0xa4 - Clock configuration for GPADC

§dig32k_wakeup_ctrl: DIG32K_WAKEUP_CTRL

0xa8 - DIG32K_WAKEUP_CTRL.

§wifi_bt_coex_ctrl: WIFI_BT_COEX_CTRL

0xac - WIFI_BT_COEX_CTRL.

§uart_sig_sel_0: UART_SIG_SEL_0

0xc0 - UART_SIG_SEL_0.

§dbg_sel_ll: DBG_SEL_LL

0xd0 - DBG_SEL_LL.

§dbg_sel_lh: DBG_SEL_LH

0xd4 - DBG_SEL_LH.

§dbg_sel_hl: DBG_SEL_HL

0xd8 - DBG_SEL_HL.

§dbg_sel_hh: DBG_SEL_HH

0xdc - DBG_SEL_HH.

§debug: DEBUG

0xe0 - debug.

§gpio_cfgctl0: GPIO_CFGCTL0

0x100 - GPIO0, GPIO1 configuration

§gpio_cfgctl1: GPIO_CFGCTL1

0x104 - GPIO2, GPIO3 configuration

§gpio_cfgctl2: GPIO_CFGCTL2

0x108 - GPIO4, GPIO5 configuration

§gpio_cfgctl3: GPIO_CFGCTL3

0x10c - GPIO6, GPIO7 configuration

§gpio_cfgctl4: GPIO_CFGCTL4

0x110 - GPIO8, GPIO9 configuration

§gpio_cfgctl5: GPIO_CFGCTL5

0x114 - GPIO10, GPIO11 configuration

§gpio_cfgctl6: GPIO_CFGCTL6

0x118 - GPIO12, GPIO13 configuration

§gpio_cfgctl7: GPIO_CFGCTL7

0x11c - GPIO14, GPIO15 configuration

§gpio_cfgctl8: GPIO_CFGCTL8

0x120 - GPIO16, GPIO17 configuration

§gpio_cfgctl9: GPIO_CFGCTL9

0x124 - GPIO18, GPIO19 configuration

§gpio_cfgctl10: GPIO_CFGCTL10

0x128 - GPIO20, GPIO21 configuration

§gpio_cfgctl11: GPIO_CFGCTL11

0x12c - GPIO22, GPIO23 configuration

§gpio_cfgctl12: GPIO_CFGCTL12

0x130 - GPIO24, GPIO25 configuration

§gpio_cfgctl13: GPIO_CFGCTL13

0x134 - GPIO26, GPIO27 configuration

§gpio_cfgctl14: GPIO_CFGCTL14

0x138 - GPIO28 configuration

§gpio_cfgctl30: GPIO_CFGCTL30

0x180 - Input register for all GPIO pins. Input Enabled bit must be set in configuration register to work.

§gpio_cfgctl31: GPIO_CFGCTL31

0x184 - Reserved according to SDK.

§gpio_cfgctl32: GPIO_CFGCTL32

0x188 - Output register for all GPIO pins. Output Enabled bit must be set in Output Enable register to work.

§gpio_cfgctl33: GPIO_CFGCTL33

0x18c - Reserved according to SDK.

§gpio_cfgctl34: GPIO_CFGCTL34

0x190 - Output enable register for GPIO.

§gpio_cfgctl35: GPIO_CFGCTL35

0x194 - Reserved according to SDK.

§gpio_int_mask1: GPIO_INT_MASK1

0x1a0 - Interrupt masking register. The SDK limits the GPIO pins to < 32 although the docs do not mention more than 28 GPIO pins.

§gpio_int_stat1: GPIO_INT_STAT1

0x1a8 - Interrupt status register. The SDK limits the GPIO pins to < 32 although the docs do not mention more than 28 GPIO pins.

§gpio_int_clr1: GPIO_INT_CLR1

0x1b0 - Interrupt clearing register.

§gpio_int_mode_set1: GPIO_INT_MODE_SET1

0x1c0 - GPIO interrupt trigger and control register for GPIO0-GPIO9.

§gpio_int_mode_set2: GPIO_INT_MODE_SET2

0x1c4 - GPIO interrupt trigger and control register for GPIO10-GPIO19.

§gpio_int_mode_set3: GPIO_INT_MODE_SET3

0x1c8 - GPIO interrupt trigger and control register for GPIO20-GPIO29.

§led_driver: LED_DRIVER

0x224 - led_driver.

§gpdac_ctrl: GPDAC_CTRL

0x308 - gpdac_ctrl.

§gpdac_actrl: GPDAC_ACTRL

0x30c - gpdac_actrl.

§gpdac_bctrl: GPDAC_BCTRL

0x310 - gpdac_bctrl.

§gpdac_data: GPDAC_DATA

0x314 - gpdac_data.

§tzc_glb_ctrl_0: TZC_GLB_CTRL_0

0xf00 - tzc_glb_ctrl_0.

§tzc_glb_ctrl_1: TZC_GLB_CTRL_1

0xf04 - tzc_glb_ctrl_1.

§tzc_glb_ctrl_2: TZC_GLB_CTRL_2

0xf08 - tzc_glb_ctrl_2.

§tzc_glb_ctrl_3: TZC_GLB_CTRL_3

0xf0c - Reserved according to SDK.

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