1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - Clock configuration for processor and bus"]
5 pub clk_cfg0: CLK_CFG0,
6 #[doc = "0x04 - clk_cfg1."]
7 pub clk_cfg1: CLK_CFG1,
8 #[doc = "0x08 - Clock configuration for UART and Flash"]
9 pub clk_cfg2: CLK_CFG2,
10 #[doc = "0x0c - Clock configuration for I2C and SPI"]
11 pub clk_cfg3: CLK_CFG3,
12 #[doc = "0x10 - swrst_cfg0."]
13 pub swrst_cfg0: SWRST_CFG0,
14 #[doc = "0x14 - swrst_cfg1."]
15 pub swrst_cfg1: SWRST_CFG1,
16 #[doc = "0x18 - swrst_cfg2."]
17 pub swrst_cfg2: SWRST_CFG2,
18 #[doc = "0x1c - swrst_cfg3."]
19 pub swrst_cfg3: SWRST_CFG3,
20 #[doc = "0x20 - cgen_cfg0."]
21 pub cgen_cfg0: CGEN_CFG0,
22 #[doc = "0x24 - cgen_cfg1."]
23 pub cgen_cfg1: CGEN_CFG1,
24 #[doc = "0x28 - cgen_cfg2."]
25 pub cgen_cfg2: CGEN_CFG2,
26 #[doc = "0x2c - cgen_cfg3."]
27 pub cgen_cfg3: CGEN_CFG3,
28 #[doc = "0x30 - MBIST_CTL."]
29 pub mbist_ctl: MBIST_CTL,
30 #[doc = "0x34 - MBIST_STAT."]
31 pub mbist_stat: MBIST_STAT,
32 _reserved14: [u8; 0x18],
33 #[doc = "0x50 - bmx_cfg1."]
34 pub bmx_cfg1: BMX_CFG1,
35 #[doc = "0x54 - bmx_cfg2."]
36 pub bmx_cfg2: BMX_CFG2,
37 #[doc = "0x58 - bmx_err_addr."]
38 pub bmx_err_addr: BMX_ERR_ADDR,
39 #[doc = "0x5c - bmx_dbg_out."]
40 pub bmx_dbg_out: BMX_DBG_OUT,
41 #[doc = "0x60 - rsv0."]
42 pub rsv0: RSV0,
43 #[doc = "0x64 - rsv1."]
44 pub rsv1: RSV1,
45 #[doc = "0x68 - rsv2."]
46 pub rsv2: RSV2,
47 #[doc = "0x6c - rsv3."]
48 pub rsv3: RSV3,
49 #[doc = "0x70 - sram_ret."]
50 pub sram_ret: SRAM_RET,
51 #[doc = "0x74 - sram_slp."]
52 pub sram_slp: SRAM_SLP,
53 #[doc = "0x78 - sram_parm."]
54 pub sram_parm: SRAM_PARM,
55 #[doc = "0x7c - seam_misc."]
56 pub seam_misc: SEAM_MISC,
57 #[doc = "0x80 - glb_parm."]
58 pub glb_parm: GLB_PARM,
59 _reserved27: [u8; 0x0c],
60 #[doc = "0x90 - CPU_CLK_CFG."]
61 pub cpu_clk_cfg: CPU_CLK_CFG,
62 _reserved28: [u8; 0x10],
63 #[doc = "0xa4 - Clock configuration for GPADC"]
64 pub gpadc_32m_src_ctrl: GPADC_32M_SRC_CTRL,
65 #[doc = "0xa8 - DIG32K_WAKEUP_CTRL."]
66 pub dig32k_wakeup_ctrl: DIG32K_WAKEUP_CTRL,
67 #[doc = "0xac - WIFI_BT_COEX_CTRL."]
68 pub wifi_bt_coex_ctrl: WIFI_BT_COEX_CTRL,
69 _reserved31: [u8; 0x10],
70 #[doc = "0xc0 - UART_SIG_SEL_0."]
71 pub uart_sig_sel_0: UART_SIG_SEL_0,
72 _reserved32: [u8; 0x0c],
73 #[doc = "0xd0 - DBG_SEL_LL."]
74 pub dbg_sel_ll: DBG_SEL_LL,
75 #[doc = "0xd4 - DBG_SEL_LH."]
76 pub dbg_sel_lh: DBG_SEL_LH,
77 #[doc = "0xd8 - DBG_SEL_HL."]
78 pub dbg_sel_hl: DBG_SEL_HL,
79 #[doc = "0xdc - DBG_SEL_HH."]
80 pub dbg_sel_hh: DBG_SEL_HH,
81 #[doc = "0xe0 - debug."]
82 pub debug: DEBUG,
83 _reserved37: [u8; 0x1c],
84 #[doc = "0x100 - GPIO0, GPIO1 configuration"]
85 pub gpio_cfgctl0: GPIO_CFGCTL0,
86 #[doc = "0x104 - GPIO2, GPIO3 configuration"]
87 pub gpio_cfgctl1: GPIO_CFGCTL1,
88 #[doc = "0x108 - GPIO4, GPIO5 configuration"]
89 pub gpio_cfgctl2: GPIO_CFGCTL2,
90 #[doc = "0x10c - GPIO6, GPIO7 configuration"]
91 pub gpio_cfgctl3: GPIO_CFGCTL3,
92 #[doc = "0x110 - GPIO8, GPIO9 configuration"]
93 pub gpio_cfgctl4: GPIO_CFGCTL4,
94 #[doc = "0x114 - GPIO10, GPIO11 configuration"]
95 pub gpio_cfgctl5: GPIO_CFGCTL5,
96 #[doc = "0x118 - GPIO12, GPIO13 configuration"]
97 pub gpio_cfgctl6: GPIO_CFGCTL6,
98 #[doc = "0x11c - GPIO14, GPIO15 configuration"]
99 pub gpio_cfgctl7: GPIO_CFGCTL7,
100 #[doc = "0x120 - GPIO16, GPIO17 configuration"]
101 pub gpio_cfgctl8: GPIO_CFGCTL8,
102 #[doc = "0x124 - GPIO18, GPIO19 configuration"]
103 pub gpio_cfgctl9: GPIO_CFGCTL9,
104 #[doc = "0x128 - GPIO20, GPIO21 configuration"]
105 pub gpio_cfgctl10: GPIO_CFGCTL10,
106 #[doc = "0x12c - GPIO22, GPIO23 configuration"]
107 pub gpio_cfgctl11: GPIO_CFGCTL11,
108 #[doc = "0x130 - GPIO24, GPIO25 configuration"]
109 pub gpio_cfgctl12: GPIO_CFGCTL12,
110 #[doc = "0x134 - GPIO26, GPIO27 configuration"]
111 pub gpio_cfgctl13: GPIO_CFGCTL13,
112 #[doc = "0x138 - GPIO28 configuration"]
113 pub gpio_cfgctl14: GPIO_CFGCTL14,
114 _reserved52: [u8; 0x44],
115 #[doc = "0x180 - Input register for all GPIO pins. Input Enabled bit must be set in configuration register to work."]
116 pub gpio_cfgctl30: GPIO_CFGCTL30,
117 #[doc = "0x184 - Reserved according to SDK."]
118 pub gpio_cfgctl31: GPIO_CFGCTL31,
119 #[doc = "0x188 - Output register for all GPIO pins. Output Enabled bit must be set in Output Enable register to work."]
120 pub gpio_cfgctl32: GPIO_CFGCTL32,
121 #[doc = "0x18c - Reserved according to SDK."]
122 pub gpio_cfgctl33: GPIO_CFGCTL33,
123 #[doc = "0x190 - Output enable register for GPIO."]
124 pub gpio_cfgctl34: GPIO_CFGCTL34,
125 #[doc = "0x194 - Reserved according to SDK."]
126 pub gpio_cfgctl35: GPIO_CFGCTL35,
127 _reserved58: [u8; 0x08],
128 #[doc = "0x1a0 - Interrupt masking register. The SDK limits the GPIO pins to < 32 although the docs do not mention more than 28 GPIO pins."]
129 pub gpio_int_mask1: GPIO_INT_MASK1,
130 _reserved59: [u8; 0x04],
131 #[doc = "0x1a8 - Interrupt status register. The SDK limits the GPIO pins to < 32 although the docs do not mention more than 28 GPIO pins."]
132 pub gpio_int_stat1: GPIO_INT_STAT1,
133 _reserved60: [u8; 0x04],
134 #[doc = "0x1b0 - Interrupt clearing register."]
135 pub gpio_int_clr1: GPIO_INT_CLR1,
136 _reserved61: [u8; 0x0c],
137 #[doc = "0x1c0 - GPIO interrupt trigger and control register for GPIO0-GPIO9."]
138 pub gpio_int_mode_set1: GPIO_INT_MODE_SET1,
139 #[doc = "0x1c4 - GPIO interrupt trigger and control register for GPIO10-GPIO19."]
140 pub gpio_int_mode_set2: GPIO_INT_MODE_SET2,
141 #[doc = "0x1c8 - GPIO interrupt trigger and control register for GPIO20-GPIO29."]
142 pub gpio_int_mode_set3: GPIO_INT_MODE_SET3,
143 _reserved64: [u8; 0x58],
144 #[doc = "0x224 - led_driver."]
145 pub led_driver: LED_DRIVER,
146 _reserved65: [u8; 0xe0],
147 #[doc = "0x308 - gpdac_ctrl."]
148 pub gpdac_ctrl: GPDAC_CTRL,
149 #[doc = "0x30c - gpdac_actrl."]
150 pub gpdac_actrl: GPDAC_ACTRL,
151 #[doc = "0x310 - gpdac_bctrl."]
152 pub gpdac_bctrl: GPDAC_BCTRL,
153 #[doc = "0x314 - gpdac_data."]
154 pub gpdac_data: GPDAC_DATA,
155 _reserved69: [u8; 0x0be8],
156 #[doc = "0xf00 - tzc_glb_ctrl_0."]
157 pub tzc_glb_ctrl_0: TZC_GLB_CTRL_0,
158 #[doc = "0xf04 - tzc_glb_ctrl_1."]
159 pub tzc_glb_ctrl_1: TZC_GLB_CTRL_1,
160 #[doc = "0xf08 - tzc_glb_ctrl_2."]
161 pub tzc_glb_ctrl_2: TZC_GLB_CTRL_2,
162 #[doc = "0xf0c - Reserved according to SDK."]
163 pub tzc_glb_ctrl_3: TZC_GLB_CTRL_3,
164}
165#[doc = "clk_cfg0 (rw) register accessor: an alias for `Reg<CLK_CFG0_SPEC>`"]
166pub type CLK_CFG0 = crate::Reg<clk_cfg0::CLK_CFG0_SPEC>;
167#[doc = "Clock configuration for processor and bus"]
168pub mod clk_cfg0;
169#[doc = "clk_cfg1 (rw) register accessor: an alias for `Reg<CLK_CFG1_SPEC>`"]
170pub type CLK_CFG1 = crate::Reg<clk_cfg1::CLK_CFG1_SPEC>;
171#[doc = "clk_cfg1."]
172pub mod clk_cfg1;
173#[doc = "clk_cfg2 (rw) register accessor: an alias for `Reg<CLK_CFG2_SPEC>`"]
174pub type CLK_CFG2 = crate::Reg<clk_cfg2::CLK_CFG2_SPEC>;
175#[doc = "Clock configuration for UART and Flash"]
176pub mod clk_cfg2;
177#[doc = "clk_cfg3 (rw) register accessor: an alias for `Reg<CLK_CFG3_SPEC>`"]
178pub type CLK_CFG3 = crate::Reg<clk_cfg3::CLK_CFG3_SPEC>;
179#[doc = "Clock configuration for I2C and SPI"]
180pub mod clk_cfg3;
181#[doc = "swrst_cfg0 (rw) register accessor: an alias for `Reg<SWRST_CFG0_SPEC>`"]
182pub type SWRST_CFG0 = crate::Reg<swrst_cfg0::SWRST_CFG0_SPEC>;
183#[doc = "swrst_cfg0."]
184pub mod swrst_cfg0;
185#[doc = "swrst_cfg1 (rw) register accessor: an alias for `Reg<SWRST_CFG1_SPEC>`"]
186pub type SWRST_CFG1 = crate::Reg<swrst_cfg1::SWRST_CFG1_SPEC>;
187#[doc = "swrst_cfg1."]
188pub mod swrst_cfg1;
189#[doc = "swrst_cfg2 (rw) register accessor: an alias for `Reg<SWRST_CFG2_SPEC>`"]
190pub type SWRST_CFG2 = crate::Reg<swrst_cfg2::SWRST_CFG2_SPEC>;
191#[doc = "swrst_cfg2."]
192pub mod swrst_cfg2;
193#[doc = "swrst_cfg3 (rw) register accessor: an alias for `Reg<SWRST_CFG3_SPEC>`"]
194pub type SWRST_CFG3 = crate::Reg<swrst_cfg3::SWRST_CFG3_SPEC>;
195#[doc = "swrst_cfg3."]
196pub mod swrst_cfg3;
197#[doc = "cgen_cfg0 (rw) register accessor: an alias for `Reg<CGEN_CFG0_SPEC>`"]
198pub type CGEN_CFG0 = crate::Reg<cgen_cfg0::CGEN_CFG0_SPEC>;
199#[doc = "cgen_cfg0."]
200pub mod cgen_cfg0;
201#[doc = "cgen_cfg1 (rw) register accessor: an alias for `Reg<CGEN_CFG1_SPEC>`"]
202pub type CGEN_CFG1 = crate::Reg<cgen_cfg1::CGEN_CFG1_SPEC>;
203#[doc = "cgen_cfg1."]
204pub mod cgen_cfg1;
205#[doc = "cgen_cfg2 (rw) register accessor: an alias for `Reg<CGEN_CFG2_SPEC>`"]
206pub type CGEN_CFG2 = crate::Reg<cgen_cfg2::CGEN_CFG2_SPEC>;
207#[doc = "cgen_cfg2."]
208pub mod cgen_cfg2;
209#[doc = "cgen_cfg3 (rw) register accessor: an alias for `Reg<CGEN_CFG3_SPEC>`"]
210pub type CGEN_CFG3 = crate::Reg<cgen_cfg3::CGEN_CFG3_SPEC>;
211#[doc = "cgen_cfg3."]
212pub mod cgen_cfg3;
213#[doc = "MBIST_CTL (rw) register accessor: an alias for `Reg<MBIST_CTL_SPEC>`"]
214pub type MBIST_CTL = crate::Reg<mbist_ctl::MBIST_CTL_SPEC>;
215#[doc = "MBIST_CTL."]
216pub mod mbist_ctl;
217#[doc = "MBIST_STAT (r) register accessor: an alias for `Reg<MBIST_STAT_SPEC>`"]
218pub type MBIST_STAT = crate::Reg<mbist_stat::MBIST_STAT_SPEC>;
219#[doc = "MBIST_STAT."]
220pub mod mbist_stat;
221#[doc = "bmx_cfg1 (rw) register accessor: an alias for `Reg<BMX_CFG1_SPEC>`"]
222pub type BMX_CFG1 = crate::Reg<bmx_cfg1::BMX_CFG1_SPEC>;
223#[doc = "bmx_cfg1."]
224pub mod bmx_cfg1;
225#[doc = "bmx_cfg2 (rw) register accessor: an alias for `Reg<BMX_CFG2_SPEC>`"]
226pub type BMX_CFG2 = crate::Reg<bmx_cfg2::BMX_CFG2_SPEC>;
227#[doc = "bmx_cfg2."]
228pub mod bmx_cfg2;
229#[doc = "bmx_err_addr (r) register accessor: an alias for `Reg<BMX_ERR_ADDR_SPEC>`"]
230pub type BMX_ERR_ADDR = crate::Reg<bmx_err_addr::BMX_ERR_ADDR_SPEC>;
231#[doc = "bmx_err_addr."]
232pub mod bmx_err_addr;
233#[doc = "bmx_dbg_out (r) register accessor: an alias for `Reg<BMX_DBG_OUT_SPEC>`"]
234pub type BMX_DBG_OUT = crate::Reg<bmx_dbg_out::BMX_DBG_OUT_SPEC>;
235#[doc = "bmx_dbg_out."]
236pub mod bmx_dbg_out;
237#[doc = "rsv0 (rw) register accessor: an alias for `Reg<RSV0_SPEC>`"]
238pub type RSV0 = crate::Reg<rsv0::RSV0_SPEC>;
239#[doc = "rsv0."]
240pub mod rsv0;
241#[doc = "rsv1 (rw) register accessor: an alias for `Reg<RSV1_SPEC>`"]
242pub type RSV1 = crate::Reg<rsv1::RSV1_SPEC>;
243#[doc = "rsv1."]
244pub mod rsv1;
245#[doc = "rsv2 (rw) register accessor: an alias for `Reg<RSV2_SPEC>`"]
246pub type RSV2 = crate::Reg<rsv2::RSV2_SPEC>;
247#[doc = "rsv2."]
248pub mod rsv2;
249#[doc = "rsv3 (rw) register accessor: an alias for `Reg<RSV3_SPEC>`"]
250pub type RSV3 = crate::Reg<rsv3::RSV3_SPEC>;
251#[doc = "rsv3."]
252pub mod rsv3;
253#[doc = "sram_ret (rw) register accessor: an alias for `Reg<SRAM_RET_SPEC>`"]
254pub type SRAM_RET = crate::Reg<sram_ret::SRAM_RET_SPEC>;
255#[doc = "sram_ret."]
256pub mod sram_ret;
257#[doc = "sram_slp (rw) register accessor: an alias for `Reg<SRAM_SLP_SPEC>`"]
258pub type SRAM_SLP = crate::Reg<sram_slp::SRAM_SLP_SPEC>;
259#[doc = "sram_slp."]
260pub mod sram_slp;
261#[doc = "sram_parm (rw) register accessor: an alias for `Reg<SRAM_PARM_SPEC>`"]
262pub type SRAM_PARM = crate::Reg<sram_parm::SRAM_PARM_SPEC>;
263#[doc = "sram_parm."]
264pub mod sram_parm;
265#[doc = "seam_misc (rw) register accessor: an alias for `Reg<SEAM_MISC_SPEC>`"]
266pub type SEAM_MISC = crate::Reg<seam_misc::SEAM_MISC_SPEC>;
267#[doc = "seam_misc."]
268pub mod seam_misc;
269#[doc = "glb_parm (rw) register accessor: an alias for `Reg<GLB_PARM_SPEC>`"]
270pub type GLB_PARM = crate::Reg<glb_parm::GLB_PARM_SPEC>;
271#[doc = "glb_parm."]
272pub mod glb_parm;
273#[doc = "CPU_CLK_CFG (rw) register accessor: an alias for `Reg<CPU_CLK_CFG_SPEC>`"]
274pub type CPU_CLK_CFG = crate::Reg<cpu_clk_cfg::CPU_CLK_CFG_SPEC>;
275#[doc = "CPU_CLK_CFG."]
276pub mod cpu_clk_cfg;
277#[doc = "GPADC_32M_SRC_CTRL (rw) register accessor: an alias for `Reg<GPADC_32M_SRC_CTRL_SPEC>`"]
278pub type GPADC_32M_SRC_CTRL = crate::Reg<gpadc_32m_src_ctrl::GPADC_32M_SRC_CTRL_SPEC>;
279#[doc = "Clock configuration for GPADC"]
280pub mod gpadc_32m_src_ctrl;
281#[doc = "DIG32K_WAKEUP_CTRL (rw) register accessor: an alias for `Reg<DIG32K_WAKEUP_CTRL_SPEC>`"]
282pub type DIG32K_WAKEUP_CTRL = crate::Reg<dig32k_wakeup_ctrl::DIG32K_WAKEUP_CTRL_SPEC>;
283#[doc = "DIG32K_WAKEUP_CTRL."]
284pub mod dig32k_wakeup_ctrl;
285#[doc = "WIFI_BT_COEX_CTRL (rw) register accessor: an alias for `Reg<WIFI_BT_COEX_CTRL_SPEC>`"]
286pub type WIFI_BT_COEX_CTRL = crate::Reg<wifi_bt_coex_ctrl::WIFI_BT_COEX_CTRL_SPEC>;
287#[doc = "WIFI_BT_COEX_CTRL."]
288pub mod wifi_bt_coex_ctrl;
289#[doc = "UART_SIG_SEL_0 (rw) register accessor: an alias for `Reg<UART_SIG_SEL_0_SPEC>`"]
290pub type UART_SIG_SEL_0 = crate::Reg<uart_sig_sel_0::UART_SIG_SEL_0_SPEC>;
291#[doc = "UART_SIG_SEL_0."]
292pub mod uart_sig_sel_0;
293#[doc = "DBG_SEL_LL (rw) register accessor: an alias for `Reg<DBG_SEL_LL_SPEC>`"]
294pub type DBG_SEL_LL = crate::Reg<dbg_sel_ll::DBG_SEL_LL_SPEC>;
295#[doc = "DBG_SEL_LL."]
296pub mod dbg_sel_ll;
297#[doc = "DBG_SEL_LH (rw) register accessor: an alias for `Reg<DBG_SEL_LH_SPEC>`"]
298pub type DBG_SEL_LH = crate::Reg<dbg_sel_lh::DBG_SEL_LH_SPEC>;
299#[doc = "DBG_SEL_LH."]
300pub mod dbg_sel_lh;
301#[doc = "DBG_SEL_HL (rw) register accessor: an alias for `Reg<DBG_SEL_HL_SPEC>`"]
302pub type DBG_SEL_HL = crate::Reg<dbg_sel_hl::DBG_SEL_HL_SPEC>;
303#[doc = "DBG_SEL_HL."]
304pub mod dbg_sel_hl;
305#[doc = "DBG_SEL_HH (rw) register accessor: an alias for `Reg<DBG_SEL_HH_SPEC>`"]
306pub type DBG_SEL_HH = crate::Reg<dbg_sel_hh::DBG_SEL_HH_SPEC>;
307#[doc = "DBG_SEL_HH."]
308pub mod dbg_sel_hh;
309#[doc = "debug (rw) register accessor: an alias for `Reg<DEBUG_SPEC>`"]
310pub type DEBUG = crate::Reg<debug::DEBUG_SPEC>;
311#[doc = "debug."]
312pub mod debug;
313#[doc = "GPIO_CFGCTL0 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL0_SPEC>`"]
314pub type GPIO_CFGCTL0 = crate::Reg<gpio_cfgctl0::GPIO_CFGCTL0_SPEC>;
315#[doc = "GPIO0, GPIO1 configuration"]
316pub mod gpio_cfgctl0;
317#[doc = "GPIO_CFGCTL1 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL1_SPEC>`"]
318pub type GPIO_CFGCTL1 = crate::Reg<gpio_cfgctl1::GPIO_CFGCTL1_SPEC>;
319#[doc = "GPIO2, GPIO3 configuration"]
320pub mod gpio_cfgctl1;
321#[doc = "GPIO_CFGCTL2 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL2_SPEC>`"]
322pub type GPIO_CFGCTL2 = crate::Reg<gpio_cfgctl2::GPIO_CFGCTL2_SPEC>;
323#[doc = "GPIO4, GPIO5 configuration"]
324pub mod gpio_cfgctl2;
325#[doc = "GPIO_CFGCTL3 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL3_SPEC>`"]
326pub type GPIO_CFGCTL3 = crate::Reg<gpio_cfgctl3::GPIO_CFGCTL3_SPEC>;
327#[doc = "GPIO6, GPIO7 configuration"]
328pub mod gpio_cfgctl3;
329#[doc = "GPIO_CFGCTL4 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL4_SPEC>`"]
330pub type GPIO_CFGCTL4 = crate::Reg<gpio_cfgctl4::GPIO_CFGCTL4_SPEC>;
331#[doc = "GPIO8, GPIO9 configuration"]
332pub mod gpio_cfgctl4;
333#[doc = "GPIO_CFGCTL5 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL5_SPEC>`"]
334pub type GPIO_CFGCTL5 = crate::Reg<gpio_cfgctl5::GPIO_CFGCTL5_SPEC>;
335#[doc = "GPIO10, GPIO11 configuration"]
336pub mod gpio_cfgctl5;
337#[doc = "GPIO_CFGCTL6 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL6_SPEC>`"]
338pub type GPIO_CFGCTL6 = crate::Reg<gpio_cfgctl6::GPIO_CFGCTL6_SPEC>;
339#[doc = "GPIO12, GPIO13 configuration"]
340pub mod gpio_cfgctl6;
341#[doc = "GPIO_CFGCTL7 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL7_SPEC>`"]
342pub type GPIO_CFGCTL7 = crate::Reg<gpio_cfgctl7::GPIO_CFGCTL7_SPEC>;
343#[doc = "GPIO14, GPIO15 configuration"]
344pub mod gpio_cfgctl7;
345#[doc = "GPIO_CFGCTL8 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL8_SPEC>`"]
346pub type GPIO_CFGCTL8 = crate::Reg<gpio_cfgctl8::GPIO_CFGCTL8_SPEC>;
347#[doc = "GPIO16, GPIO17 configuration"]
348pub mod gpio_cfgctl8;
349#[doc = "GPIO_CFGCTL9 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL9_SPEC>`"]
350pub type GPIO_CFGCTL9 = crate::Reg<gpio_cfgctl9::GPIO_CFGCTL9_SPEC>;
351#[doc = "GPIO18, GPIO19 configuration"]
352pub mod gpio_cfgctl9;
353#[doc = "GPIO_CFGCTL10 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL10_SPEC>`"]
354pub type GPIO_CFGCTL10 = crate::Reg<gpio_cfgctl10::GPIO_CFGCTL10_SPEC>;
355#[doc = "GPIO20, GPIO21 configuration"]
356pub mod gpio_cfgctl10;
357#[doc = "GPIO_CFGCTL11 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL11_SPEC>`"]
358pub type GPIO_CFGCTL11 = crate::Reg<gpio_cfgctl11::GPIO_CFGCTL11_SPEC>;
359#[doc = "GPIO22, GPIO23 configuration"]
360pub mod gpio_cfgctl11;
361#[doc = "GPIO_CFGCTL12 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL12_SPEC>`"]
362pub type GPIO_CFGCTL12 = crate::Reg<gpio_cfgctl12::GPIO_CFGCTL12_SPEC>;
363#[doc = "GPIO24, GPIO25 configuration"]
364pub mod gpio_cfgctl12;
365#[doc = "GPIO_CFGCTL13 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL13_SPEC>`"]
366pub type GPIO_CFGCTL13 = crate::Reg<gpio_cfgctl13::GPIO_CFGCTL13_SPEC>;
367#[doc = "GPIO26, GPIO27 configuration"]
368pub mod gpio_cfgctl13;
369#[doc = "GPIO_CFGCTL14 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL14_SPEC>`"]
370pub type GPIO_CFGCTL14 = crate::Reg<gpio_cfgctl14::GPIO_CFGCTL14_SPEC>;
371#[doc = "GPIO28 configuration"]
372pub mod gpio_cfgctl14;
373#[doc = "GPIO_CFGCTL30 (r) register accessor: an alias for `Reg<GPIO_CFGCTL30_SPEC>`"]
374pub type GPIO_CFGCTL30 = crate::Reg<gpio_cfgctl30::GPIO_CFGCTL30_SPEC>;
375#[doc = "Input register for all GPIO pins. Input Enabled bit must be set in configuration register to work."]
376pub mod gpio_cfgctl30;
377#[doc = "GPIO_CFGCTL31 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL31_SPEC>`"]
378pub type GPIO_CFGCTL31 = crate::Reg<gpio_cfgctl31::GPIO_CFGCTL31_SPEC>;
379#[doc = "Reserved according to SDK."]
380pub mod gpio_cfgctl31;
381#[doc = "GPIO_CFGCTL32 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL32_SPEC>`"]
382pub type GPIO_CFGCTL32 = crate::Reg<gpio_cfgctl32::GPIO_CFGCTL32_SPEC>;
383#[doc = "Output register for all GPIO pins. Output Enabled bit must be set in Output Enable register to work."]
384pub mod gpio_cfgctl32;
385#[doc = "GPIO_CFGCTL33 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL33_SPEC>`"]
386pub type GPIO_CFGCTL33 = crate::Reg<gpio_cfgctl33::GPIO_CFGCTL33_SPEC>;
387#[doc = "Reserved according to SDK."]
388pub mod gpio_cfgctl33;
389#[doc = "GPIO_CFGCTL34 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL34_SPEC>`"]
390pub type GPIO_CFGCTL34 = crate::Reg<gpio_cfgctl34::GPIO_CFGCTL34_SPEC>;
391#[doc = "Output enable register for GPIO."]
392pub mod gpio_cfgctl34;
393#[doc = "GPIO_CFGCTL35 (rw) register accessor: an alias for `Reg<GPIO_CFGCTL35_SPEC>`"]
394pub type GPIO_CFGCTL35 = crate::Reg<gpio_cfgctl35::GPIO_CFGCTL35_SPEC>;
395#[doc = "Reserved according to SDK."]
396pub mod gpio_cfgctl35;
397#[doc = "GPIO_INT_MASK1 (rw) register accessor: an alias for `Reg<GPIO_INT_MASK1_SPEC>`"]
398pub type GPIO_INT_MASK1 = crate::Reg<gpio_int_mask1::GPIO_INT_MASK1_SPEC>;
399#[doc = "Interrupt masking register. The SDK limits the GPIO pins to < 32 although the docs do not mention more than 28 GPIO pins."]
400pub mod gpio_int_mask1;
401#[doc = "GPIO_INT_STAT1 (r) register accessor: an alias for `Reg<GPIO_INT_STAT1_SPEC>`"]
402pub type GPIO_INT_STAT1 = crate::Reg<gpio_int_stat1::GPIO_INT_STAT1_SPEC>;
403#[doc = "Interrupt status register. The SDK limits the GPIO pins to < 32 although the docs do not mention more than 28 GPIO pins."]
404pub mod gpio_int_stat1;
405#[doc = "GPIO_INT_CLR1 (rw) register accessor: an alias for `Reg<GPIO_INT_CLR1_SPEC>`"]
406pub type GPIO_INT_CLR1 = crate::Reg<gpio_int_clr1::GPIO_INT_CLR1_SPEC>;
407#[doc = "Interrupt clearing register."]
408pub mod gpio_int_clr1;
409#[doc = "GPIO_INT_MODE_SET1 (rw) register accessor: an alias for `Reg<GPIO_INT_MODE_SET1_SPEC>`"]
410pub type GPIO_INT_MODE_SET1 = crate::Reg<gpio_int_mode_set1::GPIO_INT_MODE_SET1_SPEC>;
411#[doc = "GPIO interrupt trigger and control register for GPIO0-GPIO9."]
412pub mod gpio_int_mode_set1;
413#[doc = "GPIO_INT_MODE_SET2 (rw) register accessor: an alias for `Reg<GPIO_INT_MODE_SET2_SPEC>`"]
414pub type GPIO_INT_MODE_SET2 = crate::Reg<gpio_int_mode_set2::GPIO_INT_MODE_SET2_SPEC>;
415#[doc = "GPIO interrupt trigger and control register for GPIO10-GPIO19."]
416pub mod gpio_int_mode_set2;
417#[doc = "GPIO_INT_MODE_SET3 (rw) register accessor: an alias for `Reg<GPIO_INT_MODE_SET3_SPEC>`"]
418pub type GPIO_INT_MODE_SET3 = crate::Reg<gpio_int_mode_set3::GPIO_INT_MODE_SET3_SPEC>;
419#[doc = "GPIO interrupt trigger and control register for GPIO20-GPIO29."]
420pub mod gpio_int_mode_set3;
421#[doc = "led_driver (rw) register accessor: an alias for `Reg<LED_DRIVER_SPEC>`"]
422pub type LED_DRIVER = crate::Reg<led_driver::LED_DRIVER_SPEC>;
423#[doc = "led_driver."]
424pub mod led_driver;
425#[doc = "gpdac_ctrl (rw) register accessor: an alias for `Reg<GPDAC_CTRL_SPEC>`"]
426pub type GPDAC_CTRL = crate::Reg<gpdac_ctrl::GPDAC_CTRL_SPEC>;
427#[doc = "gpdac_ctrl."]
428pub mod gpdac_ctrl;
429#[doc = "gpdac_actrl (rw) register accessor: an alias for `Reg<GPDAC_ACTRL_SPEC>`"]
430pub type GPDAC_ACTRL = crate::Reg<gpdac_actrl::GPDAC_ACTRL_SPEC>;
431#[doc = "gpdac_actrl."]
432pub mod gpdac_actrl;
433#[doc = "gpdac_bctrl (rw) register accessor: an alias for `Reg<GPDAC_BCTRL_SPEC>`"]
434pub type GPDAC_BCTRL = crate::Reg<gpdac_bctrl::GPDAC_BCTRL_SPEC>;
435#[doc = "gpdac_bctrl."]
436pub mod gpdac_bctrl;
437#[doc = "gpdac_data (rw) register accessor: an alias for `Reg<GPDAC_DATA_SPEC>`"]
438pub type GPDAC_DATA = crate::Reg<gpdac_data::GPDAC_DATA_SPEC>;
439#[doc = "gpdac_data."]
440pub mod gpdac_data;
441#[doc = "tzc_glb_ctrl_0 (r) register accessor: an alias for `Reg<TZC_GLB_CTRL_0_SPEC>`"]
442pub type TZC_GLB_CTRL_0 = crate::Reg<tzc_glb_ctrl_0::TZC_GLB_CTRL_0_SPEC>;
443#[doc = "tzc_glb_ctrl_0."]
444pub mod tzc_glb_ctrl_0;
445#[doc = "tzc_glb_ctrl_1 (r) register accessor: an alias for `Reg<TZC_GLB_CTRL_1_SPEC>`"]
446pub type TZC_GLB_CTRL_1 = crate::Reg<tzc_glb_ctrl_1::TZC_GLB_CTRL_1_SPEC>;
447#[doc = "tzc_glb_ctrl_1."]
448pub mod tzc_glb_ctrl_1;
449#[doc = "tzc_glb_ctrl_2 (r) register accessor: an alias for `Reg<TZC_GLB_CTRL_2_SPEC>`"]
450pub type TZC_GLB_CTRL_2 = crate::Reg<tzc_glb_ctrl_2::TZC_GLB_CTRL_2_SPEC>;
451#[doc = "tzc_glb_ctrl_2."]
452pub mod tzc_glb_ctrl_2;
453#[doc = "tzc_glb_ctrl_3 (rw) register accessor: an alias for `Reg<TZC_GLB_CTRL_3_SPEC>`"]
454pub type TZC_GLB_CTRL_3 = crate::Reg<tzc_glb_ctrl_3::TZC_GLB_CTRL_3_SPEC>;
455#[doc = "Reserved according to SDK."]
456pub mod tzc_glb_ctrl_3;