[][src]Struct avr_device::attiny84::adc::admux::MUX_W

pub struct MUX_W<'a> { /* fields omitted */ }

Field MUX writer - Analog Channel and Gain Selection Bits

Implementations

impl<'a> MUX_W<'a>[src]

pub fn variant(self, variant: MUX_A) -> &'a mut W[src]

Writes variant to the field

pub fn adc0(self) -> &'a mut W[src]

Single-ended Input ADC0

pub fn adc1(self) -> &'a mut W[src]

Single-ended Input ADC1

pub fn adc2(self) -> &'a mut W[src]

Single-ended Input ADC2

pub fn adc3(self) -> &'a mut W[src]

Single-ended Input ADC3

pub fn adc4(self) -> &'a mut W[src]

Single-ended Input ADC4

pub fn adc5(self) -> &'a mut W[src]

Single-ended Input ADC5

pub fn adc6(self) -> &'a mut W[src]

Single-ended Input ADC6

pub fn adc7(self) -> &'a mut W[src]

Single-ended Input ADC7

pub fn adc_gnd(self) -> &'a mut W[src]

0V (GND)

pub fn adc_vbg(self) -> &'a mut W[src]

Internal Reference (VBG)

pub fn tempsens(self) -> &'a mut W[src]

Temperature sensor

pub fn adc0_adc0_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC0 Negative ADC0 20x Gain

pub fn adc0_adc1_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC0 Negative ADC1 1x Gain

pub fn adc0_adc1_20x(self) -> &'a mut W[src]

Differential Inputs Postive ADC0 Negative ADC1 20x Gain

pub fn adc0_adc3_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC0 Negative ADC3 1x Gain

pub fn adc0_adc3_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC0 Negative ADC3 20x Gain

pub fn adc1_adc0_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC1 Negative ADC0 1x Gain

pub fn adc1_adc0_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC1 Negative ADC0 20x Gain

pub fn adc1_adc2_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC1 Negative ADC2 1x Gain

pub fn adc1_adc2_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC1 Negative ADC2 20x Gain

pub fn adc1_adc3_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC1 Negative ADC3 1x Gain

pub fn adc1_adc3_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC1 Negative ADC3 20x Gain

pub fn adc2_adc1_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC2 Negative ADC2 1x Gain

pub fn adc2_adc1_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC2 Negative ADC2 20x Gain

pub fn adc2_adc3_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC2 Negative ADC3 1x Gain

pub fn adc2_adc3_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC2 Negative ADC3 20x Gain

pub fn adc3_adc0_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC3 Negative ADC0 1x Gain

pub fn adc3_adc0_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC3 Negative ADC0 20x Gain

pub fn adc3_adc1_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC3 Negative ADC1 1x Gain

pub fn adc3_adc1_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC3 Negative ADC1 20x Gain

pub fn adc3_adc2_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC3 Negative ADC2 1x Gain

pub fn adc3_adc2_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC3 Negative ADC2 20x Gain

pub fn adc3_adc3_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC3 Negative ADC3 1x Gain

pub fn adc3_adc3_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC3 Negative ADC3 20x Gain

pub fn adc3_adc4_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC4 Negative ADC0 1x Gain

pub fn adc3_adc4_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC4 Negative ADC0 20x Gain

pub fn adc3_adc5_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC5 Negative ADC1 1x Gain

pub fn adc3_adc5_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC5 Negative ADC1 20x Gain

pub fn adc3_adc6_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC6 Negative ADC2 1x Gain

pub fn adc3_adc6_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC6 Negative ADC2 20x Gain

pub fn adc3_adc7_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC7 Negative ADC3 1x Gain

pub fn adc3_adc7_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC7 Negative ADC3 20x Gain

pub fn adc4_adc3_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC4 Negative ADC3 1x Gain

pub fn adc4_adc3_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC4 Negative ADC3 20x Gain

pub fn adc4_adc5_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC4 Negative ADC5 1x Gain

pub fn adc4_adc5_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC4 Negative ADC5 20x Gain

pub fn adc5_adc3_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC5 Negative ADC3 1x Gain

pub fn adc5_adc3_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC5 Negative ADC3 20x Gain

pub fn adc5_adc4_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC5 Negative ADC4 1x Gain

pub fn adc5_adc4_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC5 Negative ADC4 20x Gain

pub fn adc5_adc6_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC5 Negative ADC6 1x Gain

pub fn adc5_adc6_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC5 Negative ADC6 20x Gain

pub fn adc6_adc3_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC6 Negative ADC3 1x Gain

pub fn adc6_adc3_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC6 Negative ADC3 20x Gain

pub fn adc6_adc5_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC6 Negative ADC5 1x Gain

pub fn adc6_adc5_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC6 Negative ADC5 20x Gain

pub fn adc6_adc7_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC6 Negative ADC7 1x Gain

pub fn adc6_adc7_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC6 Negative ADC7 20x Gain

pub fn adc7_adc3_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC7 Negative ADC3 1x Gain

pub fn adc7_adc3_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC7 Negative ADC3 20x Gain

pub fn adc7_adc6_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC7 Negative ADC6 1x Gain

pub fn adc7_adc6_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC7 Negative ADC6 20x Gain

pub fn adc7_adc7_1x(self) -> &'a mut W[src]

Differential Inputs Positive ADC7 Negative ADC7 1x Gain

pub fn adc7_adc7_20x(self) -> &'a mut W[src]

Differential Inputs Positive ADC7 Negative ADC7 20x Gain

pub fn bits(self, value: u8) -> &'a mut W[src]

Writes raw bits to the field

Auto Trait Implementations

impl<'a> Send for MUX_W<'a>

impl<'a> Sync for MUX_W<'a>

impl<'a> Unpin for MUX_W<'a>

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.