Enum avr_device::attiny84::adc::admux::MUX_A

#[repr(u8)]pub enum MUX_A {
    ADC0,
    ADC1,
    ADC2,
    ADC3,
    ADC4,
    ADC5,
    ADC6,
    ADC7,
    ADC_GND,
    ADC_VBG,
    TEMPSENS,
    ADC0_ADC0_20X,
    ADC0_ADC1_1X,
    ADC0_ADC1_20X,
    ADC0_ADC3_1X,
    ADC0_ADC3_20X,
    ADC1_ADC0_1X,
    ADC1_ADC0_20X,
    ADC1_ADC2_1X,
    ADC1_ADC2_20X,
    ADC1_ADC3_1X,
    ADC1_ADC3_20X,
    ADC2_ADC1_1X,
    ADC2_ADC1_20X,
    ADC2_ADC3_1X,
    ADC2_ADC3_20X,
    ADC3_ADC0_1X,
    ADC3_ADC0_20X,
    ADC3_ADC1_1X,
    ADC3_ADC1_20X,
    ADC3_ADC2_1X,
    ADC3_ADC2_20X,
    ADC3_ADC3_1X,
    ADC3_ADC3_20X,
    ADC3_ADC4_1X,
    ADC3_ADC4_20X,
    ADC3_ADC5_1X,
    ADC3_ADC5_20X,
    ADC3_ADC6_1X,
    ADC3_ADC6_20X,
    ADC3_ADC7_1X,
    ADC3_ADC7_20X,
    ADC4_ADC3_1X,
    ADC4_ADC3_20X,
    ADC4_ADC5_1X,
    ADC4_ADC5_20X,
    ADC5_ADC3_1X,
    ADC5_ADC3_20X,
    ADC5_ADC4_1X,
    ADC5_ADC4_20X,
    ADC5_ADC6_1X,
    ADC5_ADC6_20X,
    ADC6_ADC3_1X,
    ADC6_ADC3_20X,
    ADC6_ADC5_1X,
    ADC6_ADC5_20X,
    ADC6_ADC7_1X,
    ADC6_ADC7_20X,
    ADC7_ADC3_1X,
    ADC7_ADC3_20X,
    ADC7_ADC6_1X,
    ADC7_ADC6_20X,
    ADC7_ADC7_1X,
    ADC7_ADC7_20X,
}

Analog Channel and Gain Selection Bits

Value on reset: 0

Variants

ADC0

0: Single-ended Input ADC0

ADC1

1: Single-ended Input ADC1

ADC2

2: Single-ended Input ADC2

ADC3

3: Single-ended Input ADC3

ADC4

4: Single-ended Input ADC4

ADC5

5: Single-ended Input ADC5

ADC6

6: Single-ended Input ADC6

ADC7

7: Single-ended Input ADC7

ADC_GND

32: 0V (GND)

ADC_VBG

33: Internal Reference (VBG)

TEMPSENS

34: Temperature sensor

ADC0_ADC0_20X

35: Differential Inputs Positive ADC0 Negative ADC0 20x Gain

ADC0_ADC1_1X

8: Differential Inputs Positive ADC0 Negative ADC1 1x Gain

ADC0_ADC1_20X

9: Differential Inputs Postive ADC0 Negative ADC1 20x Gain

ADC0_ADC3_1X

10: Differential Inputs Positive ADC0 Negative ADC3 1x Gain

ADC0_ADC3_20X

11: Differential Inputs Positive ADC0 Negative ADC3 20x Gain

ADC1_ADC0_1X

40: Differential Inputs Positive ADC1 Negative ADC0 1x Gain

ADC1_ADC0_20X

41: Differential Inputs Positive ADC1 Negative ADC0 20x Gain

ADC1_ADC2_1X

12: Differential Inputs Positive ADC1 Negative ADC2 1x Gain

ADC1_ADC2_20X

13: Differential Inputs Positive ADC1 Negative ADC2 20x Gain

ADC1_ADC3_1X

14: Differential Inputs Positive ADC1 Negative ADC3 1x Gain

ADC1_ADC3_20X

15: Differential Inputs Positive ADC1 Negative ADC3 20x Gain

ADC2_ADC1_1X

44: Differential Inputs Positive ADC2 Negative ADC2 1x Gain

ADC2_ADC1_20X

45: Differential Inputs Positive ADC2 Negative ADC2 20x Gain

ADC2_ADC3_1X

16: Differential Inputs Positive ADC2 Negative ADC3 1x Gain

ADC2_ADC3_20X

17: Differential Inputs Positive ADC2 Negative ADC3 20x Gain

ADC3_ADC0_1X

42: Differential Inputs Positive ADC3 Negative ADC0 1x Gain

ADC3_ADC0_20X

43: Differential Inputs Positive ADC3 Negative ADC0 20x Gain

ADC3_ADC1_1X

46: Differential Inputs Positive ADC3 Negative ADC1 1x Gain

ADC3_ADC1_20X

47: Differential Inputs Positive ADC3 Negative ADC1 20x Gain

ADC3_ADC2_1X

48: Differential Inputs Positive ADC3 Negative ADC2 1x Gain

ADC3_ADC2_20X

49: Differential Inputs Positive ADC3 Negative ADC2 20x Gain

ADC3_ADC3_1X

36: Differential Inputs Positive ADC3 Negative ADC3 1x Gain

ADC3_ADC3_20X

37: Differential Inputs Positive ADC3 Negative ADC3 20x Gain

ADC3_ADC4_1X

18: Differential Inputs Positive ADC4 Negative ADC0 1x Gain

ADC3_ADC4_20X

19: Differential Inputs Positive ADC4 Negative ADC0 20x Gain

ADC3_ADC5_1X

20: Differential Inputs Positive ADC5 Negative ADC1 1x Gain

ADC3_ADC5_20X

21: Differential Inputs Positive ADC5 Negative ADC1 20x Gain

ADC3_ADC6_1X

22: Differential Inputs Positive ADC6 Negative ADC2 1x Gain

ADC3_ADC6_20X

23: Differential Inputs Positive ADC6 Negative ADC2 20x Gain

ADC3_ADC7_1X

24: Differential Inputs Positive ADC7 Negative ADC3 1x Gain

ADC3_ADC7_20X

25: Differential Inputs Positive ADC7 Negative ADC3 20x Gain

ADC4_ADC3_1X

50: Differential Inputs Positive ADC4 Negative ADC3 1x Gain

ADC4_ADC3_20X

51: Differential Inputs Positive ADC4 Negative ADC3 20x Gain

ADC4_ADC5_1X

26: Differential Inputs Positive ADC4 Negative ADC5 1x Gain

ADC4_ADC5_20X

27: Differential Inputs Positive ADC4 Negative ADC5 20x Gain

ADC5_ADC3_1X

52: Differential Inputs Positive ADC5 Negative ADC3 1x Gain

ADC5_ADC3_20X

53: Differential Inputs Positive ADC5 Negative ADC3 20x Gain

ADC5_ADC4_1X

58: Differential Inputs Positive ADC5 Negative ADC4 1x Gain

ADC5_ADC4_20X

59: Differential Inputs Positive ADC5 Negative ADC4 20x Gain

ADC5_ADC6_1X

28: Differential Inputs Positive ADC5 Negative ADC6 1x Gain

ADC5_ADC6_20X

29: Differential Inputs Positive ADC5 Negative ADC6 20x Gain

ADC6_ADC3_1X

54: Differential Inputs Positive ADC6 Negative ADC3 1x Gain

ADC6_ADC3_20X

55: Differential Inputs Positive ADC6 Negative ADC3 20x Gain

ADC6_ADC5_1X

60: Differential Inputs Positive ADC6 Negative ADC5 1x Gain

ADC6_ADC5_20X

61: Differential Inputs Positive ADC6 Negative ADC5 20x Gain

ADC6_ADC7_1X

30: Differential Inputs Positive ADC6 Negative ADC7 1x Gain

ADC6_ADC7_20X

31: Differential Inputs Positive ADC6 Negative ADC7 20x Gain

ADC7_ADC3_1X

56: Differential Inputs Positive ADC7 Negative ADC3 1x Gain

ADC7_ADC3_20X

57: Differential Inputs Positive ADC7 Negative ADC3 20x Gain

ADC7_ADC6_1X

62: Differential Inputs Positive ADC7 Negative ADC6 1x Gain

ADC7_ADC6_20X

63: Differential Inputs Positive ADC7 Negative ADC6 20x Gain

ADC7_ADC7_1X

38: Differential Inputs Positive ADC7 Negative ADC7 1x Gain

ADC7_ADC7_20X

39: Differential Inputs Positive ADC7 Negative ADC7 20x Gain

Trait Implementations

impl Clone for MUX_A

fn clone(&self) -> MUX_A

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for MUX_A

impl Debug for MUX_A

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<MUX_A> for u8

fn from(variant: MUX_A) -> Self

Performs the conversion.

impl PartialEq<MUX_A> for MUX_A

fn eq(&self, other: &MUX_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use]fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl StructuralPartialEq for MUX_A