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DivwEmitter

asmkit::riscv

Trait DivwEmitter 

Source 
pub trait DivwEmitter<T0, T1, T2> {
    // Required method
    fn divw(&mut self, rd: T0, rs1: T1, rs2: T2);
}
Expand description

Signed 32-bit division

Divide the lower 32-bits of register rs1 by the lower 32-bits of register rs2, and store the sign-extended result in rd.

The remainder is discarded.

Division by zero will put -1 into rd.

Division resulting in signed overflow (when most negative number is divided by -1) will put the most negative number into rd;

§Forms

Assembly: divw xd, xs1, xs2 Rust: divw(rd, rs1, rs2)

§Arguments

  • rd — Destination register.
  • rs1 — Source register.
  • rs2 — Source register.

Required Methods§

Source

fn divw(&mut self, rd: T0, rs1: T1, rs2: T2)

Dyn Compatibility§

This trait is dyn compatible.

In older versions of Rust, dyn compatibility was called "object safety".

Implementors§