Struct Assembler

Source

pub struct Assembler<'a> { /* private fields */ }

Implementations§

Source §

pub fn environment(&self) -> &Environment

Returns the environment (arch/mode) this assembler targets.

Source

pub fn is_32bit(&self) -> bool

Tests whether the assembler targets rv32 mode.

Source

pub fn is_64bit(&self) -> bool

Tests whether the assembler targets rv64 mode.

Reserve a nop-filled island for later custom rewriting.

Source

pub fn patchable_j(&mut self, label: Label) -> PatchableSite

Source

pub fn patchable_call(&mut self, label: Label) -> PatchableSite

Source

pub fn patchable_li(&mut self, rd: Gp, imm: impl Into<i64>) -> PatchableBlock

Materialize imm into rd with a fixed-size sequence and a patchable literal.

Layout (RV64): auipc; ld; jal; .dword — the returned block covers the 8-byte literal. Layout (RV32): auipc; lw; jal; .word — the returned block covers the 4-byte literal.

Rewrite with PatchableBlock::repatch_u64 / PatchableBlock::repatch_u32.

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn aes32dsi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
where Self: Aes32DsiEmitter<T0, T1, T2, T3>,

RISC-V aes32dsi instruction.

§Forms

Assembly: aes32dsi xd, xs1, xs2, bs Rust: aes32dsi(rd, rs1, rs2, bs)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
bs — Immediate encoding value.

Source

pub fn aes32dsmi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
where Self: Aes32DsmiEmitter<T0, T1, T2, T3>,

RISC-V aes32dsmi instruction.

§Forms

Assembly: aes32dsmi xd, xs1, xs2, bs Rust: aes32dsmi(rd, rs1, rs2, bs)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
bs — Immediate encoding value.

Source

pub fn aes32esi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
where Self: Aes32EsiEmitter<T0, T1, T2, T3>,

RISC-V aes32esi instruction.

§Forms

Assembly: aes32esi xd, xs1, xs2, bs Rust: aes32esi(rd, rs1, rs2, bs)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
bs — Immediate encoding value.

Source

pub fn aes32esmi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
where Self: Aes32EsmiEmitter<T0, T1, T2, T3>,

RISC-V aes32esmi instruction.

§Forms

Assembly: aes32esmi xd, xs1, xs2, bs Rust: aes32esmi(rd, rs1, rs2, bs)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
bs — Immediate encoding value.

Source

pub fn aes64ds<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Aes64DsEmitter<T0, T1, T2>,

RISC-V aes64ds instruction.

§Forms

Assembly: aes64ds xd, xs1, xs2 Rust: aes64ds(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn aes64dsm<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Aes64DsmEmitter<T0, T1, T2>,

RISC-V aes64dsm instruction.

§Forms

Assembly: aes64dsm xd, xs1, xs2 Rust: aes64dsm(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn aes64es<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Aes64EsEmitter<T0, T1, T2>,

RISC-V aes64es instruction.

§Forms

Assembly: aes64es xd, xs1, xs2 Rust: aes64es(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn aes64esm<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Aes64EsmEmitter<T0, T1, T2>,

RISC-V aes64esm instruction.

§Forms

Assembly: aes64esm xd, xs1, xs2 Rust: aes64esm(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn aes64im<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: Aes64ImEmitter<T0, T1>,

RISC-V aes64im instruction.

§Forms

Assembly: aes64im xd, xs1 Rust: aes64im(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn aes64ks1i<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rnum: T2)
where Self: Aes64Ks1IEmitter<T0, T1, T2>,

RISC-V aes64ks1i instruction.

§Forms

Assembly: aes64ks1i xd, xs1, rnum Rust: aes64ks1i(rd, rs1, rnum)

§Arguments

rd — Destination register.
rs1 — Source register.
rnum — Immediate encoding value.

Source

pub fn aes64ks2<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Aes64Ks2Emitter<T0, T1, T2>,

RISC-V aes64ks2 instruction.

§Forms

Assembly: aes64ks2 xd, xs1, xs2 Rust: aes64ks2(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn amoadd_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoaddBEmitter<T0, T1, T2, T3, T4>,

RISC-V amoadd.b instruction.

§Forms

Assembly: amoadd.b xd, xs1, xs2, aq, rl Rust: amoadd_b(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoadd_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoaddDEmitter<T0, T1, T2, T3, T4>,

Atomic fetch-and-add doubleword

Atomically:

Load the doubleword at address rs1
Write the loaded value into rd
Add the value of register rs2 to the loaded value
Write the sum to the address in rs1

§Forms

Assembly: amoadd.d xd, xs2, (xs1) Rust: amoadd_d(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoadd_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoaddHEmitter<T0, T1, T2, T3, T4>,

RISC-V amoadd.h instruction.

§Forms

Assembly: amoadd.h xd, xs1, xs2, aq, rl Rust: amoadd_h(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoadd_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoaddWEmitter<T0, T1, T2, T3, T4>,

Atomic fetch-and-add word

Atomically:

Load the word at address rs1
Write the sign-extended value into rd
Add the least-significant word of register rs2 to the loaded value
Write the sum to the address in rs1

§Forms

Assembly: amoadd.w xd, xs2, (xrs1) Rust: amoadd_w(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoand_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoandBEmitter<T0, T1, T2, T3, T4>,

RISC-V amoand.b instruction.

§Forms

Assembly: amoand.b xd, xs1, xs2, aq, rl Rust: amoand_b(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoand_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoandDEmitter<T0, T1, T2, T3, T4>,

Atomic fetch-and-and doubleword

Atomically:

Load the doubleword at address rs1
Write the loaded value into rd
AND the value of register rs2 to the loaded value
Write the result to the address in rs1

§Forms

Assembly: amoand.d xd, xs2, (xrs1) Rust: amoand_d(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoand_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoandHEmitter<T0, T1, T2, T3, T4>,

RISC-V amoand.h instruction.

§Forms

Assembly: amoand.h xd, xs1, xs2, aq, rl Rust: amoand_h(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoand_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoandWEmitter<T0, T1, T2, T3, T4>,

Atomic fetch-and-and word

Atomically:

Load the word at address rs1
Write the sign-extended value into rd
AND the least-significant word of register rs2 to the loaded value
Write the result to the address in rs1

§Forms

Assembly: amoand.w xd, xs2, (xrs1) Rust: amoand_w(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amocas_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmocasBEmitter<T0, T1, T2, T3, T4>,

RISC-V amocas.b instruction.

§Forms

Assembly: amocas.b xd, xs1, xs2, aq, rl Rust: amocas_b(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amocas_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmocasDEmitter<T0, T1, T2, T3, T4>,

RISC-V amocas.d instruction.

§Forms

Assembly: amocas.d xd, xs1, xs2, aq, rl Rust: amocas_d(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amocas_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmocasHEmitter<T0, T1, T2, T3, T4>,

RISC-V amocas.h instruction.

§Forms

Assembly: amocas.h xd, xs1, xs2, aq, rl Rust: amocas_h(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amocas_q<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmocasQEmitter<T0, T1, T2, T3, T4>,

RISC-V amocas.q instruction.

§Forms

Assembly: amocas.q xd, xs1, xs2, aq, rl Rust: amocas_q(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amocas_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmocasWEmitter<T0, T1, T2, T3, T4>,

RISC-V amocas.w instruction.

§Forms

Assembly: amocas.w xd, xs1, xs2, aq, rl Rust: amocas_w(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amomax_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxBEmitter<T0, T1, T2, T3, T4>,

RISC-V amomax.b instruction.

§Forms

Assembly: amomax.b xd, xs1, xs2, aq, rl Rust: amomax_b(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amomax_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxDEmitter<T0, T1, T2, T3, T4>,

Atomic MAX doubleword

Atomically:

Load the doubleword at address rs1
Write the loaded value into rd
Signed compare the value of register rs2 to the loaded value, and select the maximum value
Write the maximum to the address in rs1

§Forms

Assembly: amomax.d xd, xs2, (xrs1) Rust: amomax_d(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amomax_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxHEmitter<T0, T1, T2, T3, T4>,

RISC-V amomax.h instruction.

§Forms

Assembly: amomax.h xd, xs1, xs2, aq, rl Rust: amomax_h(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amomax_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxWEmitter<T0, T1, T2, T3, T4>,

Atomic MAX word

Atomically:

Load the word at address rs1
Write the sign-extended value into rd
Signed compare the least-significant word of register rs2 to the loaded value, and select the maximum value
Write the maximum to the address in rs1

§Forms

Assembly: amomax.w xd, xs2, (xrs1) Rust: amomax_w(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amomaxu_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxuBEmitter<T0, T1, T2, T3, T4>,

RISC-V amomaxu.b instruction.

§Forms

Assembly: amomaxu.b xd, xs1, xs2, aq, rl Rust: amomaxu_b(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amomaxu_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxuDEmitter<T0, T1, T2, T3, T4>,

Atomic MAX unsigned doubleword

Atomically:

Load the doubleword at address rs1
Write the loaded value into rd
Unsigned compare the value of register rs2 to the loaded value, and select the maximum value
Write the maximum to the address in rs1

§Forms

Assembly: amomaxu.d xd, xs2, (xrs1) Rust: amomaxu_d(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amomaxu_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxuHEmitter<T0, T1, T2, T3, T4>,

RISC-V amomaxu.h instruction.

§Forms

Assembly: amomaxu.h xd, xs1, xs2, aq, rl Rust: amomaxu_h(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amomaxu_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxuWEmitter<T0, T1, T2, T3, T4>,

Atomic MAX unsigned word

Atomically:

Load the word at address rs1
Write the sign-extended value into rd
Unsigned compare the least-significant word of register rs2 to the loaded value, and select the maximum value
Write the maximum to the address in rs1

§Forms

Assembly: amomaxu.w xd, xs2, (xrs1) Rust: amomaxu_w(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amomin_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmominBEmitter<T0, T1, T2, T3, T4>,

RISC-V amomin.b instruction.

§Forms

Assembly: amomin.b xd, xs1, xs2, aq, rl Rust: amomin_b(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amomin_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmominDEmitter<T0, T1, T2, T3, T4>,

Atomic MIN doubleword

Atomically:

Load the doubleword at address rs1
Write the loaded value into rd
Signed compare the value of register rs2 to the loaded value, and select the minimum value
Write the minimum to the address in rs1

§Forms

Assembly: amomin.d xd, xs2, (xrs1) Rust: amomin_d(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amomin_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmominHEmitter<T0, T1, T2, T3, T4>,

RISC-V amomin.h instruction.

§Forms

Assembly: amomin.h xd, xs1, xs2, aq, rl Rust: amomin_h(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amomin_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmominWEmitter<T0, T1, T2, T3, T4>,

Atomic MIN word

Atomically:

Load the word at address rs1
Write the sign-extended value into rd
Signed compare the least-significant word of register rs2 to the loaded value, and select the minimum value
Write the result to the address in rs1

§Forms

Assembly: amomin.w xd, xs2, (xrs1) Rust: amomin_w(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amominu_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmominuBEmitter<T0, T1, T2, T3, T4>,

RISC-V amominu.b instruction.

§Forms

Assembly: amominu.b xd, xs1, xs2, aq, rl Rust: amominu_b(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amominu_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmominuDEmitter<T0, T1, T2, T3, T4>,

Atomic MIN unsigned doubleword

Atomically:

Load the doubleword at address rs1
Write the loaded value into rd
Unsigned compare the value of register rs2 to the loaded value, and select the minimum value
Write the minimum to the address in rs1

§Forms

Assembly: amominu.d xd, xs2, (xrs1) Rust: amominu_d(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amominu_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmominuHEmitter<T0, T1, T2, T3, T4>,

RISC-V amominu.h instruction.

§Forms

Assembly: amominu.h xd, xs1, xs2, aq, rl Rust: amominu_h(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amominu_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmominuWEmitter<T0, T1, T2, T3, T4>,

Atomic MIN unsigned word

Atomically:

Load the word at address rs1
Write the sign-extended value into rd
Unsigned compare the least-significant word of register rs2 to the loaded word, and select the minimum value
Write the result to the address in rs1

§Forms

Assembly: amominu.w xd, xs2, (xrs1) Rust: amominu_w(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoor_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoorBEmitter<T0, T1, T2, T3, T4>,

RISC-V amoor.b instruction.

§Forms

Assembly: amoor.b xd, xs1, xs2, aq, rl Rust: amoor_b(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoor_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoorDEmitter<T0, T1, T2, T3, T4>,

Atomic fetch-and-or doubleword

Atomically:

Load the doubleword at address rs1
Write the loaded value into rd
OR the value of register rs2 to the loaded value
Write the result to the address in rs1

§Forms

Assembly: amoor.d xd, xs2, (xrs1) Rust: amoor_d(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoor_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoorHEmitter<T0, T1, T2, T3, T4>,

RISC-V amoor.h instruction.

§Forms

Assembly: amoor.h xd, xs1, xs2, aq, rl Rust: amoor_h(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoor_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoorWEmitter<T0, T1, T2, T3, T4>,

Atomic fetch-and-or word

Atomically:

Load the word at address rs1
Write the sign-extended value into rd
OR the least-significant word of register rs2 to the loaded value
Write the result to the address in rs1

§Forms

Assembly: amoor.w xd, xs2, (xrs1) Rust: amoor_w(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoswap_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoswapBEmitter<T0, T1, T2, T3, T4>,

RISC-V amoswap.b instruction.

§Forms

Assembly: amoswap.b xd, xs1, xs2, aq, rl Rust: amoswap_b(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoswap_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoswapDEmitter<T0, T1, T2, T3, T4>,

Atomic SWAP doubleword

Atomically:

Load the doubleword at address rs1
Write the value into rd
Store the value of register rs2 to the address in rs1

§Forms

Assembly: amoswap.d xd, xs2, (xrs1) Rust: amoswap_d(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoswap_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoswapHEmitter<T0, T1, T2, T3, T4>,

RISC-V amoswap.h instruction.

§Forms

Assembly: amoswap.h xd, xs1, xs2, aq, rl Rust: amoswap_h(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoswap_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoswapWEmitter<T0, T1, T2, T3, T4>,

Atomic SWAP word

Atomically:

Load the word at address rs1
Write the sign-extended value into rd
Store the least-significant word of register rs2 to the address in rs1

§Forms

Assembly: amoswap.w xd, xs2, (xrs1) Rust: amoswap_w(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoxor_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoxorBEmitter<T0, T1, T2, T3, T4>,

RISC-V amoxor.b instruction.

§Forms

Assembly: amoxor.b xd, xs1, xs2, aq, rl Rust: amoxor_b(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoxor_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoxorDEmitter<T0, T1, T2, T3, T4>,

Atomic fetch-and-xor doubleword

Atomically:

Load the doubleword at address rs1
Write the loaded value into rd
XOR the value of register rs2 to the loaded value
Write the result to the address in rs1

§Forms

Assembly: amoxor.d xd, xs2, (xrs1) Rust: amoxor_d(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoxor_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoxorHEmitter<T0, T1, T2, T3, T4>,

RISC-V amoxor.h instruction.

§Forms

Assembly: amoxor.h xd, xs1, xs2, aq, rl Rust: amoxor_h(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn amoxor_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoxorWEmitter<T0, T1, T2, T3, T4>,

Atomic fetch-and-xor word

Atomically:

Load the word at address rs1
Write the sign-extended value into rd
XOR the least-significant word of register rs2 to the loaded value
Write the result to the address in rs1

§Forms

Assembly: amoxor.w xd, xs2, (xrs1) Rust: amoxor_w(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn and<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: AndEmitter<T0, T1, T2>,

And

And rs1 with rs2, and store the result in rd

§Forms

Assembly: and xd, xs1, xs2 Rust: and(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn andi<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: AndiEmitter<T0, T1, T2>,

And immediate

And an immediate to the value in rs1, and store the result in rd

§Forms

Assembly: andi xd, xs1, imm Rust: andi(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Source register.
imm — Immediate encoding value.

Source

pub fn andn<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: AndnEmitter<T0, T1, T2>,

AND with inverted operand

This instruction performs the bitwise logical AND operation between rs1 and the bitwise inversion of rs2.

§Forms

Assembly: andn xd, xs1, xs2 Rust: andn(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn auipc<T0, T1>(&mut self, rd: T0, imm: T1)
where Self: AuipcEmitter<T0, T1>,

Add upper immediate to pc

Add an immediate to the current PC.

§Forms

Assembly: auipc xd, imm Rust: auipc(rd, imm)

§Arguments

rd — Destination register.
imm — Immediate encoding value.

Source

pub fn bclr<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: BclrEmitter<T0, T1, T2>,

Single-Bit clear (Register)

This instruction returns rs1 with a single bit cleared at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2.

§Forms

Assembly: bclr xd, xs1, xs2 Rust: bclr(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn bclri<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
where Self: BclriEmitter<T0, T1, T2>,

Single-Bit clear (Immediate)

This instruction returns rs1 with a single bit cleared at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.

§Forms

Assembly: bclri xd, xs1, shamt Rust: bclri(rd, rs1, shamtd)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtd — Immediate encoding value.

Source

pub fn bclri_rv32<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
where Self: BclriRv32Emitter<T0, T1, T2>,

Single-Bit clear (Immediate)

This instruction returns rs1 with a single bit cleared at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.

§Forms

Assembly: bclri.rv32 xd, xs1, shamt Rust: bclri_rv32(rd, rs1, shamtw)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtw — Immediate encoding value.

Source

pub fn beq<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: BeqEmitter<T0, T1, T2>,

Branch if equal

Branch to PC + imm if the value in register rs1 is equal to the value in register rs2.

Raise a MisalignedAddress exception if PC + imm is misaligned.

§Forms

Assembly: beq xs1, xs2, imm Rust: beq(rs1, rs2, imm)

§Arguments

rs1 — Source register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn beqz<T0, T1>(&mut self, rs1: T0, imm: T1)
where Self: BeqzEmitter<T0, T1>,

RISC-V beqz instruction.

§Forms

Assembly: beqz rs1 bimm12lohi Rust: beqz(rs1, imm)

§Arguments

rs1 — Source register.
imm — Immediate encoding value.

Source

pub fn bext<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: BextEmitter<T0, T1, T2>,

Single-Bit extract (Register)

This instruction returns a single bit extracted from rs1 at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2.

§Forms

Assembly: bext xd, xs1, xs2 Rust: bext(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn bexti<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
where Self: BextiEmitter<T0, T1, T2>,

Single-Bit extract (Immediate)

This instruction returns a single bit extracted from rs1 at the index specified in rs2. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.

§Forms

Assembly: bexti xd, xs1, shamt Rust: bexti(rd, rs1, shamtd)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtd — Immediate encoding value.

Source

pub fn bexti_rv32<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
where Self: BextiRv32Emitter<T0, T1, T2>,

Single-Bit extract (Immediate)

This instruction returns a single bit extracted from rs1 at the index specified in rs2. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.

§Forms

Assembly: bexti.rv32 xd, xs1, shamt Rust: bexti_rv32(rd, rs1, shamtw)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtw — Immediate encoding value.

Source

pub fn bge<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: BgeEmitter<T0, T1, T2>,

Branch if greater than or equal

Branch to PC + imm if the signed value in register rs1 is greater than or equal to the signed value in register rs2.

Raise a MisalignedAddress exception if PC + imm is misaligned.

§Forms

Assembly: bge xs1, xs2, imm Rust: bge(rs1, rs2, imm)

§Arguments

rs1 — Source register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn bgeu<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: BgeuEmitter<T0, T1, T2>,

Branch if greater than or equal unsigned

Branch to PC + imm if the unsigned value in register rs1 is greater than or equal to the unsigned value in register rs2.

Raise a MisalignedAddress exception if PC + imm is misaligned.

§Forms

Assembly: bgeu xs1, xs2, imm Rust: bgeu(rs1, rs2, imm)

§Arguments

rs1 — Source register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn bgez<T0, T1>(&mut self, rs1: T0, imm: T1)
where Self: BgezEmitter<T0, T1>,

RISC-V bgez instruction.

§Forms

Assembly: bgez rs1 bimm12lohi Rust: bgez(rs1, imm)

§Arguments

rs1 — Source register.
imm — Immediate encoding value.

Source

pub fn bgt<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: BgtEmitter<T0, T1, T2>,

RISC-V bgt instruction.

§Forms

Assembly: bgt rs1 rs2 bimm12lohi Rust: bgt(rs1, rs2, imm)

§Arguments

rs1 — Source register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn bgtu<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: BgtuEmitter<T0, T1, T2>,

RISC-V bgtu instruction.

§Forms

Assembly: bgtu rs1 rs2 bimm12lohi Rust: bgtu(rs1, rs2, imm)

§Arguments

rs1 — Source register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn bgtz<T0, T1>(&mut self, rs2: T0, imm: T1)
where Self: BgtzEmitter<T0, T1>,

RISC-V bgtz instruction.

§Forms

Assembly: bgtz rs2 bimm12lohi Rust: bgtz(rs2, imm)

§Arguments

rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn binv<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: BinvEmitter<T0, T1, T2>,

Single-Bit invert (Register)

This instruction returns rs1 with a single bit inverted at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2.

§Forms

Assembly: binv xd, xs1, xs2 Rust: binv(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn binvi<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
where Self: BinviEmitter<T0, T1, T2>,

Single-Bit invert (Immediate)

This instruction returns rs1 with a single bit inverted at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.

§Forms

Assembly: binvi xd, xs1, shamt Rust: binvi(rd, rs1, shamtd)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtd — Immediate encoding value.

Source

pub fn binvi_rv32<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
where Self: BinviRv32Emitter<T0, T1, T2>,

Single-Bit invert (Immediate)

This instruction returns rs1 with a single bit inverted at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.

§Forms

Assembly: binvi.rv32 xd, xs1, shamt Rust: binvi_rv32(rd, rs1, shamtw)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtw — Immediate encoding value.

Source

pub fn ble<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: BleEmitter<T0, T1, T2>,

RISC-V ble instruction.

§Forms

Assembly: ble rs1 rs2 bimm12lohi Rust: ble(rs1, rs2, imm)

§Arguments

rs1 — Source register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn bleu<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: BleuEmitter<T0, T1, T2>,

RISC-V bleu instruction.

§Forms

Assembly: bleu rs1 rs2 bimm12lohi Rust: bleu(rs1, rs2, imm)

§Arguments

rs1 — Source register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn blez<T0, T1>(&mut self, rs2: T0, imm: T1)
where Self: BlezEmitter<T0, T1>,

RISC-V blez instruction.

§Forms

Assembly: blez rs2 bimm12lohi Rust: blez(rs2, imm)

§Arguments

rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn blt<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: BltEmitter<T0, T1, T2>,

Branch if less than

Branch to PC + imm if the signed value in register rs1 is less than the signed value in register rs2.

Raise a MisalignedAddress exception if PC + imm is misaligned.

§Forms

Assembly: blt xs1, xs2, imm Rust: blt(rs1, rs2, imm)

§Arguments

rs1 — Source register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn bltu<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: BltuEmitter<T0, T1, T2>,

Branch if less than unsigned

Branch to PC + imm if the unsigned value in register rs1 is less than the unsigned value in register rs2.

Raise a MisalignedAddress exception if PC + imm is misaligned.

§Forms

Assembly: bltu xs1, xs2, imm Rust: bltu(rs1, rs2, imm)

§Arguments

rs1 — Source register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn bltz<T0, T1>(&mut self, rs1: T0, imm: T1)
where Self: BltzEmitter<T0, T1>,

RISC-V bltz instruction.

§Forms

Assembly: bltz rs1 bimm12lohi Rust: bltz(rs1, imm)

§Arguments

rs1 — Source register.
imm — Immediate encoding value.

Source

pub fn bne<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: BneEmitter<T0, T1, T2>,

Branch if not equal

Branch to PC + imm if the value in register rs1 is not equal to the value in register rs2.

Raise a MisalignedAddress exception if PC + imm is misaligned.

§Forms

Assembly: bne xs1, xs2, imm Rust: bne(rs1, rs2, imm)

§Arguments

rs1 — Source register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn bnez<T0, T1>(&mut self, rs1: T0, imm: T1)
where Self: BnezEmitter<T0, T1>,

RISC-V bnez instruction.

§Forms

Assembly: bnez rs1 bimm12lohi Rust: bnez(rs1, imm)

§Arguments

rs1 — Source register.
imm — Immediate encoding value.

Source

pub fn brev8<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: Brev8Emitter<T0, T1>,

Reverse bits in bytes

This instruction reverses the order of the bits in every byte of a register.

§Forms

Assembly: brev8 xd, xs1 Rust: brev8(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn bset<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: BsetEmitter<T0, T1, T2>,

Single-Bit set (Register)

This instruction returns rs1 with a single bit set at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2.

§Forms

Assembly: bset xd, xs1, xs2 Rust: bset(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn bseti<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
where Self: BsetiEmitter<T0, T1, T2>,

Single-Bit set (Immediate)

This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.

§Forms

Assembly: bseti xd, xs1, shamt Rust: bseti(rd, rs1, shamtd)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtd — Immediate encoding value.

Source

pub fn bseti_rv32<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
where Self: BsetiRv32Emitter<T0, T1, T2>,

Single-Bit set (Immediate)

This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.

§Forms

Assembly: bseti.rv32 xd, xs1, shamt Rust: bseti_rv32(rd, rs1, shamtw)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtw — Immediate encoding value.

Source

pub fn c_add<T0, T1>(&mut self, rd: T0, rs2: T1)
where Self: CAddEmitter<T0, T1>,

Add

Add the value in rs2 to rd, and store the result in rd. C.ADD expands into add rd, rd, rs2.

§Forms

Assembly: c.add xd, rs2 Rust: c_add(rd, rs2)

§Arguments

rd — Destination/source register.
rs2 — Instruction operand.

Source

pub fn c_addi<T0, T1>(&mut self, rd: T0, imm: T1)
where Self: CAddiEmitter<T0, T1>,

Add a sign-extended non-zero immediate

C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. C.ADDI expands into addi rd, rd, imm. C.ADDI is only valid when rd ≠ x0 and imm ≠ 0. The code points with rd=x0 encode the C.NOP instruction; the remaining code points with imm=0 encode HINTs.

§Forms

Assembly: c.addi xd, imm Rust: c_addi(rd, imm)

§Arguments

rd — Destination/source register.
imm — Immediate encoding value.

Source

pub fn c_addi16sp<T0>(&mut self, imm: T0)
where Self: CAddi16spEmitter<T0>,

Add a sign-extended non-zero immediate

C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496). C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. It expands into addi x2, x2, nzimm\[9:4\]. C.ADDI16SP is only valid when nzimm ≠ 0; the code point with nzimm=0 is reserved.

§Forms

Assembly: c.addi16sp imm Rust: c_addi16sp(imm)

§Arguments

imm — Immediate encoding value.

Source

pub fn c_addi4spn<T0, T1>(&mut self, rd: T0, imm: T1)
where Self: CAddi4spnEmitter<T0, T1>,

Add a zero-extended non-zero immediate, scaled by 4, to the stack pointer

Adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd’. This instruction is used to generate pointers to stack-allocated variables. It expands to addi rd', x2, nzuimm\[9:2\]. C.ADDI4SPN is only valid when nzuimm ≠ 0; the code points with nzuimm=0 are reserved.

§Forms

Assembly: c.addi4spn xd, imm Rust: c_addi4spn(rd, imm)

§Arguments

rd — Destination register.
imm — Immediate encoding value.

Source

pub fn c_addiw<T0, T1>(&mut self, rd: T0, imm: T1)
where Self: CAddiwEmitter<T0, T1>,

Add a sign-extended non-zero immediate

C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation as C.ADDI but produces a 32-bit result, then sign-extends result to 64 bits. C.ADDIW expands into addiw rd, rd, imm. The immediate can be zero for C.ADDIW, where this corresponds to sext.w rd. C.ADDIW is only valid when rd ≠ x0; the code points with rd=x0 are reserved.

§Forms

Assembly: c.addiw xd, imm Rust: c_addiw(rd, imm)

§Arguments

rd — Destination/source register.
imm — Immediate encoding value.

Source

pub fn c_addw<T0, T1>(&mut self, rd: T0, rs2: T1)
where Self: CAddwEmitter<T0, T1>,

Add word

Add the 32-bit values in rs2 from rd, and store the result in rd. The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15). C.ADDW expands into addw rd, rd, rs2.

§Forms

Assembly: c.addw xd, rs2 Rust: c_addw(rd, rs2)

§Arguments

rd — Destination/source register.
rs2 — Source register.

Source

pub fn c_and<T0, T1>(&mut self, rd: T0, rs2: T1)
where Self: CAndEmitter<T0, T1>,

And

And rd with rs2, and store the result in rd The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15). C.AND expands into and rd, rd, rs2.

§Forms

Assembly: c.and xd, rs2 Rust: c_and(rd, rs2)

§Arguments

rd — Destination/source register.
rs2 — Source register.

Source

pub fn c_andi<T0, T1>(&mut self, rd: T0, imm: T1)
where Self: CAndiEmitter<T0, T1>,

And immediate

And an immediate to the value in rd, and store the result in rd. The rd register index should be used as rd+8 (registers x8-x15). C.ANDI expands into andi rd, rd, imm.

§Forms

Assembly: c.andi xd, imm Rust: c_andi(rd, imm)

§Arguments

rd — Destination/source register.
imm — Immediate encoding value.

Source

pub fn c_beqz<T0, T1>(&mut self, rs1: T0, bimm9lohi: T1)
where Self: CBeqzEmitter<T0, T1>,

Branch if Equal Zero

C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register rs1’ is zero. It expands to beq rs1, x0, offset.

§Forms

Assembly: c.beqz xs1, imm Rust: c_beqz(rs1, bimm9lohi)

§Arguments

rs1 — Source register.
bimm9lohi — Immediate encoding value.

Source

pub fn c_bnez<T0, T1>(&mut self, rs1: T0, bimm9lohi: T1)
where Self: CBnezEmitter<T0, T1>,

Branch if NOT Equal Zero

C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register rs1’ is NOT zero. It expands to beq rs1, x0, offset.

§Forms

Assembly: c.bnez xs1, imm Rust: c_bnez(rs1, bimm9lohi)

§Arguments

rs1 — Source register.
bimm9lohi — Immediate encoding value.

Source

pub fn c_ebreak(&mut self)
where Self: CEbreakEmitter,

Breakpoint exception.

The C.EBREAK instruction is used by debuggers to cause control to be transferred back to a debugging environment. Unless overridden by an external debug environment, C.EBREAK raises a breakpoint exception and performs no other operation.

[NOTE] As described in the C Standard Extension for Compressed Instructions, the c.ebreak instruction performs the same operation as the EBREAK instruction.

EBREAK causes the receiving privilege mode’s epc register to be set to the address of the EBREAK instruction itself, not the address of the following instruction. As EBREAK causes a synchronous exception, it is not considered to retire, and should not increment the minstret CSR.

§Forms

Assembly: c.ebreak " " Rust: c_ebreak()

rd — Destination register.
imm — Immediate encoding value.

mop_t — Instruction operand.

Source

pub fn c_mul<T0, T1>(&mut self, rd: T0, rs2: T1)
where Self: CMulEmitter<T0, T1>,

Multiply, 16-bit encoding

This instruction multiplies XLEN bits of the source operands from rsd’ and rs2’ and writes the lowest XLEN bits of the result to rsd’.

§Forms

Assembly: c.mul xd, xs2 Rust: c_mul(rd, rs2)

§Arguments

rd — Destination/source register.
rs2 — Source register.

Source

pub fn c_mv<T0, T1>(&mut self, rd: T0, rs2: T1)
where Self: CMvEmitter<T0, T1>,

Move Register

C.MV (move register) performs copy of the data in register rs2 to register rd C.MV expands to addi rd, x0, rs2.

§Forms

Assembly: c.mv xd, xs2 Rust: c_mv(rd, rs2)

§Arguments

rd — Destination register.
rs2 — Instruction operand.

Source

pub fn c_nop<T0>(&mut self, imm: T0)
where Self: CNopEmitter<T0>,

Non-operation

C.NOP expands into addi x0, x0, imm.

§Forms

Assembly: c.nop imm Rust: c_nop(imm)

§Arguments

imm — Immediate encoding value.

Source

pub fn c_not<T0>(&mut self, rd: T0)
where Self: CNotEmitter<T0>,

Bitwise not, 16-bit encoding

This instruction takes a single source/destination operand. This instruction takes the one’s complement of rd’/rs1’ and writes the result to the same register.

§Forms

Assembly: c.not xd Rust: c_not(rd)

§Arguments

rd — Destination/source register.

rd — Destination/source register.
imm — Immediate encoding value.

Source

pub fn c_sspopchk_x5(&mut self)
where Self: CSspopchkX5Emitter,

RISC-V c.sspopchk.x5 instruction.

§Forms

Assembly: c.sspopchk.x5 Rust: c_sspopchk_x5()

§Arguments

Source

pub fn c_sspush_x1(&mut self)
where Self: CSspushX1Emitter,

RISC-V c.sspush.x1 instruction.

§Forms

Assembly: c.sspush.x1 Rust: c_sspush_x1()

rd — Destination/source register.

Source

pub fn cbo_clean<T0>(&mut self, rs1: T0)
where Self: CboCleanEmitter<T0>,

Cache Block Clean

Cleans an entire cache block globally throughout the system.

Exactly what happens is coherence protocol-dependent, but in general it is expected that after this operation():

The cache block will be in the clean (not dirty) state in any coherent cache holding a valid copy of the line.
The data will be cleaned to a point such that an incoherent load can observe the cleaned data.

cbo.clean is ordered by FENCE instructions but not FENCE.I or SFENCE.VMA.

<%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%> Both PMP and PMA access control must be the same for all bytes in the block; otherwise, cbo.clean has UNSPECIFIED behavior. <%- end -%>

Clean operations are treated as stores for page and access permissions. If permission checks fail, one of the following exceptions will occur:

<%- if ext?(:H) -%>

Store/AMO Guest-Page Fault if virtual memory translation fails during G-stage translation. <%- end -%>
Store/AMO Page Fault if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
Store/AMO Access Fault if a PMP or PMA access check fails

<%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%> Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP and PMA access checks only need to check a single address in the line. <%- end -%>

CBO operations never raise a misaligned address fault.

§Forms

Assembly: cbo.clean "TODO" Rust: cbo_clean(rs1)

§Arguments

rs1 — Source register.

Source

pub fn cbo_flush<T0>(&mut self, rs1: T0)
where Self: CboFlushEmitter<T0>,

Cache Block Flush

Flushes an entire cache block by cleaning it and then invalidating it in all caches.

cbo.flush is ordered by FENCE instructions but not FENCE.I or SFENCE.VMA.

<%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%> Both PMP and PMA access control must be the same for all bytes in the block; otherwise, cbo.flush has UNSPECIFIED behavior. <%- end -%>

Flush operations are treated as stores for page and access permissions. If permission checks fail, one of the following exceptions will occur:

<%- if ext?(:H) -%>

Store/AMO Guest-Page Fault if virtual memory translation fails during G-stage translation. <%- end -%>
Store/AMO Page Fault if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
Store/AMO Access Fault if a PMP or PMA access check fails.

<%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%> Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP and PMA access checks only need to check a single address in the line. <%- end -%>

CBO operations never raise a misaligned address fault.

§Forms

Assembly: cbo.flush "TODO" Rust: cbo_flush(rs1)

§Arguments

rs1 — Source register.

Source

pub fn cbo_inval<T0>(&mut self, rs1: T0)
where Self: CboInvalEmitter<T0>,

Cache Block Invalidate

Either invalidates or flushes (clean + invalidate) a cache block, depending on the current mode and value of menvcfg.CBIE, senvcfg.CBIE, and/or henvcfg.CBIE.

The instruction is an invalidate (without a clean) when:

In M-mode
In (H)S-mode and menvcfg.CBIE == 11
In U-mode and menvcfg.CBIE == 11 and senvcfg.CBIE == 11
In VS-mode and menvcfg.CBIE == 11 and henvcfg.CBIE == 11
In VU-mode and menvcfg.CBIE == 11 and henvcfg.CBIE == 11 and senvcfg.CBIE == 11

Otherwise, if the instruction does not trap (see Access section), the operation is a flush. The table below summarizes the options.

[%autowidth,cols=“1,1,1,1,1,1,1,1”,separator=“!”] !=== .2+h![.rotate]#menvcfg.CBIE# .2+h! [.rotate]#senvcfg.CBIE# .2+h! [.rotate]#henvcfg.CBIE# 5+^.>h! cbe.inval Operation .^h! M-mode .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode

! 00 ! - ! - ! Invalidate ! Illegal Instruction ! Illegal Instruction ! Virtual Instruction ! Virtual Instruction ! 01 ! 00 ! 00 ! Invalidate ! Flush ! Illegal Instruction ! Virtual Instruction ! Virtual Instruction ! 01 ! 00 ! 01 ! Invalidate ! Flush ! Illegal Instruction ! Flush ! Virtual Instruction ! 01 ! 00 ! 11 ! Invalidate ! Flush ! Illegal Instruction ! Flush ! Virtual Instruction ! 01 ! 01 ! 00 ! Invalidate ! Flush ! Flush ! Virtual Instruction ! Virtual Instruction ! 01 ! 01 ! 01 ! Invalidate ! Flush ! Flush ! Flush ! Flush ! 01 ! 01 ! 11 ! Invalidate ! Flush ! Flush ! Flush ! Flush ! 01 ! 11 ! 00 ! Invalidate ! Flush ! Flush ! Virtual Instruction ! Virtual Instruction ! 01 ! 11 ! 01 ! Invalidate ! Flush ! Flush ! Flush ! Flush ! 01 ! 11 ! 11 ! Invalidate ! Flush ! Flush ! Flush ! Flush ! 11 ! 00 ! 00 ! Invalidate ! Invalidate ! Illegal Instruction ! Virtual Instruction ! Virtual Instruction ! 11 ! 00 ! 01 ! Invalidate ! Invalidate ! Illegal Instruction ! Flush ! Virtual Instruction ! 11 ! 00 ! 11 ! Invalidate ! Invalidate ! Illegal Instruction ! Invalidate ! Virtual Instruction ! 11 ! 01 ! 00 ! Invalidate ! Invalidate ! Flush ! Virtual Instruction ! Virtual Instruction ! 11 ! 01 ! 01 ! Invalidate ! Invalidate ! Flush ! Flush ! Flush ! 11 ! 01 ! 11 ! Invalidate ! Invalidate ! Flush ! Invalidate ! Flush ! 11 ! 11 ! 00 ! Invalidate ! Invalidate ! Invalidate ! Virtual Instruction ! Virtual Instruction ! 11 ! 11 ! 01 ! Invalidate ! Invalidate ! Invalidate ! Flush ! Flush ! 11 ! 11 ! 11 ! Invalidate ! Invalidate ! Invalidate ! Invalidate ! Invalidate !===

cbo.inval is ordered by FENCE instructions but not FENCE.I or SFENCE.VMA.

<%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%> Both PMP and PMA access control must be the same for all bytes in the block; otherwise, cbo.zero has UNSPECIFIED behavior. <%- end -%>

Invalidate operations are treated as stores for page and access permissions. If permission checks fail, one of the following exceptions will occur:

<%- if ext?(:H) -%>

Store/AMO Guest-Page Fault if virtual memory translation fails during G-stage translation. <%- end -%>
Store/AMO Page Fault if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
Store/AMO Access Fault if a PMP or PMA access check fails.

<%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%> Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP and PMA access checks only need to check a single address in the line. <%- end -%>

CBO operations never raise a misaligned address fault.

§Forms

Assembly: cbo.inval "TODO" Rust: cbo_inval(rs1)

§Arguments

rs1 — Source register.

Source

pub fn cbo_zero<T0>(&mut self, rs1: T0)
where Self: CboZeroEmitter<T0>,

Cache Block Zero

Zeros an entire cache block

The block zeroing does not need to be atomic.

cbo.zero is ordered by FENCE instructions but not FENCE.I or SFENCE.VMA.

<%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%> Both PMP and PMA access control must be the same for all bytes in the block; otherwise, cbo.zero has UNSPECIFIED behavior. <%- end -%>

Clean operations are treated as stores for page and access permissions. If permission checks fail, one of the following exceptions will occur:

<%- if ext?(:H) -%>

Store/AMO Guest-Page Fault if virtual memory translation fails during G-stage translation. <%- end -%>
Store/AMO Page Fault if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
Store/AMO Access Fault if a PMP or PMA access check fails.

<%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%> Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP and PMA access checks only need to check a single address in the line. <%- end -%>

CBO operations never raise a misaligned address fault.

§Forms

Assembly: cbo.zero "TODO" Rust: cbo_zero(rs1)

§Arguments

rs1 — Source register.

Source

pub fn clmul<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: ClmulEmitter<T0, T1, T2>,

Carry-less multiply (low-part)

clmul produces the lower half of the 2*XLEN carry-less product

§Forms

Assembly: clmul xd, xs1, xs2 Rust: clmul(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn clmulh<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: ClmulhEmitter<T0, T1, T2>,

Carry-less multiply (high-part)

clmulh produces the upper half of the 2*XLEN carry-less product

§Forms

Assembly: clmulh xd, xs1, xs2 Rust: clmulh(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn clmulr<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: ClmulrEmitter<T0, T1, T2>,

Carry-less multiply (reversed)

clmulr produces bits 2XLEN-2:XLEN-1 of the 2XLEN carry-less product

§Forms

Assembly: clmulr xd, xs1, xs2 Rust: clmulr(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn clz<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: ClzEmitter<T0, T1>,

Count leading zero bits

This instruction counts the number of 0’s before the first 1, starting at the most-significant bit (i.e., XLEN-1) and progressing to bit 0. Accordingly, if the input is 0, the output is XLEN, and if the most-significant bit of the input is a 1, the output is 0.

§Forms

Assembly: clz xd, xs1 Rust: clz(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn clzw<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: ClzwEmitter<T0, T1>,

Count leading zero bits in word

This instruction counts the number of 0’s before the first 1 starting at bit 31 and progressing to bit 0. Accordingly, if the least-significant word is 0, the output is 32, and if the most-significant bit of the word (i.e., bit 31) is a 1, the output is 0.

§Forms

Assembly: clzw xd, xs1 Rust: clzw(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn cm_jalt<T0>(&mut self, index: T0)
where Self: CmJaltEmitter<T0>,

RISC-V cm.jalt instruction.

§Forms

Assembly: cm.jalt c_index Rust: cm_jalt(index)

§Arguments

index — Instruction operand.

Source

pub fn cpop<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: CpopEmitter<T0, T1>,

Count set bits

This instructions counts the number of 1’s (i.e., set bits) in the source register.

§.Software Hint [NOTE]

This operations is known as population count, popcount, sideways sum, bit summation, or Hamming weight.

§The GCC builtin function `__builtin_popcount (unsigned int x)` is implemented by cpop on RV32 and by cpopw on RV64. The GCC builtin function `__builtin_popcountl (unsigned long x)` for LP64 is implemented by cpop on RV64.

§Forms

Assembly: cpop xd, xs1 Rust: cpop(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn cpopw<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: CpopwEmitter<T0, T1>,

Count set bits in word

This instructions counts the number of 1’s (i.e., set bits) in the least-significant word of the source register.

§.Software Hint [NOTE]

This operations is known as population count, popcount, sideways sum, bit summation, or Hamming weight.

§The GCC builtin function `__builtin_popcount (unsigned int x)` is implemented by cpop on RV32 and by cpopw on RV64. The GCC builtin function `__builtin_popcountl (unsigned long x)` for LP64 is implemented by cpop on RV64.

§Forms

Assembly: cpopw xd, xs1 Rust: cpopw(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn csrc<T0, T1>(&mut self, rs1: T0, csr: T1)
where Self: CsrcEmitter<T0, T1>,

RISC-V csrc instruction.

§Forms

Assembly: csrc rs1 csr Rust: csrc(rs1, csr)

§Arguments

rs1 — Source register.
csr — Control and status register number.

Source

pub fn csrci<T0, T1>(&mut self, csr: T0, zimm5: T1)
where Self: CsrciEmitter<T0, T1>,

RISC-V csrci instruction.

§Forms

Assembly: csrci csr zimm5 Rust: csrci(csr, zimm5)

§Arguments

csr — Control and status register number.
zimm5 — Immediate encoding value.

Source

pub fn csrr<T0, T1>(&mut self, rd: T0, csr: T1)
where Self: CsrrEmitter<T0, T1>,

RISC-V csrr instruction.

§Forms

Assembly: csrr rd csr Rust: csrr(rd, csr)

§Arguments

rd — Destination register.
csr — Control and status register number.

Source

pub fn csrrc<T0, T1, T2>(&mut self, rd: T0, rs1: T1, csr: T2)
where Self: CsrrcEmitter<T0, T1, T2>,

RISC-V csrrc instruction.

§Forms

Assembly: csrrc xd, xs1, csr Rust: csrrc(rd, rs1, csr)

§Arguments

rd — Destination register.
rs1 — Source register.
csr — Control and status register number.

Source

pub fn csrrci<T0, T1, T2>(&mut self, rd: T0, csr: T1, zimm5: T2)
where Self: CsrrciEmitter<T0, T1, T2>,

RISC-V csrrci instruction.

§Forms

Assembly: csrrci xd, csr, imm Rust: csrrci(rd, csr, zimm5)

§Arguments

rd — Destination register.
csr — Control and status register number.
zimm5 — Immediate encoding value.

Source

pub fn csrrs<T0, T1, T2>(&mut self, rd: T0, rs1: T1, csr: T2)
where Self: CsrrsEmitter<T0, T1, T2>,

Atomic Read and Set Bits in CSR

Atomically read and set bits in a CSR.

Reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are not explicitly written.

§Forms

Assembly: csrrs xd, xs1, csr Rust: csrrs(rd, rs1, csr)

§Arguments

rd — Destination register.
rs1 — Source register.
csr — Control and status register number.

Source

pub fn csrrsi<T0, T1, T2>(&mut self, rd: T0, csr: T1, zimm5: T2)
where Self: CsrrsiEmitter<T0, T1, T2>,

RISC-V csrrsi instruction.

§Forms

Assembly: csrrsi xd, csr, imm Rust: csrrsi(rd, csr, zimm5)

§Arguments

rd — Destination register.
csr — Control and status register number.
zimm5 — Immediate encoding value.

Source

pub fn csrrw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, csr: T2)
where Self: CsrrwEmitter<T0, T1, T2>,

Atomic Read/Write CSR

Atomically swap values in the CSRs and integer registers.

Read the old value of the CSR, zero-extends the value to XLEN bits, and then write it to integer register rd. The initial value in rs1 is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read.

§Forms

Assembly: csrrw xd, xs1, csr Rust: csrrw(rd, rs1, csr)

§Arguments

rd — Destination register.
rs1 — Source register.
csr — Control and status register number.

Source

pub fn csrrwi<T0, T1, T2>(&mut self, rd: T0, csr: T1, zimm5: T2)
where Self: CsrrwiEmitter<T0, T1, T2>,

Atomic Read/Write CSR Immediate

Atomically write CSR using a 5-bit immediate, and load the previous value into ‘rd’.

Read the old value of the CSR, zero-extends the value to XLEN bits, and then write it to integer register rd. The 5-bit uimm field is zero-extended and written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read.

§Forms

Assembly: csrrwi xd, zimm, csr Rust: csrrwi(rd, csr, zimm5)

§Arguments

rd — Destination register.
csr — Control and status register number.
zimm5 — Immediate encoding value.

Source

pub fn csrs<T0, T1>(&mut self, rs1: T0, csr: T1)
where Self: CsrsEmitter<T0, T1>,

RISC-V csrs instruction.

§Forms

Assembly: csrs rs1 csr Rust: csrs(rs1, csr)

§Arguments

rs1 — Source register.
csr — Control and status register number.

Source

pub fn csrsi<T0, T1>(&mut self, csr: T0, zimm5: T1)
where Self: CsrsiEmitter<T0, T1>,

RISC-V csrsi instruction.

§Forms

Assembly: csrsi csr zimm5 Rust: csrsi(csr, zimm5)

§Arguments

csr — Control and status register number.
zimm5 — Immediate encoding value.

Source

pub fn csrw<T0, T1>(&mut self, rs1: T0, csr: T1)
where Self: CsrwEmitter<T0, T1>,

RISC-V csrw instruction.

§Forms

Assembly: csrw rs1 csr Rust: csrw(rs1, csr)

§Arguments

rs1 — Source register.
csr — Control and status register number.

Source

pub fn csrwi<T0, T1>(&mut self, csr: T0, zimm5: T1)
where Self: CsrwiEmitter<T0, T1>,

RISC-V csrwi instruction.

§Forms

Assembly: csrwi csr zimm5 Rust: csrwi(csr, zimm5)

§Arguments

csr — Control and status register number.
zimm5 — Immediate encoding value.

Source

pub fn ctz<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: CtzEmitter<T0, T1>,

Count trailing zero bits

This instruction counts the number of 0’s before the first 1, starting at the least-significant bit (i.e., 0) and progressing to the most-significant bit (i.e., XLEN-1). Accordingly, if the input is 0, the output is XLEN, and if the least-significant bit of the input is a 1, the output is 0.

§Forms

Assembly: ctz xd, xs1 Rust: ctz(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn ctzw<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: CtzwEmitter<T0, T1>,

Count trailing zero bits in word

This instruction counts the number of 0’s before the first 1, starting at the least-significant bit (i.e., 0) and progressing to the most-significant bit of the least-significant word (i.e., 31). Accordingly, if the least-significant word is 0, the output is 32, and if the least-significant bit of the input is a 1, the output is 0.

§Forms

Assembly: ctzw xd, xs1 Rust: ctzw(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn czero_eqz<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: CzeroEqzEmitter<T0, T1, T2>,

RISC-V czero.eqz instruction.

§Forms

Assembly: czero.eqz xd, xs1, xs2 Rust: czero_eqz(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn czero_nez<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: CzeroNezEmitter<T0, T1, T2>,

RISC-V czero.nez instruction.

§Forms

Assembly: czero.nez xd, xs1, xs2 Rust: czero_nez(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn div<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: DivEmitter<T0, T1, T2>,

Signed division

Divide rs1 by rs2, and store the result in rd. The remainder is discarded.

Division by zero will put -1 into rd.

Division resulting in signed overflow (when most negative number is divided by -1) will put the most negative number into rd;

§Forms

Assembly: div xd, xs1, xs2 Rust: div(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn divu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: DivuEmitter<T0, T1, T2>,

Unsigned division

Divide unsigned values in rs1 by rs2, and store the result in rd.

The remainder is discarded.

If the value in rs2 is zero, rd gets the largest unsigned value.

§Forms

Assembly: divu xd, xs1, xs2 Rust: divu(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn divuw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: DivuwEmitter<T0, T1, T2>,

Unsigned 32-bit division

Divide the unsigned 32-bit values in rs1 and rs2, and store the sign-extended result in rd.

The remainder is discarded.

If the value in rs2 is zero, rd is written with all 1s.

§Forms

Assembly: divuw xd, xs1, xs2 Rust: divuw(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn divw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: DivwEmitter<T0, T1, T2>,

Signed 32-bit division

Divide the lower 32-bits of register rs1 by the lower 32-bits of register rs2, and store the sign-extended result in rd.

The remainder is discarded.

Division by zero will put -1 into rd.

Division resulting in signed overflow (when most negative number is divided by -1) will put the most negative number into rd;

§Forms

Assembly: divw xd, xs1, xs2 Rust: divw(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rm — Rounding mode.

Source

pub fn fadd_s<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
where Self: FaddSEmitter<T0, T1, T2, T3>,

Single-precision floating-point addition

Do the single-precision floating-point addition of fs1 and fs2 and store the result in fd. rm is the dynamic Rounding Mode.

§Forms

Assembly: fadd.s fd, fs1, fs2, rm Rust: fadd_s(rd, rs1, rs2, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rm — Rounding mode.

Source

pub fn fclass_d<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FclassDEmitter<T0, T1>,

RISC-V fclass.d instruction.

§Forms

Assembly: fclass.d xd, xs1 Rust: fclass_d(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fclass_h<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FclassHEmitter<T0, T1>,

RISC-V fclass.h instruction.

§Forms

Assembly: fclass.h xd, xs1 Rust: fclass_h(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fclass_q<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FclassQEmitter<T0, T1>,

RISC-V fclass.q instruction.

§Forms

Assembly: fclass.q xd, qs1 Rust: fclass_q(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fclass_s<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FclassSEmitter<T0, T1>,

Single-precision floating-point classify.

The fclass.s instruction examines the value in floating-point register fs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number. The format of the mask is described in the table below. The corresponding bit in rd will be set if the property is true and clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set. fclass.s does not set the floating-point exception flags.

.Format of result of fclass instruction. [%autowidth,float=“center”,align=“center”,cols=“^,<”,options=“header”,] |=== |rd bit |Meaning |0 |rs1 is latexmath:[$-\infty$]. |1 |rs1 is a negative normal number. |2 |rs1 is a negative subnormal number. |3 |rs1 is latexmath:[$-0$]. |4 |rs1 is latexmath:[$+0$]. |5 |rs1 is a positive subnormal number. |6 |rs1 is a positive normal number. |7 |rs1 is latexmath:[$+\infty$]. |8 |rs1 is a signaling NaN. |9 |rs1 is a quiet NaN. |===

§Forms

Assembly: fclass.s xd, fs1 Rust: fclass_s(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fcvt_bf16_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtBf16SEmitter<T0, T1, T2>,

RISC-V fcvt.bf16.s instruction.

§Forms

Assembly: fcvt.bf16.s xd, xs1, rm Rust: fcvt_bf16_s(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_d_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtDHEmitter<T0, T1, T2>,

RISC-V fcvt.d.h instruction.

§Forms

Assembly: fcvt.d.h xd, xs1, rm Rust: fcvt_d_h(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_d_l<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtDLEmitter<T0, T1, T2>,

RISC-V fcvt.d.l instruction.

§Forms

Assembly: fcvt.d.l xd, xs1, rm Rust: fcvt_d_l(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_d_lu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtDLuEmitter<T0, T1, T2>,

RISC-V fcvt.d.lu instruction.

§Forms

Assembly: fcvt.d.lu xd, xs1, rm Rust: fcvt_d_lu(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_d_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtDQEmitter<T0, T1, T2>,

RISC-V fcvt.d.q instruction.

§Forms

Assembly: fcvt.d.q xd, qs1, rm Rust: fcvt_d_q(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_d_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtDSEmitter<T0, T1, T2>,

RISC-V fcvt.d.s instruction.

§Forms

Assembly: fcvt.d.s xd, xs1, rm Rust: fcvt_d_s(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_d_w<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtDWEmitter<T0, T1, T2>,

RISC-V fcvt.d.w instruction.

§Forms

Assembly: fcvt.d.w xd, xs1, rm Rust: fcvt_d_w(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_d_wu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtDWuEmitter<T0, T1, T2>,

RISC-V fcvt.d.wu instruction.

§Forms

Assembly: fcvt.d.wu xd, xs1, rm Rust: fcvt_d_wu(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_h_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtHDEmitter<T0, T1, T2>,

RISC-V fcvt.h.d instruction.

§Forms

Assembly: fcvt.h.d xd, xs1, rm Rust: fcvt_h_d(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_h_l<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtHLEmitter<T0, T1, T2>,

RISC-V fcvt.h.l instruction.

§Forms

Assembly: fcvt.h.l xd, xs1, rm Rust: fcvt_h_l(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_h_lu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtHLuEmitter<T0, T1, T2>,

RISC-V fcvt.h.lu instruction.

§Forms

Assembly: fcvt.h.lu xd, xs1, rm Rust: fcvt_h_lu(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_h_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtHQEmitter<T0, T1, T2>,

RISC-V fcvt.h.q instruction.

§Forms

Assembly: fcvt.h.q xd, qs1, rm Rust: fcvt_h_q(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_h_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtHSEmitter<T0, T1, T2>,

Convert half-precision float to a single-precision float

Converts a half-precision number in floating-point register fs1 into a single-precision floating-point number in floating-point register fd.

fcvt.h.s rounds according to the rm field.

All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set.

§Forms

Assembly: fcvt.h.s fd, xs1 Rust: fcvt_h_s(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_h_w<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtHWEmitter<T0, T1, T2>,

RISC-V fcvt.h.w instruction.

§Forms

Assembly: fcvt.h.w xd, xs1, rm Rust: fcvt_h_w(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_h_wu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtHWuEmitter<T0, T1, T2>,

RISC-V fcvt.h.wu instruction.

§Forms

Assembly: fcvt.h.wu xd, xs1, rm Rust: fcvt_h_wu(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_l_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtLDEmitter<T0, T1, T2>,

RISC-V fcvt.l.d instruction.

§Forms

Assembly: fcvt.l.d xd, xs1, rm Rust: fcvt_l_d(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_l_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtLHEmitter<T0, T1, T2>,

RISC-V fcvt.l.h instruction.

§Forms

Assembly: fcvt.l.h xd, xs1, rm Rust: fcvt_l_h(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_l_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtLQEmitter<T0, T1, T2>,

RISC-V fcvt.l.q instruction.

§Forms

Assembly: fcvt.l.q xd, qs1, rm Rust: fcvt_l_q(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_l_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtLSEmitter<T0, T1, T2>,

RISC-V fcvt.l.s instruction.

§Forms

Assembly: fcvt.l.s xd, fs1, rm Rust: fcvt_l_s(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_lu_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtLuDEmitter<T0, T1, T2>,

RISC-V fcvt.lu.d instruction.

§Forms

Assembly: fcvt.lu.d xd, xs1, rm Rust: fcvt_lu_d(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_lu_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtLuHEmitter<T0, T1, T2>,

RISC-V fcvt.lu.h instruction.

§Forms

Assembly: fcvt.lu.h xd, xs1, rm Rust: fcvt_lu_h(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_lu_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtLuQEmitter<T0, T1, T2>,

RISC-V fcvt.lu.q instruction.

§Forms

Assembly: fcvt.lu.q qd, hs1, rm Rust: fcvt_lu_q(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_lu_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtLuSEmitter<T0, T1, T2>,

RISC-V fcvt.lu.s instruction.

§Forms

Assembly: fcvt.lu.s xd, fs1, rm Rust: fcvt_lu_s(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_q_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtQDEmitter<T0, T1, T2>,

RISC-V fcvt.q.d instruction.

§Forms

Assembly: fcvt.q.d dd, fs1, rm Rust: fcvt_q_d(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_q_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtQHEmitter<T0, T1, T2>,

RISC-V fcvt.q.h instruction.

§Forms

Assembly: fcvt.q.h hd, qs1, rm Rust: fcvt_q_h(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_q_l<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtQLEmitter<T0, T1, T2>,

RISC-V fcvt.q.l instruction.

§Forms

Assembly: fcvt.q.l qd, xs1, rm Rust: fcvt_q_l(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_q_lu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtQLuEmitter<T0, T1, T2>,

RISC-V fcvt.q.lu instruction.

§Forms

Assembly: fcvt.q.lu qd, xs1, rm Rust: fcvt_q_lu(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_q_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtQSEmitter<T0, T1, T2>,

RISC-V fcvt.q.s instruction.

§Forms

Assembly: fcvt.q.s qd, fs1, rm Rust: fcvt_q_s(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_q_w<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtQWEmitter<T0, T1, T2>,

RISC-V fcvt.q.w instruction.

§Forms

Assembly: fcvt.q.w fd, xs1, rm Rust: fcvt_q_w(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_q_wu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtQWuEmitter<T0, T1, T2>,

RISC-V fcvt.q.wu instruction.

§Forms

Assembly: fcvt.q.wu qd, xs1, rm Rust: fcvt_q_wu(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_s_bf16<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtSBf16Emitter<T0, T1, T2>,

RISC-V fcvt.s.bf16 instruction.

§Forms

Assembly: fcvt.s.bf16 xd, xs1, rm Rust: fcvt_s_bf16(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_s_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtSDEmitter<T0, T1, T2>,

RISC-V fcvt.s.d instruction.

§Forms

Assembly: fcvt.s.d xd, xs1, rm Rust: fcvt_s_d(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_s_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtSHEmitter<T0, T1, T2>,

Convert single-precision float to a half-precision float

Converts a single-precision number in floating-point register fs1 into a half-precision floating-point number in floating-point register fd.

fcvt.s.h will never round, and so the ‘rm’ field is effectively ignored.

§Forms

Assembly: fcvt.s.h fd, xs1 Rust: fcvt_s_h(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_s_l<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtSLEmitter<T0, T1, T2>,

RISC-V fcvt.s.l instruction.

§Forms

Assembly: fcvt.s.l fd, xs1, rm Rust: fcvt_s_l(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_s_lu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtSLuEmitter<T0, T1, T2>,

RISC-V fcvt.s.lu instruction.

§Forms

Assembly: fcvt.s.lu fd, xs1, rm Rust: fcvt_s_lu(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_s_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtSQEmitter<T0, T1, T2>,

RISC-V fcvt.s.q instruction.

§Forms

Assembly: fcvt.s.q fd, qs1, rm Rust: fcvt_s_q(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_s_w<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtSWEmitter<T0, T1, T2>,

Convert signed 32-bit integer to single-precision float

Converts a 32-bit signed integer in integer register rs1 into a floating-point number in floating-point register fd.

All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using fcvt.s.w rd, x0, which will never set any exception flags.

All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set.

§Forms

Assembly: fcvt.s.w fd, xs1 Rust: fcvt_s_w(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_s_wu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtSWuEmitter<T0, T1, T2>,

RISC-V fcvt.s.wu instruction.

§Forms

Assembly: fcvt.s.wu fd, xs1, rm Rust: fcvt_s_wu(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_w_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtWDEmitter<T0, T1, T2>,

RISC-V fcvt.w.d instruction.

§Forms

Assembly: fcvt.w.d xd, xs1, rm Rust: fcvt_w_d(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_w_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtWHEmitter<T0, T1, T2>,

RISC-V fcvt.w.h instruction.

§Forms

Assembly: fcvt.w.h xd, xs1, rm Rust: fcvt_w_h(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_w_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtWQEmitter<T0, T1, T2>,

RISC-V fcvt.w.q instruction.

§Forms

Assembly: fcvt.w.q xd, qs1, rm Rust: fcvt_w_q(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_w_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtWSEmitter<T0, T1, T2>,

Convert single-precision float to integer word to signed 32-bit integer.

Converts a floating-point number in floating-point register fs1 to a signed 32-bit integer indicates integer register rd.

For XLEN >32, fcvt.w.s sign-extends the 32-bit result to the destination register width.

If the rounded result is not representable as a 32-bit signed integer, it is clipped to the nearest value and the invalid flag is set.

The range of valid inputs and behavior for invalid inputs are:

[separator=“!”] !=== ! ! Value

h! Minimum valid input (after rounding) ! -2^31 h! Maximum valid input (after rounding) ! 2^31 - 1 h! Output for out-of-range negative input ! -2^31 h! Output for -∞ ! -2^31 h! Output for out-of-range positive input ! 2^31 - 1 h! Output for +∞ for NaN ! 2^31 - 1 !===

All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using fcvt.s.w rd, x0, which will never set any exception flags.

All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set.

§Forms

Assembly: fcvt.w.s xd, fs1 Rust: fcvt_w_s(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_wu_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtWuDEmitter<T0, T1, T2>,

RISC-V fcvt.wu.d instruction.

§Forms

Assembly: fcvt.wu.d xd, xs1, rm Rust: fcvt_wu_d(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_wu_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtWuHEmitter<T0, T1, T2>,

RISC-V fcvt.wu.h instruction.

§Forms

Assembly: fcvt.wu.h xd, xs1, rm Rust: fcvt_wu_h(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_wu_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtWuQEmitter<T0, T1, T2>,

RISC-V fcvt.wu.q instruction.

§Forms

Assembly: fcvt.wu.q xd, xs1, rm Rust: fcvt_wu_q(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvt_wu_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FcvtWuSEmitter<T0, T1, T2>,

RISC-V fcvt.wu.s instruction.

§Forms

Assembly: fcvt.wu.s xd, fs1, rm Rust: fcvt_wu_s(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fcvtmod_w_d<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FcvtmodWDEmitter<T0, T1>,

RISC-V fcvtmod.w.d instruction.

§Forms

Assembly: fcvtmod.w.d xd, xs1 Rust: fcvtmod_w_d(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fdiv_d<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
where Self: FdivDEmitter<T0, T1, T2, T3>,

RISC-V fdiv.d instruction.

§Forms

Assembly: fdiv.d xd, xs1, xs2, rm Rust: fdiv_d(rd, rs1, rs2, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rm — Rounding mode.

Source

pub fn fdiv_h<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
where Self: FdivHEmitter<T0, T1, T2, T3>,

RISC-V fdiv.h instruction.

§Forms

Assembly: fdiv.h xd, xs1, xs2, rm Rust: fdiv_h(rd, rs1, rs2, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rm — Rounding mode.

Source

pub fn fdiv_q<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
where Self: FdivQEmitter<T0, T1, T2, T3>,

RISC-V fdiv.q instruction.

§Forms

Assembly: fdiv.q qd, qs1, qs2, rm Rust: fdiv_q(rd, rs1, rs2, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rm — Rounding mode.

Source

pub fn fdiv_s<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
where Self: FdivSEmitter<T0, T1, T2, T3>,

RISC-V fdiv.s instruction.

§Forms

Assembly: fdiv.s fd, fs1, fs2, rm Rust: fdiv_s(rd, rs1, rs2, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rm — Rounding mode.

Source

pub fn fence<T0, T1, T2, T3, T4>( &mut self, fm: T0, pred: T1, succ: T2, rs1: T3, rd: T4, )
where Self: FenceEmitter<T0, T1, T2, T3, T4>,

Memory ordering fence

Orders memory operations.

The fence instruction is used to order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors. Any combination of device input (I), device output (O), memory reads (R), and memory writes (W) may be ordered with respect to any combination of the same. Informally, no other RISC-V hart or external device can observe any operation in the successor set following a fence before any operation in the predecessor set preceding the fence.

The predecessor and successor fields have the same format to specify operation types:

[%autowidth] |=== 4+| pred 4+| succ

| 27 | 26 |25 | 24 | 23 | 22 | 21| 20 | PI | PO |PR | PW | SI | SO |SR | SW |===

When the mode field fm is 0001 and both the predecessor and successor sets are ‘RW’, then the instruction acts as a special-case fence.tso. fence.tso orders all load operations in its predecessor set before all memory operations in its successor set, and all store operations in its predecessor set before all store operations in its successor set. This leaves non-AMO store operations in the ’fence.tso’s predecessor set unordered with non-AMO loads in its successor set.

When mode field fm is not 0001, or when mode field fm is 0001 but the pred and succ fields are not both ‘RW’ (0x3), then the fence acts as a baseline fence (e.g., fm is effectively 0000). This is unaffected by the FIOM bits, described below (implicit promotion does not change how fence.tso is decoded).

The rs1 and rd fields are unused and ignored.

In modes other than M-mode, fence is further affected by menvcfg.FIOM, senvcfg.FIOM<% if ext?(:H) %>, and/or henvcfg.FIOM<% end %> as follows:

.Effective PR/PW/SR/SW in (H)S-mode [%autowidth,cols=“,,,”,options=“header”,separator=“!”] !=== ! [.rotate]#menvcfg.FIOM# ! pred.PI + pred.PO + succ.SI + succ.SO ! -> + -> + -> + -> ! effective PR + effective PW + effective SR + effective SW

! 0 ! - ! ! from encoding ! 1 ! 0 ! ! from encoding ! 1 ! 1 ! ! 1 !===

.Effective PR/PW/SR/SW in U-mode [%autowidth,options=“header”,separator=“!”,cols=“,,,,”] !=== ! [.rotate]#menvcfg.FIOM# ! [.rotate]#senvcfg.FIOM# ! pred.PI + pred.PO + succ.SI + succ.SO ! -> + -> + -> + -> ! effective PR + effective PW + effective SR + effective SW

! 0 ! 0 ! - ! ! from encoding ! 0 ! 1 ! 0 ! ! from encoding ! 0 ! 1 ! 1 ! ! 1 ! 1 ! - ! 0 ! ! from encoding ! 1 ! - ! 1 ! ! 1 !===

<%- if ext?(:H) -%> .Effective PR/PW/SR/SW in VS-mode and VU-mode [%autowidth,options=“header”,separator=“!”,cols=“,,,,”] !=== ! [.rotate]#menvcfg.FIOM# ! [.rotate]#henvcfg.FIOM# ! pred.PI + pred.PO + succ.SI + succ.SO ! -> + -> + -> + -> ! effective PR + effective PW + effective SR + effective SW

! 0 ! 0 ! - ! ! from encoding ! 0 ! 1 ! 0 ! ! from encoding ! 0 ! 1 ! 1 ! ! 1 ! 1 ! - ! 0 ! ! from encoding ! 1 ! - ! 1 ! ! 1 !=== <%- end -%>

§Forms

Assembly: fence "TODO" Rust: fence(fm, pred, succ, rs1, rd)

§Arguments

fm — Immediate encoding value.
pred — Immediate encoding value.
succ — Immediate encoding value.
rs1 — Source register.
rd — Destination/source register.

Source

pub fn fence_i(&mut self)
where Self: FenceIEmitter,

Instruction fence

The FENCE.I instruction is used to synchronize the instruction and data streams. RISC-V does not guarantee that stores to instruction memory will be made visible to instruction fetches on a RISC-V hart until that hart executes a FENCE.I instruction. A FENCE.I instruction ensures that a subsequent instruction fetch on a RISC-V hart will see any previous data stores already visible to the same RISC-V hart. FENCE.I does not ensure that other RISC-V harts’ instruction fetches will observe the local hart’s stores in a multiprocessor system. To make a store to instruction memory visible to all RISC-V harts, the writing hart also has to execute a data FENCE before requesting that all remote RISC-V harts execute a FENCE.I.

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn feq_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FeqHEmitter<T0, T1, T2>,

RISC-V feq.h instruction.

§Forms

Assembly: feq.h xd, xs1, xs2 Rust: feq_h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn feq_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FeqQEmitter<T0, T1, T2>,

RISC-V feq.q instruction.

§Forms

Assembly: feq.q xd, qs1, qs2 Rust: feq_q(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn feq_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FeqSEmitter<T0, T1, T2>,

Single-precision floating-point equal

Writes 1 to rd if fs1 and fs2 are equal, and 0 otherwise.

If either operand is NaN, the result is 0 (not equal). If either operand is a signaling NaN, the invalid flag is set.

Positive zero is considered equal to negative zero.

§Forms

Assembly: feq.s xd, fs1, fs2 Rust: feq_s(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fld<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: FldEmitter<T0, T1, T2>,

RISC-V fld instruction.

§Forms

Assembly: fld xd, xs1, imm Rust: fld(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Memory base register.
imm — Immediate encoding value.

Source

pub fn fle_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FleDEmitter<T0, T1, T2>,

RISC-V fle.d instruction.

§Forms

Assembly: fle.d xd, xs1, xs2 Rust: fle_d(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fle_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FleHEmitter<T0, T1, T2>,

RISC-V fle.h instruction.

§Forms

Assembly: fle.h xd, xs1, xs2 Rust: fle_h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fle_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FleQEmitter<T0, T1, T2>,

RISC-V fle.q instruction.

§Forms

Assembly: fle.q xd, qs1, qs2 Rust: fle_q(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fle_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FleSEmitter<T0, T1, T2>,

Single-precision floating-point less than or equal

Writes 1 to rd if fs1 is less than or equal to fs2, and 0 otherwise.

If either operand is NaN, the result is 0 (not equal). If either operand is a NaN (signaling or quiet), the invalid flag is set.

Positive zero and negative zero are considered equal.

§Forms

Assembly: fle.s xd, fs1, fs2 Rust: fle_s(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fleq_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FleqDEmitter<T0, T1, T2>,

RISC-V fleq.d instruction.

§Forms

Assembly: fleq.d xd, xs1, xs2 Rust: fleq_d(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fleq_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FleqHEmitter<T0, T1, T2>,

RISC-V fleq.h instruction.

§Forms

Assembly: fleq.h xd, xs1, xs2 Rust: fleq_h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fleq_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FleqQEmitter<T0, T1, T2>,

RISC-V fleq.q instruction.

§Forms

Assembly: fleq.q xd, qs1, qs2 Rust: fleq_q(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fleq_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FleqSEmitter<T0, T1, T2>,

RISC-V fleq.s instruction.

§Forms

Assembly: fleq.s xd, fs1, fs2 Rust: fleq_s(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn flh<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: FlhEmitter<T0, T1, T2>,

Half-precision floating-point load

The flh instruction loads a single-precision floating-point value from memory at address rs1 + imm into floating-point register rd.

flh does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

flh is only guaranteed to execute atomically if the effective address is naturally aligned.

§Forms

Assembly: flh fd, imm(xs1) Rust: flh(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Memory base register.
imm — Immediate encoding value.

Source

pub fn fli_d<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FliDEmitter<T0, T1>,

RISC-V fli.d instruction.

§Forms

Assembly: fli.d xd, xs1 Rust: fli_d(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fli_h<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FliHEmitter<T0, T1>,

RISC-V fli.h instruction.

§Forms

Assembly: fli.h xd, xs1 Rust: fli_h(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fli_q<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FliQEmitter<T0, T1>,

RISC-V fli.q instruction.

§Forms

Assembly: fli.q fd, qs1 Rust: fli_q(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fli_s<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FliSEmitter<T0, T1>,

RISC-V fli.s instruction.

§Forms

Assembly: fli.s fd, fs1 Rust: fli_s(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn flq<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: FlqEmitter<T0, T1, T2>,

RISC-V flq instruction.

§Forms

Assembly: flq qd, xs1, imm Rust: flq(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Memory base register.
imm — Immediate encoding value.

Source

pub fn flt_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FltDEmitter<T0, T1, T2>,

RISC-V flt.d instruction.

§Forms

Assembly: flt.d xd, xs1, xs2 Rust: flt_d(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn flt_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FltHEmitter<T0, T1, T2>,

RISC-V flt.h instruction.

§Forms

Assembly: flt.h xd, xs1, xs2 Rust: flt_h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn flt_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FltQEmitter<T0, T1, T2>,

RISC-V flt.q instruction.

§Forms

Assembly: flt.q xd, qs1, qs2 Rust: flt_q(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn flt_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FltSEmitter<T0, T1, T2>,

Single-precision floating-point less than

Writes 1 to rd if fs1 is less than fs2, and 0 otherwise.

If either operand is NaN, the result is 0 (not equal). If either operand is a NaN (signaling or quiet), the invalid flag is set.

§Forms

Assembly: flt.s xd, fs1, fs2 Rust: flt_s(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fltq_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FltqDEmitter<T0, T1, T2>,

RISC-V fltq.d instruction.

§Forms

Assembly: fltq.d xd, xs1, xs2 Rust: fltq_d(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fltq_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FltqHEmitter<T0, T1, T2>,

RISC-V fltq.h instruction.

§Forms

Assembly: fltq.h xd, xs1, xs2 Rust: fltq_h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fltq_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FltqQEmitter<T0, T1, T2>,

RISC-V fltq.q instruction.

§Forms

Assembly: fltq.q qd, qs1, qs2 Rust: fltq_q(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fltq_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FltqSEmitter<T0, T1, T2>,

RISC-V fltq.s instruction.

§Forms

Assembly: fltq.s xd, fs1, fs2 Rust: fltq_s(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn flw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: FlwEmitter<T0, T1, T2>,

Single-precision floating-point load

The flw instruction loads a single-precision floating-point value from memory at address rs1 + imm into floating-point register fd.

flw does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

§Forms

Assembly: flw fd, xs1, imm Rust: flw(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Memory base register.
imm — Immediate encoding value.

Source

pub fn fmadd_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FmaddDEmitter<T0, T1, T2, T3, T4>,

RISC-V fmadd.d instruction.

§Forms

Assembly: fmadd.d xd, xs1, xs2, xs3, rm Rust: fmadd_d(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn fmadd_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FmaddHEmitter<T0, T1, T2, T3, T4>,

RISC-V fmadd.h instruction.

§Forms

Assembly: fmadd.h xd, xs1, xs2, xs3, rm Rust: fmadd_h(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn fmadd_q<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FmaddQEmitter<T0, T1, T2, T3, T4>,

RISC-V fmadd.q instruction.

§Forms

Assembly: fmadd.q qd, qs1, qs2, qs3, rm Rust: fmadd_q(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn fmadd_s<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FmaddSEmitter<T0, T1, T2, T3, T4>,

RISC-V fmadd.s instruction.

§Forms

Assembly: fmadd.s fd, fs1, fs2, fs3, rm Rust: fmadd_s(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn fmax_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FmaxDEmitter<T0, T1, T2>,

RISC-V fmax.d instruction.

§Forms

Assembly: fmax.d xd, xs1, xs2 Rust: fmax_d(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmax_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FmaxHEmitter<T0, T1, T2>,

RISC-V fmax.h instruction.

§Forms

Assembly: fmax.h xd, xs1, xs2 Rust: fmax_h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmax_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FmaxQEmitter<T0, T1, T2>,

RISC-V fmax.q instruction.

§Forms

Assembly: fmax.q qd, qs1, qs2 Rust: fmax_q(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmax_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FmaxSEmitter<T0, T1, T2>,

RISC-V fmax.s instruction.

§Forms

Assembly: fmax.s fd, fs1, fs2 Rust: fmax_s(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmaxm_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FmaxmDEmitter<T0, T1, T2>,

RISC-V fmaxm.d instruction.

§Forms

Assembly: fmaxm.d xd, xs1, xs2 Rust: fmaxm_d(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmaxm_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FmaxmHEmitter<T0, T1, T2>,

RISC-V fmaxm.h instruction.

§Forms

Assembly: fmaxm.h xd, xs1, xs2 Rust: fmaxm_h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmaxm_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FmaxmQEmitter<T0, T1, T2>,

RISC-V fmaxm.q instruction.

§Forms

Assembly: fmaxm.q qd, qs1, qs2 Rust: fmaxm_q(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmaxm_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FmaxmSEmitter<T0, T1, T2>,

RISC-V fmaxm.s instruction.

§Forms

Assembly: fmaxm.s xd, xs1, xs2 Rust: fmaxm_s(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmin_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FminDEmitter<T0, T1, T2>,

RISC-V fmin.d instruction.

§Forms

Assembly: fmin.d xd, xs1, xs2 Rust: fmin_d(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmin_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FminHEmitter<T0, T1, T2>,

RISC-V fmin.h instruction.

§Forms

Assembly: fmin.h xd, xs1, xs2 Rust: fmin_h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmin_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FminQEmitter<T0, T1, T2>,

RISC-V fmin.q instruction.

§Forms

Assembly: fmin.q xd, xs1, xs2 Rust: fmin_q(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmin_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FminSEmitter<T0, T1, T2>,

RISC-V fmin.s instruction.

§Forms

Assembly: fmin.s xd, xs1, xs2 Rust: fmin_s(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fminm_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FminmDEmitter<T0, T1, T2>,

RISC-V fminm.d instruction.

§Forms

Assembly: fminm.d xd, xs1, xs2 Rust: fminm_d(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fminm_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FminmHEmitter<T0, T1, T2>,

RISC-V fminm.h instruction.

§Forms

Assembly: fminm.h xd, xs1, xs2 Rust: fminm_h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fminm_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FminmQEmitter<T0, T1, T2>,

RISC-V fminm.q instruction.

§Forms

Assembly: fminm.q qd, qs1, qs2 Rust: fminm_q(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fminm_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FminmSEmitter<T0, T1, T2>,

RISC-V fminm.s instruction.

§Forms

Assembly: fminm.s fd, fs1, fs2 Rust: fminm_s(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmsub_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FmsubDEmitter<T0, T1, T2, T3, T4>,

RISC-V fmsub.d instruction.

§Forms

Assembly: fmsub.d xd, xs1, xs2, xs3, rm Rust: fmsub_d(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn fmsub_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FmsubHEmitter<T0, T1, T2, T3, T4>,

RISC-V fmsub.h instruction.

§Forms

Assembly: fmsub.h xd, xs1, xs2, xs3, rm Rust: fmsub_h(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn fmsub_q<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FmsubQEmitter<T0, T1, T2, T3, T4>,

RISC-V fmsub.q instruction.

§Forms

Assembly: fmsub.q qd, qs1, qs2, qs3, rm Rust: fmsub_q(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn fmsub_s<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FmsubSEmitter<T0, T1, T2, T3, T4>,

RISC-V fmsub.s instruction.

§Forms

Assembly: fmsub.s fd, fs1, fs2, fs3, rm Rust: fmsub_s(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn fmul_d<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
where Self: FmulDEmitter<T0, T1, T2, T3>,

RISC-V fmul.d instruction.

§Forms

Assembly: fmul.d xd, xs1, xs2, rm Rust: fmul_d(rd, rs1, rs2, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rm — Rounding mode.

Source

pub fn fmul_h<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
where Self: FmulHEmitter<T0, T1, T2, T3>,

RISC-V fmul.h instruction.

§Forms

Assembly: fmul.h xd, xs1, xs2, rm Rust: fmul_h(rd, rs1, rs2, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rm — Rounding mode.

Source

pub fn fmul_q<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
where Self: FmulQEmitter<T0, T1, T2, T3>,

RISC-V fmul.q instruction.

§Forms

Assembly: fmul.q qd, qs1, qs2, rm Rust: fmul_q(rd, rs1, rs2, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rm — Rounding mode.

Source

pub fn fmul_s<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
where Self: FmulSEmitter<T0, T1, T2, T3>,

RISC-V fmul.s instruction.

§Forms

Assembly: fmul.s fd, fs1, fs2, rm Rust: fmul_s(rd, rs1, rs2, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rm — Rounding mode.

Source

pub fn fmv_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FmvDEmitter<T0, T1, T2>,

RISC-V fmv.d instruction.

§Forms

Assembly: fmv.d rd rs1 rs2_eq_rs1 Rust: fmv_d(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmv_d_x<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FmvDXEmitter<T0, T1>,

RISC-V fmv.d.x instruction.

§Forms

Assembly: fmv.d.x xd, xs1 Rust: fmv_d_x(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fmv_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FmvHEmitter<T0, T1, T2>,

RISC-V fmv.h instruction.

§Forms

Assembly: fmv.h rd rs1 rs2_eq_rs1 Rust: fmv_h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmv_h_x<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FmvHXEmitter<T0, T1>,

Half-precision floating-point move from integer

Moves the half-precision value encoded in IEEE 754-2008 standard encoding from the lower 16 bits of integer register rs1 to the floating-point register fd. The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved.

§Forms

Assembly: fmv.h.x fd, xs1 Rust: fmv_h_x(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fmv_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FmvQEmitter<T0, T1, T2>,

RISC-V fmv.q instruction.

§Forms

Assembly: fmv.q rd rs1 rs2_eq_rs1 Rust: fmv_q(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmv_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FmvSEmitter<T0, T1, T2>,

RISC-V fmv.s instruction.

§Forms

Assembly: fmv.s rd rs1 rs2_eq_rs1 Rust: fmv_s(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmv_s_x<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FmvSXEmitter<T0, T1>,

RISC-V fmv.s.x instruction.

§Forms

Assembly: fmv.s.x rd rs1 Rust: fmv_s_x(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fmv_w_x<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FmvWXEmitter<T0, T1>,

Single-precision floating-point move from integer

Moves the single-precision value encoded in IEEE 754-2008 standard encoding from the lower 32 bits of integer register rs1 to the floating-point register fd. The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved.

§Forms

Assembly: fmv.w.x fd, xs1 Rust: fmv_w_x(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fmv_x_d<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FmvXDEmitter<T0, T1>,

RISC-V fmv.x.d instruction.

§Forms

Assembly: fmv.x.d xd, xs1 Rust: fmv_x_d(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fmv_x_h<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FmvXHEmitter<T0, T1>,

Move half-precision value from floating-point to integer register

Moves the half-precision value in floating-point register rs1 represented in IEEE 754-2008 encoding to the lower 16 bits of integer register rd.

The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved.

The highest XLEN-16 bits of the destination register are filled with copies of the floating-point number’s sign bit.

§Forms

Assembly: fmv.x.h rd, fs1 Rust: fmv_x_h(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fmv_x_s<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FmvXSEmitter<T0, T1>,

RISC-V fmv.x.s instruction.

§Forms

Assembly: fmv.x.s rd rs1 Rust: fmv_x_s(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fmv_x_w<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FmvXWEmitter<T0, T1>,

Move single-precision value from floating-point to integer register

Moves the single-precision value in floating-point register rs1 represented in IEEE 754-2008 encoding to the lower 32 bits of integer register rd. The bits are not modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved. For RV64, the higher 32 bits of the destination register are filled with copies of the floating-point number’s sign bit.

§Forms

Assembly: fmv.x.w xd, fs1 Rust: fmv_x_w(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fmvh_x_d<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FmvhXDEmitter<T0, T1>,

RISC-V fmvh.x.d instruction.

§Forms

Assembly: fmvh.x.d xd, xs1 Rust: fmvh_x_d(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fmvh_x_q<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FmvhXQEmitter<T0, T1>,

RISC-V fmvh.x.q instruction.

§Forms

Assembly: fmvh.x.q xd, qs1 Rust: fmvh_x_q(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fmvp_d_x<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FmvpDXEmitter<T0, T1, T2>,

RISC-V fmvp.d.x instruction.

§Forms

Assembly: fmvp.d.x xd, xs1, xs2 Rust: fmvp_d_x(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fmvp_q_x<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FmvpQXEmitter<T0, T1, T2>,

RISC-V fmvp.q.x instruction.

§Forms

Assembly: fmvp.q.x qd, xs1, xs2 Rust: fmvp_q_x(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fneg_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FnegDEmitter<T0, T1, T2>,

RISC-V fneg.d instruction.

§Forms

Assembly: fneg.d rd rs1 rs2_eq_rs1 Rust: fneg_d(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fneg_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FnegHEmitter<T0, T1, T2>,

RISC-V fneg.h instruction.

§Forms

Assembly: fneg.h rd rs1 rs2_eq_rs1 Rust: fneg_h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fneg_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FnegQEmitter<T0, T1, T2>,

RISC-V fneg.q instruction.

§Forms

Assembly: fneg.q rd rs1 rs2_eq_rs1 Rust: fneg_q(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fneg_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FnegSEmitter<T0, T1, T2>,

RISC-V fneg.s instruction.

§Forms

Assembly: fneg.s rd rs1 rs2_eq_rs1 Rust: fneg_s(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fnmadd_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FnmaddDEmitter<T0, T1, T2, T3, T4>,

RISC-V fnmadd.d instruction.

§Forms

Assembly: fnmadd.d xd, xs1, xs2, xs3, rm Rust: fnmadd_d(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn fnmadd_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FnmaddHEmitter<T0, T1, T2, T3, T4>,

RISC-V fnmadd.h instruction.

§Forms

Assembly: fnmadd.h xd, xs1, xs2, xs3, rm Rust: fnmadd_h(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn fnmadd_q<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FnmaddQEmitter<T0, T1, T2, T3, T4>,

RISC-V fnmadd.q instruction.

§Forms

Assembly: fnmadd.q qd, qs1, qs2, qs3, rm Rust: fnmadd_q(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn fnmadd_s<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FnmaddSEmitter<T0, T1, T2, T3, T4>,

RISC-V fnmadd.s instruction.

§Forms

Assembly: fnmadd.s fd, fs1, fs2, fs3, rm Rust: fnmadd_s(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn fnmsub_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FnmsubDEmitter<T0, T1, T2, T3, T4>,

RISC-V fnmsub.d instruction.

§Forms

Assembly: fnmsub.d xd, xs1, xs2, xs3, rm Rust: fnmsub_d(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn fnmsub_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FnmsubHEmitter<T0, T1, T2, T3, T4>,

RISC-V fnmsub.h instruction.

§Forms

Assembly: fnmsub.h xd, xs1, xs2, xs3, rm Rust: fnmsub_h(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn fnmsub_q<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FnmsubQEmitter<T0, T1, T2, T3, T4>,

RISC-V fnmsub.q instruction.

§Forms

Assembly: fnmsub.q qd, qs1, qs2, qs3, rm Rust: fnmsub_q(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn fnmsub_s<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, rs3: T3, rm: T4, )
where Self: FnmsubSEmitter<T0, T1, T2, T3, T4>,

RISC-V fnmsub.s instruction.

§Forms

Assembly: fnmsub.s xd, xs1, xs2, xs3, rm Rust: fnmsub_s(rd, rs1, rs2, rs3, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rs3 — Source register.
rm — Rounding mode.

Source

pub fn frcsr<T0>(&mut self, rd: T0)
where Self: FrcsrEmitter<T0>,

RISC-V frcsr instruction.

§Forms

Assembly: frcsr rd Rust: frcsr(rd)

§Arguments

rd — Destination register.

Source

pub fn frflags<T0>(&mut self, rd: T0)
where Self: FrflagsEmitter<T0>,

RISC-V frflags instruction.

§Forms

Assembly: frflags rd Rust: frflags(rd)

§Arguments

rd — Destination register.

Source

pub fn fround_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FroundDEmitter<T0, T1, T2>,

RISC-V fround.d instruction.

§Forms

Assembly: fround.d xd, xs1, rm Rust: fround_d(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fround_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FroundHEmitter<T0, T1, T2>,

RISC-V fround.h instruction.

§Forms

Assembly: fround.h xd, xs1, rm Rust: fround_h(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fround_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FroundQEmitter<T0, T1, T2>,

RISC-V fround.q instruction.

§Forms

Assembly: fround.q qd, qs1, rm Rust: fround_q(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fround_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FroundSEmitter<T0, T1, T2>,

RISC-V fround.s instruction.

§Forms

Assembly: fround.s fd, xs1, rm Rust: fround_s(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn froundnx_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FroundnxDEmitter<T0, T1, T2>,

RISC-V froundnx.d instruction.

§Forms

Assembly: froundnx.d xd, xs1, rm Rust: froundnx_d(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn froundnx_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FroundnxHEmitter<T0, T1, T2>,

RISC-V froundnx.h instruction.

§Forms

Assembly: froundnx.h xd, xs1, rm Rust: froundnx_h(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn froundnx_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FroundnxQEmitter<T0, T1, T2>,

RISC-V froundnx.q instruction.

§Forms

Assembly: froundnx.q qd, qs1, rm Rust: froundnx_q(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn froundnx_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FroundnxSEmitter<T0, T1, T2>,

RISC-V froundnx.s instruction.

§Forms

Assembly: froundnx.s fd, rs1, rm Rust: froundnx_s(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn frrm<T0>(&mut self, rd: T0)
where Self: FrrmEmitter<T0>,

RISC-V frrm instruction.

§Forms

Assembly: frrm rd Rust: frrm(rd)

§Arguments

rd — Destination register.

Source

pub fn fscsr<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FscsrEmitter<T0, T1>,

RISC-V fscsr instruction.

§Forms

Assembly: fscsr rd rs1 Rust: fscsr(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fsd<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: FsdEmitter<T0, T1, T2>,

RISC-V fsd instruction.

§Forms

Assembly: fsd xs1, xs2, imm Rust: fsd(rs1, rs2, imm)

§Arguments

rs1 — Memory base register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn fsflags<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FsflagsEmitter<T0, T1>,

RISC-V fsflags instruction.

§Forms

Assembly: fsflags rd rs1 Rust: fsflags(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fsflagsi<T0, T1>(&mut self, rd: T0, zimm5: T1)
where Self: FsflagsiEmitter<T0, T1>,

RISC-V fsflagsi instruction.

§Forms

Assembly: fsflagsi rd zimm5 Rust: fsflagsi(rd, zimm5)

§Arguments

rd — Destination register.
zimm5 — Immediate encoding value.

Source

pub fn fsgnj_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FsgnjDEmitter<T0, T1, T2>,

RISC-V fsgnj.d instruction.

§Forms

Assembly: fsgnj.d xd, xs1, xs2 Rust: fsgnj_d(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fsgnj_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FsgnjHEmitter<T0, T1, T2>,

RISC-V fsgnj.h instruction.

§Forms

Assembly: fsgnj.h xd, xs1, xs2 Rust: fsgnj_h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fsgnj_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FsgnjQEmitter<T0, T1, T2>,

RISC-V fsgnj.q instruction.

§Forms

Assembly: fsgnj.q qd, qs1, qs2 Rust: fsgnj_q(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fsgnj_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FsgnjSEmitter<T0, T1, T2>,

Single-precision sign inject

Writes fd with sign bit of fs2 and the exponent and mantissa of fs1.

Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs.

§Forms

Assembly: fsgnj.s fd, fs1, fs2 Rust: fsgnj_s(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fsgnjn_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FsgnjnDEmitter<T0, T1, T2>,

RISC-V fsgnjn.d instruction.

§Forms

Assembly: fsgnjn.d xd, xs1, xs2 Rust: fsgnjn_d(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fsgnjn_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FsgnjnHEmitter<T0, T1, T2>,

RISC-V fsgnjn.h instruction.

§Forms

Assembly: fsgnjn.h xd, xs1, xs2 Rust: fsgnjn_h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fsgnjn_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FsgnjnQEmitter<T0, T1, T2>,

RISC-V fsgnjn.q instruction.

§Forms

Assembly: fsgnjn.q qd, qs1, qs2 Rust: fsgnjn_q(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fsgnjn_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FsgnjnSEmitter<T0, T1, T2>,

Single-precision sign inject negate

Writes fd with the opposite of the sign bit of fs2 and the exponent and mantissa of fs1.

Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs.

§Forms

Assembly: fsgnjn.s fd, fs1, fs2 Rust: fsgnjn_s(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fsgnjx_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FsgnjxDEmitter<T0, T1, T2>,

RISC-V fsgnjx.d instruction.

§Forms

Assembly: fsgnjx.d xd, xs1, xs2 Rust: fsgnjx_d(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fsgnjx_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FsgnjxHEmitter<T0, T1, T2>,

RISC-V fsgnjx.h instruction.

§Forms

Assembly: fsgnjx.h xd, xs1, xs2 Rust: fsgnjx_h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fsgnjx_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FsgnjxQEmitter<T0, T1, T2>,

RISC-V fsgnjx.q instruction.

§Forms

Assembly: fsgnjx.q qd, qs1, qs2 Rust: fsgnjx_q(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fsgnjx_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: FsgnjxSEmitter<T0, T1, T2>,

Single-precision sign inject exclusive or

Writes fd with the xor of the sign bits of fs2 and fs1 and the exponent and mantissa of fs1.

Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs.

§Forms

Assembly: fsgnjx.s fd, fs1, fs2 Rust: fsgnjx_s(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn fsh<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: FshEmitter<T0, T1, T2>,

Half-precision floating-point store

The fsh instruction stores a half-precision floating-point value from register rd to memory at address rs1 + imm.

fsh does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

fsh ignores all but the lower 16 bits in rs2.

fsh is only guaranteed to execute atomically if the effective address is naturally aligned.

§Forms

Assembly: fsh fs2, imm(xs1) Rust: fsh(rs1, rs2, imm)

§Arguments

rs1 — Memory base register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn fsq<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: FsqEmitter<T0, T1, T2>,

RISC-V fsq instruction.

§Forms

Assembly: fsq xs1, qs2, imm Rust: fsq(rs1, rs2, imm)

§Arguments

rs1 — Memory base register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn fsqrt_d<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FsqrtDEmitter<T0, T1, T2>,

RISC-V fsqrt.d instruction.

§Forms

Assembly: fsqrt.d xd, xs1, rm Rust: fsqrt_d(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fsqrt_h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FsqrtHEmitter<T0, T1, T2>,

RISC-V fsqrt.h instruction.

§Forms

Assembly: fsqrt.h xd, xs1, rm Rust: fsqrt_h(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fsqrt_q<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FsqrtQEmitter<T0, T1, T2>,

RISC-V fsqrt.q instruction.

§Forms

Assembly: fsqrt.q qd, qs1, rm Rust: fsqrt_q(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fsqrt_s<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rm: T2)
where Self: FsqrtSEmitter<T0, T1, T2>,

RISC-V fsqrt.s instruction.

§Forms

Assembly: fsqrt.s fd, fs1, rm Rust: fsqrt_s(rd, rs1, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rm — Rounding mode.

Source

pub fn fsrm<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: FsrmEmitter<T0, T1>,

RISC-V fsrm instruction.

§Forms

Assembly: fsrm rd rs1 Rust: fsrm(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn fsrmi<T0, T1>(&mut self, rd: T0, zimm5: T1)
where Self: FsrmiEmitter<T0, T1>,

RISC-V fsrmi instruction.

§Forms

Assembly: fsrmi rd zimm5 Rust: fsrmi(rd, zimm5)

§Arguments

rd — Destination register.
zimm5 — Immediate encoding value.

Source

pub fn fsub_d<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
where Self: FsubDEmitter<T0, T1, T2, T3>,

RISC-V fsub.d instruction.

§Forms

Assembly: fsub.d xd, xs1, xs2, rm Rust: fsub_d(rd, rs1, rs2, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rm — Rounding mode.

Source

pub fn fsub_h<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
where Self: FsubHEmitter<T0, T1, T2, T3>,

RISC-V fsub.h instruction.

§Forms

Assembly: fsub.h xd, xs1, xs2, rm Rust: fsub_h(rd, rs1, rs2, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rm — Rounding mode.

Source

pub fn fsub_q<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
where Self: FsubQEmitter<T0, T1, T2, T3>,

RISC-V fsub.q instruction.

§Forms

Assembly: fsub.q qd, qs1, qs2, rm Rust: fsub_q(rd, rs1, rs2, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rm — Rounding mode.

Source

pub fn fsub_s<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, rm: T3)
where Self: FsubSEmitter<T0, T1, T2, T3>,

Single-precision floating-point subtraction

Do the single-precision floating-point subtraction of fs2 from fs1 and store the result in fd. rm is the dynamic Rounding Mode.

§Forms

Assembly: fsub.s fd, fs1, fs2, rm Rust: fsub_s(rd, rs1, rs2, rm)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
rm — Rounding mode.

Source

pub fn fsw<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: FswEmitter<T0, T1, T2>,

Single-precision floating-point store

The fsw instruction stores a single-precision floating-point value in fs2 to memory at address rs1 + imm.

fsw does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

§Forms

Assembly: fsw fs2, xs1, imm Rust: fsw(rs1, rs2, imm)

§Arguments

rs1 — Memory base register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn hfence_gvma<T0, T1>(&mut self, rs1: T0, rs2: T1)
where Self: HfenceGvmaEmitter<T0, T1>,

RISC-V hfence.gvma instruction.

§Forms

Assembly: hfence.gvma xs1, xs2 Rust: hfence_gvma(rs1, rs2)

§Arguments

rs1 — Source register.
rs2 — Source register.

Source

pub fn hfence_vvma<T0, T1>(&mut self, rs1: T0, rs2: T1)
where Self: HfenceVvmaEmitter<T0, T1>,

RISC-V hfence.vvma instruction.

§Forms

Assembly: hfence.vvma xs1, xs2 Rust: hfence_vvma(rs1, rs2)

§Arguments

rs1 — Source register.
rs2 — Source register.

Source

pub fn hinval_gvma<T0, T1>(&mut self, rs1: T0, rs2: T1)
where Self: HinvalGvmaEmitter<T0, T1>,

Invalidate cached address translations

hinval.gvma has the same semantics as sinval.vma except that it combines with sfence.w.inval and sfence.inval.ir to replace hfence.gvma and uses VMID instead of ASID.

§Forms

Assembly: hinval.gvma xs1, xs2 Rust: hinval_gvma(rs1, rs2)

§Arguments

rs1 — Source register.
rs2 — Source register.

Source

pub fn hinval_vvma<T0, T1>(&mut self, rs1: T0, rs2: T1)
where Self: HinvalVvmaEmitter<T0, T1>,

Invalidate cached address translations

hinval.vvma has the same semantics as sinval.vma except that it combines with sfence.w.inval and sfence.inval.ir to replace hfence.vvma.

§Forms

Assembly: hinval.vvma xs1, xs2 Rust: hinval_vvma(rs1, rs2)

§Arguments

rs1 — Source register.
rs2 — Source register.

Source

pub fn hlv_b<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: HlvBEmitter<T0, T1>,

RISC-V hlv.b instruction.

§Forms

Assembly: hlv.b xd, xs1 Rust: hlv_b(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn hlv_bu<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: HlvBuEmitter<T0, T1>,

RISC-V hlv.bu instruction.

§Forms

Assembly: hlv.bu xd, xs1 Rust: hlv_bu(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn hlv_d<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: HlvDEmitter<T0, T1>,

RISC-V hlv.d instruction.

§Forms

Assembly: hlv.d xd, xs1 Rust: hlv_d(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn hlv_h<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: HlvHEmitter<T0, T1>,

RISC-V hlv.h instruction.

§Forms

Assembly: hlv.h xd, xs1 Rust: hlv_h(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn hlv_hu<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: HlvHuEmitter<T0, T1>,

RISC-V hlv.hu instruction.

§Forms

Assembly: hlv.hu xd, xs1 Rust: hlv_hu(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn hlv_w<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: HlvWEmitter<T0, T1>,

RISC-V hlv.w instruction.

§Forms

Assembly: hlv.w xd, xs1 Rust: hlv_w(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn hlv_wu<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: HlvWuEmitter<T0, T1>,

RISC-V hlv.wu instruction.

§Forms

Assembly: hlv.wu xd, xs1 Rust: hlv_wu(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn hlvx_hu<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: HlvxHuEmitter<T0, T1>,

RISC-V hlvx.hu instruction.

§Forms

Assembly: hlvx.hu xd, xs1 Rust: hlvx_hu(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn hlvx_wu<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: HlvxWuEmitter<T0, T1>,

RISC-V hlvx.wu instruction.

§Forms

Assembly: hlvx.wu xd, xs1 Rust: hlvx_wu(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn hsv_b<T0, T1>(&mut self, rs1: T0, rs2: T1)
where Self: HsvBEmitter<T0, T1>,

RISC-V hsv.b instruction.

§Forms

Assembly: hsv.b xs1, xs2 Rust: hsv_b(rs1, rs2)

§Arguments

rs1 — Source register.
rs2 — Source register.

Source

pub fn hsv_d<T0, T1>(&mut self, rs1: T0, rs2: T1)
where Self: HsvDEmitter<T0, T1>,

RISC-V hsv.d instruction.

§Forms

Assembly: hsv.d xs1, xs2 Rust: hsv_d(rs1, rs2)

§Arguments

rs1 — Source register.
rs2 — Source register.

Source

pub fn hsv_h<T0, T1>(&mut self, rs1: T0, rs2: T1)
where Self: HsvHEmitter<T0, T1>,

RISC-V hsv.h instruction.

§Forms

Assembly: hsv.h xs1, xs2 Rust: hsv_h(rs1, rs2)

§Arguments

rs1 — Source register.
rs2 — Source register.

Source

pub fn hsv_w<T0, T1>(&mut self, rs1: T0, rs2: T1)
where Self: HsvWEmitter<T0, T1>,

RISC-V hsv.w instruction.

§Forms

Assembly: hsv.w xs1, xs2 Rust: hsv_w(rs1, rs2)

§Arguments

rs1 — Source register.
rs2 — Source register.

Source

pub fn j<T0>(&mut self, imm: T0)
where Self: JEmitter<T0>,

RISC-V j instruction.

§Forms

Assembly: j jimm20 Rust: j(imm)

§Arguments

imm — Immediate encoding value.

Source

pub fn jal<T0, T1>(&mut self, rd: T0, imm: T1)
where Self: JalEmitter<T0, T1>,

Jump and link

Jump to a PC-relative offset and store the return address in rd.

§Forms

Assembly: jal xd, imm Rust: jal(rd, imm)

§Arguments

rd — Destination register.
imm — Immediate encoding value.

Source

pub fn jal_pseudo<T0>(&mut self, imm: T0)
where Self: JalPseudoEmitter<T0>,

RISC-V jal.pseudo instruction.

§Forms

Assembly: jal.pseudo jimm20 Rust: jal_pseudo(imm)

§Arguments

imm — Immediate encoding value.

Source

pub fn jalr<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: JalrEmitter<T0, T1, T2>,

Jump and link register

Jump to an address formed by adding rs1 to a signed offset then clearing the least significant bit, and store the return address in rd.

§Forms

Assembly: jalr xd, imm(rs1) Rust: jalr(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Source register.
imm — Immediate encoding value.

Source

pub fn jalr_pseudo<T0>(&mut self, rs1: T0)
where Self: JalrPseudoEmitter<T0>,

RISC-V jalr.pseudo instruction.

§Forms

Assembly: jalr.pseudo rs1 Rust: jalr_pseudo(rs1)

§Arguments

rs1 — Source register.

Source

pub fn jr<T0>(&mut self, rs1: T0)
where Self: JrEmitter<T0>,

RISC-V jr instruction.

§Forms

Assembly: jr rs1 Rust: jr(rs1)

§Arguments

rs1 — Source register.

Source

pub fn lb<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: LbEmitter<T0, T1, T2>,

Load byte

Load 8 bits of data into register rd from an address formed by adding rs1 to a signed offset. Sign extend the result.

§Forms

Assembly: lb xd, imm(rs1) Rust: lb(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Memory base register.
imm — Immediate encoding value.

Source

pub fn lbu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: LbuEmitter<T0, T1, T2>,

Load byte unsigned

Load 8 bits of data into register rd from an address formed by adding rs1 to a signed offset. Zero extend the result.

§Forms

Assembly: lbu xd, imm(rs1) Rust: lbu(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Memory base register.
imm — Immediate encoding value.

Source

pub fn ld<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: LdEmitter<T0, T1, T2>,

Load doubleword

Load 64 bits of data into register rd from an address formed by adding rs1 to a signed offset.

§Forms

Assembly: ld xd, imm(rs1) Rust: ld(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Memory base register.
imm — Immediate encoding value.

Source

pub fn lh<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: LhEmitter<T0, T1, T2>,

Load halfword

Load 16 bits of data into register rd from an address formed by adding rs1 to a signed offset. Sign extend the result.

§Forms

Assembly: lh xd, imm(rs1) Rust: lh(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Memory base register.
imm — Immediate encoding value.

Source

pub fn lhu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: LhuEmitter<T0, T1, T2>,

Load halfword unsigned

Load 16 bits of data into register rd from an address formed by adding rs1 to a signed offset. Zero extend the result.

§Forms

Assembly: lhu xd, imm(rs1) Rust: lhu(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Memory base register.
imm — Immediate encoding value.

Source

pub fn lpad<T0>(&mut self, imm: T0)
where Self: LpadEmitter<T0>,

RISC-V lpad instruction.

§Forms

Assembly: lpad imm Rust: lpad(imm)

§Arguments

imm — Immediate encoding value.

Source

pub fn lr_d<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, aq: T2, rl: T3)
where Self: LrDEmitter<T0, T1, T2, T3>,

Load reserved doubleword

Loads a word from the address in rs1, places the value in rd, and registers a reservation set – a set of bytes that subsumes the bytes in the addressed word.

The address in rs1 must be 8-byte aligned.

If the address is not naturally aligned, a LoadAddressMisaligned exception or an LoadAccessFault exception will be generated. The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.

An implementation can register an arbitrarily large reservation set on each LR, provided the reservation set includes all bytes of the addressed data word or doubleword. An SC can only pair with the most recent LR in program order. An SC may succeed only if no store from another hart to the reservation set can be observed to have occurred between the LR and the SC, and if there is no other SC between the LR and itself in program order. An SC may succeed only if no write from a device other than a hart to the bytes accessed by the LR instruction can be observed to have occurred between the LR and SC. Note this LR might have had a different effective address and data size, but reserved the SC’s address as part of the reservation set.

§[NOTE]

Following this model, in systems with memory translation, an SC is allowed to succeed if the earlier LR reserved the same location using an alias with a different virtual address, but is also allowed to fail if the virtual address is different.

§To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only required to invalidate reservations when they overlap the bytes accessed by the LR. These writes are not required to invalidate the reservation when they access other bytes in the reservation set.

Software should not set the rl bit on an LR instruction unless the aq bit is also set. LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those with both bits clear, but may result in lower performance.

§Forms

Assembly: lr.d xd, xs1 Rust: lr_d(rd, rs1, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn lr_w<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, aq: T2, rl: T3)
where Self: LrWEmitter<T0, T1, T2, T3>,

Load reserved word

Loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set – a set of bytes that subsumes the bytes in the addressed word.

<%- if XLEN == 64 -%> The 32-bit load result is sign-extended to 64-bits. <%- end -%>

The address in rs1 must be naturally aligned to the size of the operand (i.e., eight-byte aligned for doublewords and four-byte aligned for words).

If the address is not naturally aligned, a LoadAddressMisaligned exception or an LoadAccessFault exception will be generated. The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.

An implementation can register an arbitrarily large reservation set on each LR, provided the reservation set includes all bytes of the addressed data word or doubleword. An SC can only pair with the most recent LR in program order. An SC may succeed only if no store from another hart to the reservation set can be observed to have occurred between the LR and the SC, and if there is no other SC between the LR and itself in program order. An SC may succeed only if no write from a device other than a hart to the bytes accessed by the LR instruction can be observed to have occurred between the LR and SC. Note this LR might have had a different effective address and data size, but reserved the SC’s address as part of the reservation set.

§[NOTE]

Following this model, in systems with memory translation, an SC is allowed to succeed if the earlier LR reserved the same location using an alias with a different virtual address, but is also allowed to fail if the virtual address is different.

§To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only required to invalidate reservations when they overlap the bytes accessed by the LR. These writes are not required to invalidate the reservation when they access other bytes in the reservation set.

Software should not set the rl bit on an LR instruction unless the aq bit is also set. LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those with both bits clear, but may result in lower performance.

§Forms

Assembly: lr.w xd, xs1 Rust: lr_w(rd, rs1, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn lui<T0, T1>(&mut self, rd: T0, imm: T1)
where Self: LuiEmitter<T0, T1>,

Load upper immediate

Load the zero-extended imm into rd.

§Forms

Assembly: lui xd, imm Rust: lui(rd, imm)

§Arguments

rd — Destination register.
imm — Immediate encoding value.

Source

pub fn lw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: LwEmitter<T0, T1, T2>,

Load word

Load 32 bits of data into register rd from an address formed by adding rs1 to a signed offset. Sign extend the result.

§Forms

Assembly: lw xd, imm(rs1) Rust: lw(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Memory base register.
imm — Immediate encoding value.

Source

pub fn lwu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: LwuEmitter<T0, T1, T2>,

Load word unsigned

Load 64 bits of data into register rd from an address formed by adding rs1 to a signed offset. Zero extend the result.

§Forms

Assembly: lwu xd, imm(rs1) Rust: lwu(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Memory base register.
imm — Immediate encoding value.

Source

pub fn max<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: MaxEmitter<T0, T1, T2>,

Maximum

This instruction returns the larger of two signed integers.

.Software Hint [NOTE] Calculating the absolute value of a signed integer can be performed using the following sequence: neg rD,rS followed by `max rD,rS,rD. When using this common sequence, it is suggested that they are scheduled with no intervening instructions so that implementations that are so optimized can fuse them together.

§Forms

Assembly: max xd, xs1, xs2 Rust: max(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn maxu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: MaxuEmitter<T0, T1, T2>,

Unsigned maximum

This instruction returns the larger of two unsigned integers.

§Forms

Assembly: maxu xd, xs1, xs2 Rust: maxu(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn min<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: MinEmitter<T0, T1, T2>,

Minimum

This instruction returns the smaller of two signed integers.

§Forms

Assembly: min xd, xs1, xs2 Rust: min(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn minu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: MinuEmitter<T0, T1, T2>,

Unsigned minimum

This instruction returns the smaller of two unsigned integers.

§Forms

Assembly: minu xd, xs1, xs2 Rust: minu(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn mnret(&mut self)
where Self: MnretEmitter,

RISC-V mnret instruction.

§Forms

Assembly: mnret mnret Rust: mnret()

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn mret(&mut self)
where Self: MretEmitter,

Machine Exception Return

Returns from an exception in M-mode.

§Forms

Assembly: mret "" Rust: mret()

§Arguments

Source

pub fn mul<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: MulEmitter<T0, T1, T2>,

Signed multiply

MUL performs an XLEN-bitxXLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits in the destination register. Any overflow is thrown away.

[NOTE] If both the high and low bits of the same product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing two separate multiplies.

§Forms

Assembly: mul xd, xs1, xs2 Rust: mul(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn mulh<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: MulhEmitter<T0, T1, T2>,

Signed multiply high

Multiply the signed values in rs1 to rs2, and store the upper half of the result in rd. The lower half is thrown away.

If both the upper and lower halves are needed, it suggested to use the sequence:

§mulh rdh, rs1, rs2 mul rdl, rs1, rs2

Microarchitectures may look for that sequence and fuse the operations.

§Forms

Assembly: mulh xd, xs1, xs2 Rust: mulh(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn mulhsu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: MulhsuEmitter<T0, T1, T2>,

Signed/unsigned multiply high

Multiply the signed value in rs1 by the unsigned value in rs2, and store the upper half of the result in rd. The lower half is thrown away.

If both the upper and lower halves are needed, it suggested to use the sequence:

§mulhsu rdh, rs1, rs2 mul rdl, rs1, rs2

Microarchitectures may look for that sequence and fuse the operations.

§Forms

Assembly: mulhsu xd, xs1, xs2 Rust: mulhsu(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn mulhu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: MulhuEmitter<T0, T1, T2>,

Unsigned multiply high

Multiply the unsigned values in rs1 to rs2, and store the upper half of the result in rd. The lower half is thrown away.

If both the upper and lower halves are needed, it suggested to use the sequence:

§mulhu rdh, rs1, rs2 mul rdl, rs1, rs2

Microarchitectures may look for that sequence and fuse the operations.

§Forms

Assembly: mulhu xd, xs1, xs2 Rust: mulhu(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn mulw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: MulwEmitter<T0, T1, T2>,

Signed 32-bit multiply

Multiplies the lower 32 bits of the source registers, placing the sign-extension of the lower 32 bits of the result into the destination register.

Any overflow is thrown away.

[NOTE] In RV64, MUL can be used to obtain the upper 32 bits of the 64-bit product, but signed arguments must be proper 32-bit signed values, whereas unsigned arguments must have their upper 32 bits clear. If the arguments are not known to be sign- or zero-extended, an alternative is to shift both arguments left by 32 bits, then use MULH[[S]U].

§Forms

Assembly: mulw xd, xs1, xs2 Rust: mulw(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn mv<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: MvEmitter<T0, T1>,

RISC-V mv instruction.

§Forms

Assembly: mv rd rs1 Rust: mv(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn neg<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: NegEmitter<T0, T1>,

RISC-V neg instruction.

§Forms

Assembly: neg rd rs1 Rust: neg(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn or<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: OrEmitter<T0, T1, T2>,

Or

Or rs1 with rs2, and store the result in rd

§Forms

Assembly: or xd, xs1, xs2 Rust: or(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn orc_b<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: OrcBEmitter<T0, T1>,

Bitware OR-combine, byte granule

Combines the bits within each byte using bitwise logical OR. This sets the bits of each byte in the result rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the respective byte of rs is set.

§Forms

Assembly: orc.b xd, xs1, xs2 Rust: orc_b(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn ori<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: OriEmitter<T0, T1, T2>,

Or immediate

Or an immediate to the value in rs1, and store the result in rd

§Forms

Assembly: ori xd, xs1, imm Rust: ori(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Source register.
imm — Immediate encoding value.

Source

pub fn orn<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: OrnEmitter<T0, T1, T2>,

OR with inverted operand

This instruction performs the bitwise logical OR operation between rs1 and the bitwise inversion of rs2.

§Forms

Assembly: orn xd, xs1, xs2 Rust: orn(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn pack<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: PackEmitter<T0, T1, T2>,

RISC-V pack instruction.

§Forms

Assembly: pack xd, xs1, xs2 Rust: pack(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn packh<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: PackhEmitter<T0, T1, T2>,

RISC-V packh instruction.

§Forms

Assembly: packh xd, xs1, xs2 Rust: packh(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn packw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: PackwEmitter<T0, T1, T2>,

RISC-V packw instruction.

§Forms

Assembly: packw xd, xs1, xs2 Rust: packw(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn pause(&mut self)
where Self: PauseEmitter,

RISC-V pause instruction.

§Forms

Assembly: pause Rust: pause()

rd — Destination register.

Source

pub fn rem<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: RemEmitter<T0, T1, T2>,

Signed remainder

Calculate the remainder of signed division of rs1 by rs2, and store the result in rd.

If the value in register rs2 is zero, write the value in rs1 into rd;

If the result of the division overflows, write zero into rd;

§Forms

Assembly: rem xd, xs1, xs2 Rust: rem(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn remu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: RemuEmitter<T0, T1, T2>,

Unsigned remainder

Calculate the remainder of unsigned division of rs1 by rs2, and store the result in rd.

§Forms

Assembly: remu xd, xs1, xs2 Rust: remu(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn remuw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: RemuwEmitter<T0, T1, T2>,

Unsigned 32-bit remainder

Calculate the remainder of unsigned division of the 32-bit values in rs1 by rs2, and store the sign-extended result in rd.

If the value in rs2 is zero, rd gets the sign-extended value in rs1.

§Forms

Assembly: remuw xd, xs1, xs2 Rust: remuw(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn remw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: RemwEmitter<T0, T1, T2>,

Signed 32-bit remainder

Calculate the remainder of signed division of the 32-bit values rs1 by rs2, and store the sign-extended result in rd.

If the value in register rs2 is zero, write the sign-extended 32-bit value in rs1 into rd;

If the result of the division overflows, write zero into rd;

§Forms

Assembly: remw xd, xs1, xs2 Rust: remw(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn ret(&mut self)
where Self: RetEmitter,

RISC-V ret instruction.

§Forms

Assembly: ret Rust: ret()

§Arguments

Source

pub fn rev8<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: Rev8Emitter<T0, T1>,

Byte-reverse register (RV64 encoding)

This instruction reverses the order of the bytes in rs1.

[NOTE] The rev8 mnemonic corresponds to different instruction encodings in RV32 and RV64.

[NOTE] The byte-reverse operation is only available for the full register width. To emulate word-sized and halfword-sized byte-reversal, perform a rev8 rd,rs followed by a srai rd,rd,K, where K is XLEN-32 and XLEN-16, respectively.

§Forms

Assembly: rev8 xd, xs1 Rust: rev8(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn rev8_rv32<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: Rev8Rv32Emitter<T0, T1>,

Byte-reverse register (RV64 encoding)

This instruction reverses the order of the bytes in rs1.

[NOTE] The rev8 mnemonic corresponds to different instruction encodings in RV32 and RV64.

[NOTE] The byte-reverse operation is only available for the full register width. To emulate word-sized and halfword-sized byte-reversal, perform a rev8 rd,rs followed by a srai rd,rd,K, where K is XLEN-32 and XLEN-16, respectively.

§Forms

Assembly: rev8.rv32 xd, xs1 Rust: rev8_rv32(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn rol<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: RolEmitter<T0, T1, T2>,

Rotate left (Register)

This instruction performs a rotate left of rs1 by the amount in least-significant log2(XLEN) bits of rs2.

§Forms

Assembly: rol xd, xs1, xs2 Rust: rol(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn rolw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: RolwEmitter<T0, T1, T2>,

Rotate left word (Register)

This instruction performs a rotate left of the least-significant word of rs1 by the amount in least-significant 5 bits of rs2. The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.

§Forms

Assembly: rolw xd, xs1, xs2 Rust: rolw(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn ror<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: RorEmitter<T0, T1, T2>,

Rotate right (Register)

This instruction performs a rotate right of rs1 by the amount in least-significant log2(XLEN) bits of rs2.

§Forms

Assembly: ror xd, xs1, xs2 Rust: ror(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn rori<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
where Self: RoriEmitter<T0, T1, T2>,

Rotate right (Immediate)

This instruction performs a rotate right of rs1 by the amount in the least-significant log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.

§Forms

Assembly: rori xd, xs1, shamt Rust: rori(rd, rs1, shamtd)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtd — Immediate encoding value.

Source

pub fn rori_rv32<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
where Self: RoriRv32Emitter<T0, T1, T2>,

Rotate right (Immediate)

This instruction performs a rotate right of rs1 by the amount in the least-significant log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.

§Forms

Assembly: rori.rv32 xd, xs1, shamt Rust: rori_rv32(rd, rs1, shamtw)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtw — Immediate encoding value.

Source

pub fn roriw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
where Self: RoriwEmitter<T0, T1, T2>,

Rotate right word (Immediate)

This instruction performs a rotate right on the least-significant word of rs1 by the amount in the least-significant log2(XLEN) bits of shamt. The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.

§Forms

Assembly: roriw xd, xs1, shamt Rust: roriw(rd, rs1, shamtw)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtw — Immediate encoding value.

Source

pub fn rorw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: RorwEmitter<T0, T1, T2>,

Rotate right word (Register)

This instruction performs a rotate right on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2. The resultant word is sign-extended by copying bit 31 to all of the more-significant bits.

§Forms

Assembly: rorw xd, xs1, xs2 Rust: rorw(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sb<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: SbEmitter<T0, T1, T2>,

Store byte

Store 8 bits of data from register rs2 to an address formed by adding rs1 to a signed offset.

§Forms

Assembly: sb xs2, imm(xs1) Rust: sb(rs1, rs2, imm)

§Arguments

rs1 — Memory base register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn sbreak(&mut self)
where Self: SbreakEmitter,

RISC-V sbreak instruction.

§Forms

Assembly: sbreak Rust: sbreak()

§Arguments

Source

pub fn sc_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: ScDEmitter<T0, T1, T2, T3, T4>,

Store conditional doubleword

sc.d conditionally writes a doubleword in rs2 to the address in rs1: the sc.d succeeds only if the reservation is still valid and the reservation set contains the bytes being written. If the sc.d succeeds, the instruction writes the doubleword in rs2 to memory, and it writes zero to rd. If the sc.d fails, the instruction does not write to memory, and it writes a nonzero value to rd. For the purposes of memory protection, a failed sc.d may be treated like a store. Regardless of success or failure, executing an sc.d instruction invalidates any reservation held by this hart.

The failure code with value 1 encodes an unspecified failure. Other failure codes are reserved at this time. Portable software should only assume the failure code will be non-zero.

A store-conditional instruction to a scratch word of memory should be used to forcibly invalidate any existing load reservation:

during a preemptive context switch, and
if necessary when changing virtual to physical address mappings, such as when migrating pages that might contain an active reservation.

§The invalidation of a hart’s reservation when it executes an LR or SC imply that a hart can only hold one reservation at a time, and that an SC can only pair with the most recent LR, and LR with the next following SC, in program order. This is a restriction to the Atomicity Axiom in Section 18.1 that ensures software runs correctly on expected common implementations that operate in this manner.

An SC instruction can never be observed by another RISC-V hart before the LR instruction that established the reservation.

§[NOTE]

The LR/SC sequence can be given acquire semantics by setting the aq bit on the LR instruction. The LR/SC sequence can be given release semantics by by setting the rl bit on the SC instruction. Assuming suitable mappings for other atomic operations, setting the aq bit on the LR instruction, and setting the rl bit on the SC instruction makes the LR/SC sequence sequentially consistent in the C++ memory_order_seq_cst sense. Such a sequence does not act as a fence for ordering ordinary load and store instructions before and after the sequence. Specific instruction mappings for other C++ atomic operations, or stronger notions of “sequential consistency”, may require both bits to be set on either or both of the LR or SC instruction.

§If neither bit is set on either LR or SC, the LR/SC sequence can be observed to occur before or after surrounding memory operations from the same RISC-V hart. This can be appropriate when the LR/SC sequence is used to implement a parallel reduction operation.

Software should not set the rl bit on an LR instruction unless the aq bit is also set. LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those with both bits clear, but may result in lower performance.

§Forms

Assembly: sc.d xd, xs2, xs1 Rust: sc_d(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn sc_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: ScWEmitter<T0, T1, T2, T3, T4>,

Store conditional word

sc.w conditionally writes a word in rs2 to the address in rs1: the sc.w succeeds only if the reservation is still valid and the reservation set contains the bytes being written. If the sc.w succeeds, the instruction writes the word in rs2 to memory, and it writes zero to rd. If the sc.w fails, the instruction does not write to memory, and it writes a nonzero value to rd. For the purposes of memory protection, a failed sc.w may be treated like a store. Regardless of success or failure, executing an sc.w instruction invalidates any reservation held by this hart.

<%- if XLEN == 64 -%> [NOTE] If a value other than 0 or 1 is defined as a result for sc.w, the value will before sign-extended into rd. <%- end -%>

The failure code with value 1 encodes an unspecified failure. Other failure codes are reserved at this time. Portable software should only assume the failure code will be non-zero.

A store-conditional instruction to a scratch word of memory should be used to forcibly invalidate any existing load reservation:

during a preemptive context switch, and
if necessary when changing virtual to physical address mappings, such as when migrating pages that might contain an active reservation.

§The invalidation of a hart’s reservation when it executes an LR or SC imply that a hart can only hold one reservation at a time, and that an SC can only pair with the most recent LR, and LR with the next following SC, in program order. This is a restriction to the Atomicity Axiom in Section 18.1 that ensures software runs correctly on expected common implementations that operate in this manner.

An SC instruction can never be observed by another RISC-V hart before the LR instruction that established the reservation.

§[NOTE]

The LR/SC sequence can be given acquire semantics by setting the aq bit on the LR instruction. The LR/SC sequence can be given release semantics by by setting the rl bit on the SC instruction. Assuming suitable mappings for other atomic operations, setting the aq bit on the LR instruction, and setting the rl bit on the SC instruction makes the LR/SC sequence sequentially consistent in the C++ memory_order_seq_cst sense. Such a sequence does not act as a fence for ordering ordinary load and store instructions before and after the sequence. Specific instruction mappings for other C++ atomic operations, or stronger notions of “sequential consistency”, may require both bits to be set on either or both of the LR or SC instruction.

§If neither bit is set on either LR or SC, the LR/SC sequence can be observed to occur before or after surrounding memory operations from the same RISC-V hart. This can be appropriate when the LR/SC sequence is used to implement a parallel reduction operation.

Software should not set the rl bit on an LR instruction unless the aq bit is also set. LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those with both bits clear, but may result in lower performance.

§Forms

Assembly: sc.w xd, xs2, xs1 Rust: sc_w(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn scall(&mut self)
where Self: ScallEmitter,

RISC-V scall instruction.

§Forms

Assembly: scall Rust: scall()

§Arguments

Source

pub fn sctrclr(&mut self)
where Self: SctrclrEmitter,

RISC-V sctrclr instruction.

§Forms

Assembly: sctrclr sctrclr Rust: sctrclr()

pub fn sext_h<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: SextHEmitter<T0, T1>,

Sign-extend halfword

This instruction sign-extends the least-significant halfword in the source to XLEN by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits.

§Forms

Assembly: sext.h xd, xs1 Rust: sext_h(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn sext_w<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: SextWEmitter<T0, T1>,

RISC-V sext.w instruction.

§Forms

Assembly: sext.w rd rs1 Rust: sext_w(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn sfence_inval_ir(&mut self)
where Self: SfenceInvalIrEmitter,

Order implicit page table reads after invalidation

The sfence.inval.ir instruction guarantees that any previous sinval.vma instructions executed by the current hart are ordered before subsequent implicit references by that hart to the memory-management data structures.

§Forms

Assembly: sfence.inval.ir "" Rust: sfence_inval_ir()

§Arguments

Source

pub fn sfence_vma<T0, T1>(&mut self, rs1: T0, rs2: T1)
where Self: SfenceVmaEmitter<T0, T1>,

Supervisor memory-management fence

The supervisor memory-management fence instruction SFENCE.VMA is used to synchronize updates to in-memory memory-management data structures with current execution. Instruction execution causes implicit reads and writes to these data structures; however, these implicit references are ordinarily not ordered with respect to explicit loads and stores. Executing an SFENCE.VMA instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before certain implicit references by subsequent instructions in that hart to the memory-management data structures. The specific set of operations ordered by SFENCE.VMA is determined by rs1 and rs2, as described below. SFENCE.VMA is also used to invalidate entries in the address-translation cache associated with a hart (see <<sv32algorithm>>). Further details on the behavior of this instruction are described in <<virt-control>> and <<pmp-vmem>>.

§[NOTE]

SFENCE.VMA orders only the local hart’s implicit references to the memory-management data structures.

§[NOTE]

§Consequently, other harts must be notified separately when the memory-management data structures have been modified. One approach is to use 1) a local data fence to ensure local writes are visible globally, then 2) an interprocessor interrupt to the other thread, then 3) a local SFENCE.VMA in the interrupt handler of the remote thread, and finally 4) signal back to originating thread that operation is complete. This is, of course, the RISC-V analog to a TLB shootdown.

For the common case that the translation data structures have only been modified for a single address mapping (i.e., one page or superpage), rs1 can specify a virtual address within that mapping to effect a translation fence for that mapping only. Furthermore, for the common case that the translation data structures have only been modified for a single address-space identifier, rs2 can specify the address space. The behavior of SFENCE.VMA depends on rs1 and rs2 as follows:

If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. The fence also invalidates all address-translation cache entries, for all address spaces.
If rs1=x0 and rs2≠x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see <<translation>>) are not ordered. The fence also invalidates all address-translation cache entries matching the address space identified by integer register rs2, except for entries containing global mappings.
If rs1≠x0 and rs2=x0, the fence orders only reads and writes made to leaf page table entries corresponding to the virtual address in rs1, for all address spaces. The fence also invalidates all address-translation cache entries that contain leaf page table entries corresponding to the virtual address in rs1, for all address spaces.
If rs1≠x0 and rs2≠x0, the fence orders only reads and writes made to leaf page table entries corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. The fence also invalidates all address-translation cache entries that contain leaf page table entries corresponding to the virtual address in rs1 and that match the address space identified by integer register rs2, except for entries containing global mappings.

§Arguments

rs1 — Source register.
rs2 — Source register.

Source

pub fn sfence_w_inval(&mut self)
where Self: SfenceWInvalEmitter,

Order writes before sfence

The sfence.w.inval instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before subsequent sinval.vma instructions executed by the same hart.

§Forms

Assembly: sfence.w.inval "" Rust: sfence_w_inval()

§Arguments

Source

pub fn sgtz<T0, T1>(&mut self, rd: T0, rs2: T1)
where Self: SgtzEmitter<T0, T1>,

RISC-V sgtz instruction.

§Forms

Assembly: sgtz rd rs2 Rust: sgtz(rd, rs2)

§Arguments

rd — Destination register.
rs2 — Source register.

Source

pub fn sh<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: ShEmitter<T0, T1, T2>,

Store halfword

Store 16 bits of data from register rs2 to an address formed by adding rs1 to a signed offset.

§Forms

Assembly: sh xs2, imm(xs1) Rust: sh(rs1, rs2, imm)

§Arguments

rs1 — Memory base register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn sh1add<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Sh1AddEmitter<T0, T1, T2>,

Shift left by 1 and add

This instruction shifts rs1 to the left by 1 bit and adds it to rs2.

§Forms

Assembly: sh1add xd, xs1, xs2 Rust: sh1add(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sh1add_uw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Sh1AddUwEmitter<T0, T1, T2>,

Shift unsigned word left by 1 and add

This instruction performs an XLEN-wide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 1 place.

§Forms

Assembly: sh1add.uw xd, xs1, xs2 Rust: sh1add_uw(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sh2add<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Sh2AddEmitter<T0, T1, T2>,

Shift left by 2 and add

This instruction shifts rs1 to the left by 2 places and adds it to rs2.

§Forms

Assembly: sh2add xd, xs1, xs2 Rust: sh2add(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sh2add_uw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Sh2AddUwEmitter<T0, T1, T2>,

Shift unsigned word left by 2 and add

This instruction performs an XLEN-wide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 2 places.

§Forms

Assembly: sh2add.uw xd, xs1, xs2 Rust: sh2add_uw(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sh3add<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Sh3AddEmitter<T0, T1, T2>,

Shift left by 3 and add

This instruction shifts rs1 to the left by 3 places and adds it to rs2.

§Forms

Assembly: sh3add xd, xs1, xs2 Rust: sh3add(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sh3add_uw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Sh3AddUwEmitter<T0, T1, T2>,

Shift unsigned word left by 3 and add

This instruction performs an XLEN-wide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 3 places.

§Forms

Assembly: sh3add.uw xd, xs1, xs2 Rust: sh3add_uw(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sha256sig0<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: Sha256Sig0Emitter<T0, T1>,

RISC-V sha256sig0 instruction.

§Forms

Assembly: sha256sig0 xd, xs1 Rust: sha256sig0(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn sha256sig1<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: Sha256Sig1Emitter<T0, T1>,

RISC-V sha256sig1 instruction.

§Forms

Assembly: sha256sig1 xd, xs1 Rust: sha256sig1(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn sha256sum0<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: Sha256Sum0Emitter<T0, T1>,

RISC-V sha256sum0 instruction.

§Forms

Assembly: sha256sum0 xd, xs1 Rust: sha256sum0(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn sha256sum1<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: Sha256Sum1Emitter<T0, T1>,

RISC-V sha256sum1 instruction.

§Forms

Assembly: sha256sum1 xd, xs1 Rust: sha256sum1(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn sha512sig0<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: Sha512Sig0Emitter<T0, T1>,

RISC-V sha512sig0 instruction.

§Forms

Assembly: sha512sig0 xd, xs1 Rust: sha512sig0(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn sha512sig0h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Sha512Sig0HEmitter<T0, T1, T2>,

RISC-V sha512sig0h instruction.

§Forms

Assembly: sha512sig0h xd, xs1, xs2 Rust: sha512sig0h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sha512sig0l<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Sha512Sig0LEmitter<T0, T1, T2>,

RISC-V sha512sig0l instruction.

§Forms

Assembly: sha512sig0l xd, xs1, xs2 Rust: sha512sig0l(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sha512sig1<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: Sha512Sig1Emitter<T0, T1>,

RISC-V sha512sig1 instruction.

§Forms

Assembly: sha512sig1 xd, xs1 Rust: sha512sig1(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn sha512sig1h<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Sha512Sig1HEmitter<T0, T1, T2>,

RISC-V sha512sig1h instruction.

§Forms

Assembly: sha512sig1h xd, xs1, xs2 Rust: sha512sig1h(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sha512sig1l<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Sha512Sig1LEmitter<T0, T1, T2>,

RISC-V sha512sig1l instruction.

§Forms

Assembly: sha512sig1l xd, xs1, xs2 Rust: sha512sig1l(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sha512sum0<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: Sha512Sum0Emitter<T0, T1>,

RISC-V sha512sum0 instruction.

§Forms

Assembly: sha512sum0 xd, xs1 Rust: sha512sum0(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn sha512sum0r<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Sha512Sum0REmitter<T0, T1, T2>,

RISC-V sha512sum0r instruction.

§Forms

Assembly: sha512sum0r xd, xs1, xs2 Rust: sha512sum0r(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sha512sum1<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: Sha512Sum1Emitter<T0, T1>,

RISC-V sha512sum1 instruction.

§Forms

Assembly: sha512sum1 xd, xs1 Rust: sha512sum1(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn sha512sum1r<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Sha512Sum1REmitter<T0, T1, T2>,

RISC-V sha512sum1r instruction.

§Forms

Assembly: sha512sum1r xd, xs1, xs2 Rust: sha512sum1r(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sinval_vma<T0, T1>(&mut self, rs1: T0, rs2: T1)
where Self: SinvalVmaEmitter<T0, T1>,

Invalidate cached address translations

§Forms

Assembly: sinval.vma xs1, xs2 Rust: sinval_vma(rs1, rs2)

§Arguments

rs1 — Source register.
rs2 — Source register.

Source

pub fn sll<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: SllEmitter<T0, T1, T2>,

Shift left logical

Shift the value in rs1 left by the value in the lower 6 bits of rs2, and store the result in rd.

§Forms

Assembly: sll xd, xs1, xs2 Rust: sll(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn slli<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
where Self: SlliEmitter<T0, T1, T2>,

Shift left logical immediate

Shift the value in rs1 left by shamt, and store the result in rd

§Forms

Assembly: slli xd, xs1, shamt Rust: slli(rd, rs1, shamtd)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtd — Immediate encoding value.

Source

pub fn slli_rv32<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
where Self: SlliRv32Emitter<T0, T1, T2>,

Shift left logical immediate

Shift the value in rs1 left by shamt, and store the result in rd

§Forms

Assembly: slli.rv32 xd, xs1, shamt Rust: slli_rv32(rd, rs1, shamtw)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtw — Immediate encoding value.

Source

pub fn slli_uw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
where Self: SlliUwEmitter<T0, T1, T2>,

Shift left unsigned word (Immediate)

This instruction takes the least-significant word of rs1, zero-extends it, and shifts it left by the immediate.

[NOTE] This instruction is the same as slli with zext.w performed on rs1 before shifting.

§Forms

Assembly: slli.uw xd, xs1, shamt Rust: slli_uw(rd, rs1, shamtd)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtd — Immediate encoding value.

Source

pub fn slliw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
where Self: SlliwEmitter<T0, T1, T2>,

Shift left logical immediate word

Shift the 32-bit value in rs1 left by shamt, and store the sign-extended result in rd

§Forms

Assembly: slliw xd, xs1, shamt Rust: slliw(rd, rs1, shamtw)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtw — Immediate encoding value.

Source

pub fn sllw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: SllwEmitter<T0, T1, T2>,

Shift left logical word

Shift the 32-bit value in rs1 left by the value in the lower 5 bits of rs2, and store the sign-extended result in rd.

§Forms

Assembly: sllw xd, xs1, xs2 Rust: sllw(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn slt<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: SltEmitter<T0, T1, T2>,

Set on less than

Places the value 1 in register rd if register rs1 is less than the value in register rs2, where both sources are treated as signed numbers, else 0 is written to rd.

§Forms

Assembly: slt xd, xs1, rs2 Rust: slt(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn slti<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: SltiEmitter<T0, T1, T2>,

Set on less than immediate

Places the value 1 in register rd if register rs1 is less than the sign-extended immediate when both are treated as signed numbers, else 0 is written to rd.

§Forms

Assembly: slti xd, xs1, imm Rust: slti(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Source register.
imm — Immediate encoding value.

Source

pub fn sltiu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: SltiuEmitter<T0, T1, T2>,

Set on less than immediate unsigned

Places the value 1 in register rd if register rs1 is less than the sign-extended immediate when both are treated as unsigned numbers (i.e., the immediate is first sign-extended to XLEN bits then treated as an unsigned number), else 0 is written to rd.

NOTE: sltiu rd, rs1, 1 sets rd to 1 if rs1 equals zero, otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs).

§Forms

Assembly: sltiu xd, xs1, imm Rust: sltiu(rd, rs1, imm)

§Arguments

rd — Destination register.
rs1 — Source register.
imm — Immediate encoding value.

Source

pub fn sltu<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: SltuEmitter<T0, T1, T2>,

Set on less than unsigned

Places the value 1 in register rd if register rs1 is less than the value in register rs2, where both sources are treated as unsigned numbers, else 0 is written to rd.

§Forms

Assembly: sltu xd, xs1, xs2 Rust: sltu(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sltz<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: SltzEmitter<T0, T1>,

RISC-V sltz instruction.

§Forms

Assembly: sltz rd rs1 Rust: sltz(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn sm3p0<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: Sm3P0Emitter<T0, T1>,

RISC-V sm3p0 instruction.

§Forms

Assembly: sm3p0 xd, xs1 Rust: sm3p0(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn sm3p1<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: Sm3P1Emitter<T0, T1>,

RISC-V sm3p1 instruction.

§Forms

Assembly: sm3p1 xd, xs1 Rust: sm3p1(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn sm4ed<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
where Self: Sm4EdEmitter<T0, T1, T2, T3>,

RISC-V sm4ed instruction.

§Forms

Assembly: sm4ed xd, xs1, xs2, bs Rust: sm4ed(rd, rs1, rs2, bs)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
bs — Immediate encoding value.

Source

pub fn sm4ks<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
where Self: Sm4KsEmitter<T0, T1, T2, T3>,

RISC-V sm4ks instruction.

§Forms

Assembly: sm4ks xd, xs1, xs2, bs Rust: sm4ks(rd, rs1, rs2, bs)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.
bs — Immediate encoding value.

Source

pub fn snez<T0, T1>(&mut self, rd: T0, rs2: T1)
where Self: SnezEmitter<T0, T1>,

RISC-V snez instruction.

§Forms

Assembly: snez rd rs2 Rust: snez(rd, rs2)

§Arguments

rd — Destination register.
rs2 — Source register.

Source

pub fn sra<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: SraEmitter<T0, T1, T2>,

Shift right arithmetic

Arithmetic shift the value in rs1 right by the value in the lower 5 bits of rs2, and store the result in rd.

§Forms

Assembly: sra xd, xs1, xs2 Rust: sra(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn srai<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtd: T2)
where Self: SraiEmitter<T0, T1, T2>,

Shift right arithmetic immediate

Arithmetic shift (the original sign bit is copied into the vacated upper bits) the value in rs1 right by shamt, and store the result in rd.

§Forms

Assembly: srai xd, xs1, shamt Rust: srai(rd, rs1, shamtd)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtd — Immediate encoding value.

Source

pub fn srai_rv32<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
where Self: SraiRv32Emitter<T0, T1, T2>,

Shift right arithmetic immediate

Arithmetic shift (the original sign bit is copied into the vacated upper bits) the value in rs1 right by shamt, and store the result in rd.

§Forms

Assembly: srai.rv32 xd, xs1, shamt Rust: srai_rv32(rd, rs1, shamtw)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtw — Immediate encoding value.

Source

pub fn sraiw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, shamtw: T2)
where Self: SraiwEmitter<T0, T1, T2>,

Shift right arithmetic immediate word

Arithmetic shift (the original sign bit is copied into the vacated upper bits) the 32-bit value in rs1 right by shamt, and store the sign-extended result in rd.

§Forms

Assembly: sraiw xd, xs1, shamt Rust: sraiw(rd, rs1, shamtw)

§Arguments

rd — Destination register.
rs1 — Source register.
shamtw — Immediate encoding value.

Source

pub fn sraw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: SrawEmitter<T0, T1, T2>,

Shift right arithmetic word

Arithmetic shift the 32-bit value in rs1 right by the value in the lower 5 bits of rs2, and store the sign-extended result in rd.

§Forms

Assembly: sraw xd, xs1, xs2 Rust: sraw(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sret(&mut self)
where Self: SretEmitter,

Supervisor Exception Return

Returns from an exception.

When sret is allowed to execute, its behavior depends on whether or not the current privilege mode is virtualized.

When the current privilege mode is (H)S-mode or M-mode

sret sets hstatus.HPV = 0, mstatus.SPP = 0, mstatus.SIE = mstatus.SPIE, and mstatus.SPIE = 1, changes the privilege mode according to the table below, and then jumps to the address in sepc.

.Next privilege mode following an sret in (H)S-mode or M-mode [%autowidth] |=== | [.rotate]#mstatus.SPP# | [.rotate]#hstatus.SPV# .>| Mode after sret

| 0 | 0 | U-mode | 0 | 1 | VU-mode | 1 | 0 | (H)S-mode | 1 | 1 | VS-mode |===

When the current privilege mode is VS-mode

sret sets vsstatus.SPP = 0, vsstatus.SIE = vstatus.SPIE, and vsstatus.SPIE = 1, changes the privilege mode according to the table below, and then jumps to the address in vsepc.

.Next privilege mode following an sret in (H)S-mode or M-mode [%autowidth] |=== | [.rotate]#vsstatus.SPP# .>| Mode after sret

| 0 | VU-mode | 1 | VS-mode |===

§Forms

Assembly: sret "" Rust: sret()

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn ssamoswap_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: SsamoswapDEmitter<T0, T1, T2, T3, T4>,

RISC-V ssamoswap.d instruction.

§Forms

Assembly: ssamoswap.d xd, xs1, xs2, aq, rl Rust: ssamoswap_d(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

Source

pub fn ssamoswap_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: SsamoswapWEmitter<T0, T1, T2, T3, T4>,

RISC-V ssamoswap.w instruction.

§Forms

Assembly: ssamoswap.w xd, xs1, xs2, aq, rl Rust: ssamoswap_w(rd, rs1, rs2, aq, rl)

§Arguments

rd — Destination register.
rs1 — Memory base register.
rs2 — Source register.
aq — Acquire-order bit.
rl — Release-order bit; retained for the existing emitter API.

rd — Destination register.

Source

pub fn sub<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: SubEmitter<T0, T1, T2>,

Subtract

Subtract the value in rs2 from rs1, and store the result in rd

§Forms

Assembly: sub xd, xs1, xs2 Rust: sub(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn subw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: SubwEmitter<T0, T1, T2>,

Subtract word

Subtract the 32-bit values in rs2 from rs1, and store the sign-extended result in rd

§Forms

Assembly: subw xd, xs1, xs2 Rust: subw(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn sw<T0, T1, T2>(&mut self, rs1: T0, rs2: T1, imm: T2)
where Self: SwEmitter<T0, T1, T2>,

Store word

Store 32 bits of data from register rs2 to an address formed by adding rs1 to a signed offset.

§Forms

Assembly: sw xs2, imm(xs1) Rust: sw(rs1, rs2, imm)

§Arguments

rs1 — Memory base register.
rs2 — Source register.
imm — Immediate encoding value.

Source

pub fn unzip<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: UnzipEmitter<T0, T1>,

Bit deinterleave

This instruction gathers bits from the high and low halves of the source word into odd/even bit positions in the destination word. It is the inverse of the zip instruction. This instruction is available only on RV32.

§Forms

Assembly: unzip xd, xs1 Rust: unzip(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn vaadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VaaddVvEmitter<T0, T1, T2, T3>,

RISC-V vaadd.vv instruction.

§Forms

Assembly: vaadd.vv vm, vs2, vs1, vd Rust: vaadd_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vaadd_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VaaddVxEmitter<T0, T1, T2, T3>,

RISC-V vaadd.vx instruction.

§Forms

Assembly: vaadd.vx vm, vs2, xs1, vd Rust: vaadd_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vaaddu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VaadduVvEmitter<T0, T1, T2, T3>,

RISC-V vaaddu.vv instruction.

§Forms

Assembly: vaaddu.vv vm, vs2, vs1, vd Rust: vaaddu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vaaddu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VaadduVxEmitter<T0, T1, T2, T3>,

RISC-V vaaddu.vx instruction.

§Forms

Assembly: vaaddu.vx vm, vs2, xs1, vd Rust: vaaddu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vadc_vim<T0, T1, T2>(&mut self, vd: T0, vs2: T1, simm5: T2)
where Self: VadcVimEmitter<T0, T1, T2>,

RISC-V vadc.vim instruction.

§Forms

Assembly: vadc.vim vs2, vd, imm Rust: vadc_vim(vd, vs2, simm5)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.

Source

pub fn vadc_vvm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VadcVvmEmitter<T0, T1, T2>,

RISC-V vadc.vvm instruction.

§Forms

Assembly: vadc.vvm vs2, vs1, vd Rust: vadc_vvm(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vadc_vxm<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
where Self: VadcVxmEmitter<T0, T1, T2>,

RISC-V vadc.vxm instruction.

§Forms

Assembly: vadc.vxm vs2, xs1, vd Rust: vadc_vxm(vd, rs1, vs2)

§Arguments

vd — Vector register operand.
rs1 — Source register.
vs2 — Vector register operand.

Source

pub fn vadd_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
where Self: VaddViEmitter<T0, T1, T2, T3>,

RISC-V vadd.vi instruction.

§Forms

Assembly: vadd.vi vm, vs2, vd, imm Rust: vadd_vi(vd, vs2, simm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VaddVvEmitter<T0, T1, T2, T3>,

RISC-V vadd.vv instruction.

§Forms

Assembly: vadd.vv vm, vs2, vs1, vd Rust: vadd_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vadd_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VaddVxEmitter<T0, T1, T2, T3>,

RISC-V vadd.vx instruction.

§Forms

Assembly: vadd.vx vm, vs2, xs1, vd Rust: vadd_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vaesdf_vs<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: VaesdfVsEmitter<T0, T1>,

RISC-V vaesdf.vs instruction.

§Forms

Assembly: vaesdf.vs vs2, vd Rust: vaesdf_vs(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vaesdf_vv<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: VaesdfVvEmitter<T0, T1>,

RISC-V vaesdf.vv instruction.

§Forms

Assembly: vaesdf.vv vs2, vd Rust: vaesdf_vv(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vaesdm_vs<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: VaesdmVsEmitter<T0, T1>,

RISC-V vaesdm.vs instruction.

§Forms

Assembly: vaesdm.vs vs2, vd Rust: vaesdm_vs(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vaesdm_vv<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: VaesdmVvEmitter<T0, T1>,

RISC-V vaesdm.vv instruction.

§Forms

Assembly: vaesdm.vv vs2, vd Rust: vaesdm_vv(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vaesef_vs<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: VaesefVsEmitter<T0, T1>,

RISC-V vaesef.vs instruction.

§Forms

Assembly: vaesef.vs vs2, vd Rust: vaesef_vs(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vaesef_vv<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: VaesefVvEmitter<T0, T1>,

RISC-V vaesef.vv instruction.

§Forms

Assembly: vaesef.vv vs2, vd Rust: vaesef_vv(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vaesem_vs<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: VaesemVsEmitter<T0, T1>,

RISC-V vaesem.vs instruction.

§Forms

Assembly: vaesem.vs vs2, vd Rust: vaesem_vs(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vaesem_vv<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: VaesemVvEmitter<T0, T1>,

RISC-V vaesem.vv instruction.

§Forms

Assembly: vaesem.vv vs2, vd Rust: vaesem_vv(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vaeskf1_vi<T0, T1, T2>(&mut self, vd: T0, vs2: T1, zimm5: T2)
where Self: Vaeskf1ViEmitter<T0, T1, T2>,

RISC-V vaeskf1.vi instruction.

§Forms

Assembly: vaeskf1.vi vs2, vd, imm Rust: vaeskf1_vi(vd, vs2, zimm5)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.

Source

pub fn vaeskf2_vi<T0, T1, T2>(&mut self, vd: T0, vs2: T1, zimm5: T2)
where Self: Vaeskf2ViEmitter<T0, T1, T2>,

RISC-V vaeskf2.vi instruction.

§Forms

Assembly: vaeskf2.vi vs2, vd, imm Rust: vaeskf2_vi(vd, vs2, zimm5)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.

Source

pub fn vaesz_vs<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: VaeszVsEmitter<T0, T1>,

Vector AES round zero

§Forms

Assembly: vaesz.vs vs2, vd Rust: vaesz_vs(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vand_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
where Self: VandViEmitter<T0, T1, T2, T3>,

RISC-V vand.vi instruction.

§Forms

Assembly: vand.vi vm, vs2, vd, imm Rust: vand_vi(vd, vs2, simm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vand_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VandVvEmitter<T0, T1, T2, T3>,

RISC-V vand.vv instruction.

§Forms

Assembly: vand.vv vm, vs2, vs1, vd Rust: vand_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vand_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VandVxEmitter<T0, T1, T2, T3>,

RISC-V vand.vx instruction.

§Forms

Assembly: vand.vx vm, vs2, xs1, vd Rust: vand_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vandn_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VandnVvEmitter<T0, T1, T2, T3>,

RISC-V vandn.vv instruction.

§Forms

Assembly: vandn.vv vm, vs2, vs1, vd Rust: vandn_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vandn_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VandnVxEmitter<T0, T1, T2, T3>,

RISC-V vandn.vx instruction.

§Forms

Assembly: vandn.vx vm, vs2, xs1, vd Rust: vandn_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vasub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VasubVvEmitter<T0, T1, T2, T3>,

RISC-V vasub.vv instruction.

§Forms

Assembly: vasub.vv vm, vs2, vs1, vd Rust: vasub_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vasub_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VasubVxEmitter<T0, T1, T2, T3>,

RISC-V vasub.vx instruction.

§Forms

Assembly: vasub.vx vm, vs2, xs1, vd Rust: vasub_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vasubu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VasubuVvEmitter<T0, T1, T2, T3>,

RISC-V vasubu.vv instruction.

§Forms

Assembly: vasubu.vv vm, vs2, vs1, vd Rust: vasubu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vasubu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VasubuVxEmitter<T0, T1, T2, T3>,

RISC-V vasubu.vx instruction.

§Forms

Assembly: vasubu.vx vm, vs2, xs1, vd Rust: vasubu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vbrev8_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: Vbrev8VEmitter<T0, T1, T2>,

RISC-V vbrev8.v instruction.

§Forms

Assembly: vbrev8.v vm, vs2, vd Rust: vbrev8_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vbrev_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VbrevVEmitter<T0, T1, T2>,

RISC-V vbrev.v instruction.

§Forms

Assembly: vbrev.v vm, vs2, vd Rust: vbrev_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vclmul_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VclmulVvEmitter<T0, T1, T2, T3>,

RISC-V vclmul.vv instruction.

§Forms

Assembly: vclmul.vv vm, vs2, vs1, vd Rust: vclmul_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vclmul_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VclmulVxEmitter<T0, T1, T2, T3>,

RISC-V vclmul.vx instruction.

§Forms

Assembly: vclmul.vx vm, vs2, xs1, vd Rust: vclmul_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vclmulh_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VclmulhVvEmitter<T0, T1, T2, T3>,

RISC-V vclmulh.vv instruction.

§Forms

Assembly: vclmulh.vv vm, vs2, vs1, vd Rust: vclmulh_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vclmulh_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VclmulhVxEmitter<T0, T1, T2, T3>,

RISC-V vclmulh.vx instruction.

§Forms

Assembly: vclmulh.vx vm, vs2, xs1, vd Rust: vclmulh_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vclz_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VclzVEmitter<T0, T1, T2>,

RISC-V vclz.v instruction.

§Forms

Assembly: vclz.v vm, vs2, vd Rust: vclz_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vcompress_vm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VcompressVmEmitter<T0, T1, T2>,

RISC-V vcompress.vm instruction.

§Forms

Assembly: vcompress.vm vs2, vs1, vd Rust: vcompress_vm(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vcpop_m<T0, T1, T2>(&mut self, rd: T0, vs2: T1, vm: T2)
where Self: VcpopMEmitter<T0, T1, T2>,

RISC-V vcpop.m instruction.

§Forms

Assembly: vcpop.m vm, vs2, xd Rust: vcpop_m(rd, vs2, vm)

§Arguments

rd — Destination register.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vcpop_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VcpopVEmitter<T0, T1, T2>,

RISC-V vcpop.v instruction.

§Forms

Assembly: vcpop.v vm, vs2, vd Rust: vcpop_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vctz_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VctzVEmitter<T0, T1, T2>,

RISC-V vctz.v instruction.

§Forms

Assembly: vctz.v vm, vs2, vd Rust: vctz_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vdiv_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VdivVvEmitter<T0, T1, T2, T3>,

RISC-V vdiv.vv instruction.

§Forms

Assembly: vdiv.vv vm, vs2, vs1, vd Rust: vdiv_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vdiv_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VdivVxEmitter<T0, T1, T2, T3>,

RISC-V vdiv.vx instruction.

§Forms

Assembly: vdiv.vx vm, vs2, xs1, vd Rust: vdiv_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vdivu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VdivuVvEmitter<T0, T1, T2, T3>,

RISC-V vdivu.vv instruction.

§Forms

Assembly: vdivu.vv vm, vs2, vs1, vd Rust: vdivu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vdivu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VdivuVxEmitter<T0, T1, T2, T3>,

RISC-V vdivu.vx instruction.

§Forms

Assembly: vdivu.vx vm, vs2, xs1, vd Rust: vdivu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfadd_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfaddVfEmitter<T0, T1, T2, T3>,

RISC-V vfadd.vf instruction.

§Forms

Assembly: vfadd.vf vm, vs2, xs1, vd Rust: vfadd_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfaddVvEmitter<T0, T1, T2, T3>,

RISC-V vfadd.vv instruction.

§Forms

Assembly: vfadd.vv vm, vs2, vs1, vd Rust: vfadd_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfclass_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfclassVEmitter<T0, T1, T2>,

RISC-V vfclass.v instruction.

§Forms

Assembly: vfclass.v vm, vs2, vd Rust: vfclass_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfcvt_f_x_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfcvtFXVEmitter<T0, T1, T2>,

RISC-V vfcvt.f.x.v instruction.

§Forms

Assembly: vfcvt.f.x.v vm, vs2, vd Rust: vfcvt_f_x_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfcvt_f_xu_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfcvtFXuVEmitter<T0, T1, T2>,

RISC-V vfcvt.f.xu.v instruction.

§Forms

Assembly: vfcvt.f.xu.v vm, vs2, vd Rust: vfcvt_f_xu_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfcvt_rtz_x_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfcvtRtzXFVEmitter<T0, T1, T2>,

RISC-V vfcvt.rtz.x.f.v instruction.

§Forms

Assembly: vfcvt.rtz.x.f.v vm, vs2, vd Rust: vfcvt_rtz_x_f_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfcvt_rtz_xu_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfcvtRtzXuFVEmitter<T0, T1, T2>,

RISC-V vfcvt.rtz.xu.f.v instruction.

§Forms

Assembly: vfcvt.rtz.xu.f.v vm, vs2, vd Rust: vfcvt_rtz_xu_f_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfcvt_x_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfcvtXFVEmitter<T0, T1, T2>,

RISC-V vfcvt.x.f.v instruction.

§Forms

Assembly: vfcvt.x.f.v vm, vs2, vd Rust: vfcvt_x_f_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfcvt_xu_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfcvtXuFVEmitter<T0, T1, T2>,

RISC-V vfcvt.xu.f.v instruction.

§Forms

Assembly: vfcvt.xu.f.v vm, vs2, vd Rust: vfcvt_xu_f_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfdiv_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfdivVfEmitter<T0, T1, T2, T3>,

RISC-V vfdiv.vf instruction.

§Forms

Assembly: vfdiv.vf vm, vs2, xs1, vd Rust: vfdiv_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfdiv_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfdivVvEmitter<T0, T1, T2, T3>,

RISC-V vfdiv.vv instruction.

§Forms

Assembly: vfdiv.vv vm, vs2, vs1, vd Rust: vfdiv_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfirst_m<T0, T1, T2>(&mut self, rd: T0, vs2: T1, vm: T2)
where Self: VfirstMEmitter<T0, T1, T2>,

RISC-V vfirst.m instruction.

§Forms

Assembly: vfirst.m vm, vs2, xd Rust: vfirst_m(rd, vs2, vm)

§Arguments

rd — Destination register.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfmacc_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfmaccVfEmitter<T0, T1, T2, T3>,

RISC-V vfmacc.vf instruction.

§Forms

Assembly: vfmacc.vf vm, vs2, xs1, vd Rust: vfmacc_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfmacc_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfmaccVvEmitter<T0, T1, T2, T3>,

RISC-V vfmacc.vv instruction.

§Forms

Assembly: vfmacc.vv vm, vs2, vs1, vd Rust: vfmacc_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfmadd_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfmaddVfEmitter<T0, T1, T2, T3>,

RISC-V vfmadd.vf instruction.

§Forms

Assembly: vfmadd.vf vm, vs2, xs1, vd Rust: vfmadd_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfmadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfmaddVvEmitter<T0, T1, T2, T3>,

RISC-V vfmadd.vv instruction.

§Forms

Assembly: vfmadd.vv vm, vs2, vs1, vd Rust: vfmadd_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfmax_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfmaxVfEmitter<T0, T1, T2, T3>,

RISC-V vfmax.vf instruction.

§Forms

Assembly: vfmax.vf vm, vs2, xs1, vd Rust: vfmax_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfmax_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfmaxVvEmitter<T0, T1, T2, T3>,

RISC-V vfmax.vv instruction.

§Forms

Assembly: vfmax.vv vm, vs2, vs1, vd Rust: vfmax_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfmerge_vfm<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
where Self: VfmergeVfmEmitter<T0, T1, T2>,

RISC-V vfmerge.vfm instruction.

§Forms

Assembly: vfmerge.vfm vs2, xs1, vd Rust: vfmerge_vfm(vd, rs1, vs2)

§Arguments

vd — Vector register operand.
rs1 — Source register.
vs2 — Vector register operand.

Source

pub fn vfmin_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfminVfEmitter<T0, T1, T2, T3>,

RISC-V vfmin.vf instruction.

§Forms

Assembly: vfmin.vf vm, vs2, xs1, vd Rust: vfmin_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfmin_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfminVvEmitter<T0, T1, T2, T3>,

RISC-V vfmin.vv instruction.

§Forms

Assembly: vfmin.vv vm, vs2, vs1, vd Rust: vfmin_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfmsac_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfmsacVfEmitter<T0, T1, T2, T3>,

RISC-V vfmsac.vf instruction.

§Forms

Assembly: vfmsac.vf vm, vs2, xs1, vd Rust: vfmsac_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfmsac_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfmsacVvEmitter<T0, T1, T2, T3>,

RISC-V vfmsac.vv instruction.

§Forms

Assembly: vfmsac.vv vm, vs2, vs1, vd Rust: vfmsac_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfmsub_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfmsubVfEmitter<T0, T1, T2, T3>,

RISC-V vfmsub.vf instruction.

§Forms

Assembly: vfmsub.vf vm, vs2, xs1, vd Rust: vfmsub_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfmsub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfmsubVvEmitter<T0, T1, T2, T3>,

RISC-V vfmsub.vv instruction.

§Forms

Assembly: vfmsub.vv vm, vs2, vs1, vd Rust: vfmsub_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfmul_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfmulVfEmitter<T0, T1, T2, T3>,

RISC-V vfmul.vf instruction.

§Forms

Assembly: vfmul.vf vm, vs2, xs1, vd Rust: vfmul_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfmul_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfmulVvEmitter<T0, T1, T2, T3>,

RISC-V vfmul.vv instruction.

§Forms

Assembly: vfmul.vv vm, vs2, vs1, vd Rust: vfmul_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfmv_f_s<T0, T1>(&mut self, rd: T0, vs2: T1)
where Self: VfmvFSEmitter<T0, T1>,

RISC-V vfmv.f.s instruction.

§Forms

Assembly: vfmv.f.s vs2, xd Rust: vfmv_f_s(rd, vs2)

§Arguments

rd — Destination register.
vs2 — Vector register operand.

Source

pub fn vfmv_s_f<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: VfmvSFEmitter<T0, T1>,

RISC-V vfmv.s.f instruction.

§Forms

Assembly: vfmv.s.f xs1, vd Rust: vfmv_s_f(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Source register.

Source

pub fn vfmv_v_f<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: VfmvVFEmitter<T0, T1>,

RISC-V vfmv.v.f instruction.

§Forms

Assembly: vfmv.v.f xs1, vd Rust: vfmv_v_f(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Source register.

Source

pub fn vfncvt_f_f_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfncvtFFWEmitter<T0, T1, T2>,

RISC-V vfncvt.f.f.w instruction.

§Forms

Assembly: vfncvt.f.f.w vm, vs2, vd Rust: vfncvt_f_f_w(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfncvt_f_x_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfncvtFXWEmitter<T0, T1, T2>,

RISC-V vfncvt.f.x.w instruction.

§Forms

Assembly: vfncvt.f.x.w vm, vs2, vd Rust: vfncvt_f_x_w(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfncvt_f_xu_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfncvtFXuWEmitter<T0, T1, T2>,

RISC-V vfncvt.f.xu.w instruction.

§Forms

Assembly: vfncvt.f.xu.w vm, vs2, vd Rust: vfncvt_f_xu_w(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfncvt_rod_f_f_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfncvtRodFFWEmitter<T0, T1, T2>,

RISC-V vfncvt.rod.f.f.w instruction.

§Forms

Assembly: vfncvt.rod.f.f.w vm, vs2, vd Rust: vfncvt_rod_f_f_w(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfncvt_rtz_x_f_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfncvtRtzXFWEmitter<T0, T1, T2>,

RISC-V vfncvt.rtz.x.f.w instruction.

§Forms

Assembly: vfncvt.rtz.x.f.w vm, vs2, vd Rust: vfncvt_rtz_x_f_w(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfncvt_rtz_xu_f_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfncvtRtzXuFWEmitter<T0, T1, T2>,

RISC-V vfncvt.rtz.xu.f.w instruction.

§Forms

Assembly: vfncvt.rtz.xu.f.w vm, vs2, vd Rust: vfncvt_rtz_xu_f_w(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfncvt_x_f_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfncvtXFWEmitter<T0, T1, T2>,

RISC-V vfncvt.x.f.w instruction.

§Forms

Assembly: vfncvt.x.f.w vm, vs2, vd Rust: vfncvt_x_f_w(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfncvt_xu_f_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfncvtXuFWEmitter<T0, T1, T2>,

RISC-V vfncvt.xu.f.w instruction.

§Forms

Assembly: vfncvt.xu.f.w vm, vs2, vd Rust: vfncvt_xu_f_w(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfncvtbf16_f_f_w<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: Vfncvtbf16FFWEmitter<T0, T1, T2>,

RISC-V vfncvtbf16.f.f.w instruction.

§Forms

Assembly: vfncvtbf16.f.f.w vm, vs2, vd Rust: vfncvtbf16_f_f_w(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfnmacc_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfnmaccVfEmitter<T0, T1, T2, T3>,

RISC-V vfnmacc.vf instruction.

§Forms

Assembly: vfnmacc.vf vm, vs2, xs1, vd Rust: vfnmacc_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfnmacc_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfnmaccVvEmitter<T0, T1, T2, T3>,

RISC-V vfnmacc.vv instruction.

§Forms

Assembly: vfnmacc.vv vm, vs2, vs1, vd Rust: vfnmacc_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfnmadd_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfnmaddVfEmitter<T0, T1, T2, T3>,

RISC-V vfnmadd.vf instruction.

§Forms

Assembly: vfnmadd.vf vm, vs2, xs1, vd Rust: vfnmadd_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfnmadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfnmaddVvEmitter<T0, T1, T2, T3>,

RISC-V vfnmadd.vv instruction.

§Forms

Assembly: vfnmadd.vv vm, vs2, vs1, vd Rust: vfnmadd_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfnmsac_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfnmsacVfEmitter<T0, T1, T2, T3>,

RISC-V vfnmsac.vf instruction.

§Forms

Assembly: vfnmsac.vf vm, vs2, xs1, vd Rust: vfnmsac_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfnmsac_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfnmsacVvEmitter<T0, T1, T2, T3>,

RISC-V vfnmsac.vv instruction.

§Forms

Assembly: vfnmsac.vv vm, vs2, vs1, vd Rust: vfnmsac_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfnmsub_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfnmsubVfEmitter<T0, T1, T2, T3>,

RISC-V vfnmsub.vf instruction.

§Forms

Assembly: vfnmsub.vf vm, vs2, xs1, vd Rust: vfnmsub_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfnmsub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfnmsubVvEmitter<T0, T1, T2, T3>,

RISC-V vfnmsub.vv instruction.

§Forms

Assembly: vfnmsub.vv vm, vs2, vs1, vd Rust: vfnmsub_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfrdiv_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfrdivVfEmitter<T0, T1, T2, T3>,

RISC-V vfrdiv.vf instruction.

§Forms

Assembly: vfrdiv.vf vm, vs2, xs1, vd Rust: vfrdiv_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfrec7_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: Vfrec7VEmitter<T0, T1, T2>,

RISC-V vfrec7.v instruction.

§Forms

Assembly: vfrec7.v vm, vs2, vd Rust: vfrec7_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfredmax_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfredmaxVsEmitter<T0, T1, T2, T3>,

RISC-V vfredmax.vs instruction.

§Forms

Assembly: vfredmax.vs vm, vs2, vs1, vd Rust: vfredmax_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfredmin_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfredminVsEmitter<T0, T1, T2, T3>,

RISC-V vfredmin.vs instruction.

§Forms

Assembly: vfredmin.vs vm, vs2, vs1, vd Rust: vfredmin_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfredosum_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfredosumVsEmitter<T0, T1, T2, T3>,

RISC-V vfredosum.vs instruction.

§Forms

Assembly: vfredosum.vs vm, vs2, vs1, vd Rust: vfredosum_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfredsum_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfredsumVsEmitter<T0, T1, T2, T3>,

RISC-V vfredsum.vs instruction.

§Forms

Assembly: vfredsum.vs vd vs1 vs2 vm Rust: vfredsum_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfredusum_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfredusumVsEmitter<T0, T1, T2, T3>,

RISC-V vfredusum.vs instruction.

§Forms

Assembly: vfredusum.vs vm, vs2, vs1, vd Rust: vfredusum_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfrsqrt7_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: Vfrsqrt7VEmitter<T0, T1, T2>,

RISC-V vfrsqrt7.v instruction.

§Forms

Assembly: vfrsqrt7.v vm, vs2, vd Rust: vfrsqrt7_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfrsub_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfrsubVfEmitter<T0, T1, T2, T3>,

RISC-V vfrsub.vf instruction.

§Forms

Assembly: vfrsub.vf vm, vs2, xs1, vd Rust: vfrsub_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfsgnj_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfsgnjVfEmitter<T0, T1, T2, T3>,

RISC-V vfsgnj.vf instruction.

§Forms

Assembly: vfsgnj.vf vm, vs2, xs1, vd Rust: vfsgnj_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfsgnj_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfsgnjVvEmitter<T0, T1, T2, T3>,

RISC-V vfsgnj.vv instruction.

§Forms

Assembly: vfsgnj.vv vm, vs2, vs1, vd Rust: vfsgnj_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfsgnjn_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfsgnjnVfEmitter<T0, T1, T2, T3>,

RISC-V vfsgnjn.vf instruction.

§Forms

Assembly: vfsgnjn.vf vm, vs2, xs1, vd Rust: vfsgnjn_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfsgnjn_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfsgnjnVvEmitter<T0, T1, T2, T3>,

RISC-V vfsgnjn.vv instruction.

§Forms

Assembly: vfsgnjn.vv vm, vs2, vs1, vd Rust: vfsgnjn_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfsgnjx_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfsgnjxVfEmitter<T0, T1, T2, T3>,

RISC-V vfsgnjx.vf instruction.

§Forms

Assembly: vfsgnjx.vf vm, vs2, xs1, vd Rust: vfsgnjx_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfsgnjx_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfsgnjxVvEmitter<T0, T1, T2, T3>,

RISC-V vfsgnjx.vv instruction.

§Forms

Assembly: vfsgnjx.vv vm, vs2, vs1, vd Rust: vfsgnjx_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfslide1down_vf<T0, T1, T2, T3>( &mut self, vd: T0, vs2: T1, rs1: T2, vm: T3, )
where Self: Vfslide1DownVfEmitter<T0, T1, T2, T3>,

RISC-V vfslide1down.vf instruction.

§Forms

Assembly: vfslide1down.vf vm, vs2, xs1, vd Rust: vfslide1down_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfslide1up_vf<T0, T1, T2, T3>( &mut self, vd: T0, vs2: T1, rs1: T2, vm: T3, )
where Self: Vfslide1UpVfEmitter<T0, T1, T2, T3>,

RISC-V vfslide1up.vf instruction.

§Forms

Assembly: vfslide1up.vf vm, vs2, xs1, vd Rust: vfslide1up_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfsqrt_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfsqrtVEmitter<T0, T1, T2>,

RISC-V vfsqrt.v instruction.

§Forms

Assembly: vfsqrt.v vm, vs2, vd Rust: vfsqrt_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfsub_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfsubVfEmitter<T0, T1, T2, T3>,

RISC-V vfsub.vf instruction.

§Forms

Assembly: vfsub.vf vm, vs2, xs1, vd Rust: vfsub_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfsub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfsubVvEmitter<T0, T1, T2, T3>,

RISC-V vfsub.vv instruction.

§Forms

Assembly: vfsub.vv vm, vs2, vs1, vd Rust: vfsub_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwadd_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfwaddVfEmitter<T0, T1, T2, T3>,

RISC-V vfwadd.vf instruction.

§Forms

Assembly: vfwadd.vf vm, vs2, xs1, vd Rust: vfwadd_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfwadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfwaddVvEmitter<T0, T1, T2, T3>,

RISC-V vfwadd.vv instruction.

§Forms

Assembly: vfwadd.vv vm, vs2, vs1, vd Rust: vfwadd_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwadd_wf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfwaddWfEmitter<T0, T1, T2, T3>,

RISC-V vfwadd.wf instruction.

§Forms

Assembly: vfwadd.wf vm, vs2, xs1, vd Rust: vfwadd_wf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfwadd_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfwaddWvEmitter<T0, T1, T2, T3>,

RISC-V vfwadd.wv instruction.

§Forms

Assembly: vfwadd.wv vm, vs2, vs1, vd Rust: vfwadd_wv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwcvt_f_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfwcvtFFVEmitter<T0, T1, T2>,

RISC-V vfwcvt.f.f.v instruction.

§Forms

Assembly: vfwcvt.f.f.v vm, vs2, vd Rust: vfwcvt_f_f_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwcvt_f_x_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfwcvtFXVEmitter<T0, T1, T2>,

RISC-V vfwcvt.f.x.v instruction.

§Forms

Assembly: vfwcvt.f.x.v vm, vs2, vd Rust: vfwcvt_f_x_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwcvt_f_xu_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfwcvtFXuVEmitter<T0, T1, T2>,

RISC-V vfwcvt.f.xu.v instruction.

§Forms

Assembly: vfwcvt.f.xu.v vm, vs2, vd Rust: vfwcvt_f_xu_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwcvt_rtz_x_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfwcvtRtzXFVEmitter<T0, T1, T2>,

RISC-V vfwcvt.rtz.x.f.v instruction.

§Forms

Assembly: vfwcvt.rtz.x.f.v vm, vs2, vd Rust: vfwcvt_rtz_x_f_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwcvt_rtz_xu_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfwcvtRtzXuFVEmitter<T0, T1, T2>,

RISC-V vfwcvt.rtz.xu.f.v instruction.

§Forms

Assembly: vfwcvt.rtz.xu.f.v vm, vs2, vd Rust: vfwcvt_rtz_xu_f_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwcvt_x_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfwcvtXFVEmitter<T0, T1, T2>,

RISC-V vfwcvt.x.f.v instruction.

§Forms

Assembly: vfwcvt.x.f.v vm, vs2, vd Rust: vfwcvt_x_f_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwcvt_xu_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VfwcvtXuFVEmitter<T0, T1, T2>,

RISC-V vfwcvt.xu.f.v instruction.

§Forms

Assembly: vfwcvt.xu.f.v vm, vs2, vd Rust: vfwcvt_xu_f_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwcvtbf16_f_f_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: Vfwcvtbf16FFVEmitter<T0, T1, T2>,

RISC-V vfwcvtbf16.f.f.v instruction.

§Forms

Assembly: vfwcvtbf16.f.f.v vm, vs2, vd Rust: vfwcvtbf16_f_f_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwmacc_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfwmaccVfEmitter<T0, T1, T2, T3>,

RISC-V vfwmacc.vf instruction.

§Forms

Assembly: vfwmacc.vf vm, vs2, xs1, vd Rust: vfwmacc_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfwmacc_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfwmaccVvEmitter<T0, T1, T2, T3>,

RISC-V vfwmacc.vv instruction.

§Forms

Assembly: vfwmacc.vv vm, vs2, vs1, vd Rust: vfwmacc_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwmaccbf16_vf<T0, T1, T2, T3>( &mut self, vd: T0, vs2: T1, rs1: T2, vm: T3, )
where Self: Vfwmaccbf16VfEmitter<T0, T1, T2, T3>,

RISC-V vfwmaccbf16.vf instruction.

§Forms

Assembly: vfwmaccbf16.vf vm, vs2, xs1, vd Rust: vfwmaccbf16_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfwmaccbf16_vv<T0, T1, T2, T3>( &mut self, vd: T0, vs1: T1, vs2: T2, vm: T3, )
where Self: Vfwmaccbf16VvEmitter<T0, T1, T2, T3>,

RISC-V vfwmaccbf16.vv instruction.

§Forms

Assembly: vfwmaccbf16.vv vm, vs2, vs1, vd Rust: vfwmaccbf16_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwmsac_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfwmsacVfEmitter<T0, T1, T2, T3>,

RISC-V vfwmsac.vf instruction.

§Forms

Assembly: vfwmsac.vf vm, vs2, xs1, vd Rust: vfwmsac_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfwmsac_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfwmsacVvEmitter<T0, T1, T2, T3>,

RISC-V vfwmsac.vv instruction.

§Forms

Assembly: vfwmsac.vv vm, vs2, vs1, vd Rust: vfwmsac_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwmul_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfwmulVfEmitter<T0, T1, T2, T3>,

RISC-V vfwmul.vf instruction.

§Forms

Assembly: vfwmul.vf vm, vs2, xs1, vd Rust: vfwmul_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfwmul_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfwmulVvEmitter<T0, T1, T2, T3>,

RISC-V vfwmul.vv instruction.

§Forms

Assembly: vfwmul.vv vm, vs2, vs1, vd Rust: vfwmul_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwnmacc_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfwnmaccVfEmitter<T0, T1, T2, T3>,

RISC-V vfwnmacc.vf instruction.

§Forms

Assembly: vfwnmacc.vf vm, vs2, xs1, vd Rust: vfwnmacc_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfwnmacc_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfwnmaccVvEmitter<T0, T1, T2, T3>,

RISC-V vfwnmacc.vv instruction.

§Forms

Assembly: vfwnmacc.vv vm, vs2, vs1, vd Rust: vfwnmacc_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwnmsac_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfwnmsacVfEmitter<T0, T1, T2, T3>,

RISC-V vfwnmsac.vf instruction.

§Forms

Assembly: vfwnmsac.vf vm, vs2, xs1, vd Rust: vfwnmsac_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfwnmsac_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfwnmsacVvEmitter<T0, T1, T2, T3>,

RISC-V vfwnmsac.vv instruction.

§Forms

Assembly: vfwnmsac.vv vm, vs2, vs1, vd Rust: vfwnmsac_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwredosum_vs<T0, T1, T2, T3>( &mut self, vd: T0, vs1: T1, vs2: T2, vm: T3, )
where Self: VfwredosumVsEmitter<T0, T1, T2, T3>,

RISC-V vfwredosum.vs instruction.

§Forms

Assembly: vfwredosum.vs vm, vs2, vs1, vd Rust: vfwredosum_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwredsum_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfwredsumVsEmitter<T0, T1, T2, T3>,

RISC-V vfwredsum.vs instruction.

§Forms

Assembly: vfwredsum.vs vd vs1 vs2 vm Rust: vfwredsum_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwredusum_vs<T0, T1, T2, T3>( &mut self, vd: T0, vs1: T1, vs2: T2, vm: T3, )
where Self: VfwredusumVsEmitter<T0, T1, T2, T3>,

RISC-V vfwredusum.vs instruction.

§Forms

Assembly: vfwredusum.vs vm, vs2, vs1, vd Rust: vfwredusum_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwsub_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfwsubVfEmitter<T0, T1, T2, T3>,

RISC-V vfwsub.vf instruction.

§Forms

Assembly: vfwsub.vf vm, vs2, xs1, vd Rust: vfwsub_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfwsub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfwsubVvEmitter<T0, T1, T2, T3>,

RISC-V vfwsub.vv instruction.

§Forms

Assembly: vfwsub.vv vm, vs2, vs1, vd Rust: vfwsub_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vfwsub_wf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VfwsubWfEmitter<T0, T1, T2, T3>,

RISC-V vfwsub.wf instruction.

§Forms

Assembly: vfwsub.wf vm, vs2, xs1, vd Rust: vfwsub_wf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vfwsub_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VfwsubWvEmitter<T0, T1, T2, T3>,

RISC-V vfwsub.wv instruction.

§Forms

Assembly: vfwsub.wv vm, vs2, vs1, vd Rust: vfwsub_wv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vghsh_vv<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VghshVvEmitter<T0, T1, T2>,

RISC-V vghsh.vv instruction.

§Forms

Assembly: vghsh.vv vs2, vs1, vd Rust: vghsh_vv(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vgmul_vv<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: VgmulVvEmitter<T0, T1>,

RISC-V vgmul.vv instruction.

§Forms

Assembly: vgmul.vv vs2, vd Rust: vgmul_vv(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vid_v<T0, T1>(&mut self, vd: T0, vm: T1)
where Self: VidVEmitter<T0, T1>,

RISC-V vid.v instruction.

§Forms

Assembly: vid.v vm, vd Rust: vid_v(vd, vm)

§Arguments

vd — Vector register operand.
vm — Vector mask control.

Source

pub fn viota_m<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: ViotaMEmitter<T0, T1, T2>,

RISC-V viota.m instruction.

§Forms

Assembly: viota.m vm, vs2, vd Rust: viota_m(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vl1r_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl1RVEmitter<T0, T1>,

RISC-V vl1r.v instruction.

§Forms

Assembly: vl1r.v vd rs1 Rust: vl1r_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl1re16_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl1Re16VEmitter<T0, T1>,

RISC-V vl1re16.v instruction.

§Forms

Assembly: vl1re16.v xs1, vd Rust: vl1re16_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl1re32_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl1Re32VEmitter<T0, T1>,

RISC-V vl1re32.v instruction.

§Forms

Assembly: vl1re32.v xs1, vd Rust: vl1re32_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl1re64_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl1Re64VEmitter<T0, T1>,

RISC-V vl1re64.v instruction.

§Forms

Assembly: vl1re64.v xs1, vd Rust: vl1re64_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl1re8_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl1Re8VEmitter<T0, T1>,

RISC-V vl1re8.v instruction.

§Forms

Assembly: vl1re8.v xs1, vd Rust: vl1re8_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl2r_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl2RVEmitter<T0, T1>,

RISC-V vl2r.v instruction.

§Forms

Assembly: vl2r.v vd rs1 Rust: vl2r_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl2re16_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl2Re16VEmitter<T0, T1>,

RISC-V vl2re16.v instruction.

§Forms

Assembly: vl2re16.v xs1, vd Rust: vl2re16_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl2re32_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl2Re32VEmitter<T0, T1>,

RISC-V vl2re32.v instruction.

§Forms

Assembly: vl2re32.v xs1, vd Rust: vl2re32_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl2re64_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl2Re64VEmitter<T0, T1>,

RISC-V vl2re64.v instruction.

§Forms

Assembly: vl2re64.v xs1, vd Rust: vl2re64_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl2re8_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl2Re8VEmitter<T0, T1>,

RISC-V vl2re8.v instruction.

§Forms

Assembly: vl2re8.v xs1, vd Rust: vl2re8_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl4r_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl4RVEmitter<T0, T1>,

RISC-V vl4r.v instruction.

§Forms

Assembly: vl4r.v vd rs1 Rust: vl4r_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl4re16_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl4Re16VEmitter<T0, T1>,

RISC-V vl4re16.v instruction.

§Forms

Assembly: vl4re16.v xs1, vd Rust: vl4re16_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl4re32_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl4Re32VEmitter<T0, T1>,

RISC-V vl4re32.v instruction.

§Forms

Assembly: vl4re32.v xs1, vd Rust: vl4re32_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl4re64_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl4Re64VEmitter<T0, T1>,

RISC-V vl4re64.v instruction.

§Forms

Assembly: vl4re64.v xs1, vd Rust: vl4re64_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl4re8_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl4Re8VEmitter<T0, T1>,

RISC-V vl4re8.v instruction.

§Forms

Assembly: vl4re8.v xs1, vd Rust: vl4re8_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl8r_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl8RVEmitter<T0, T1>,

RISC-V vl8r.v instruction.

§Forms

Assembly: vl8r.v vd rs1 Rust: vl8r_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl8re16_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl8Re16VEmitter<T0, T1>,

RISC-V vl8re16.v instruction.

§Forms

Assembly: vl8re16.v xs1, vd Rust: vl8re16_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl8re32_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl8Re32VEmitter<T0, T1>,

RISC-V vl8re32.v instruction.

§Forms

Assembly: vl8re32.v xs1, vd Rust: vl8re32_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl8re64_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl8Re64VEmitter<T0, T1>,

RISC-V vl8re64.v instruction.

§Forms

Assembly: vl8re64.v xs1, vd Rust: vl8re64_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vl8re8_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vl8Re8VEmitter<T0, T1>,

RISC-V vl8re8.v instruction.

§Forms

Assembly: vl8re8.v xs1, vd Rust: vl8re8_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vle16_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
where Self: Vle16VEmitter<T0, T1, T2, T3>,

RISC-V vle16.v instruction.

§Forms

Assembly: vle16.v vm, xs1, vd Rust: vle16_v(vd, rs1, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vle16ff_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
where Self: Vle16FfVEmitter<T0, T1, T2, T3>,

RISC-V vle16ff.v instruction.

§Forms

Assembly: vle16ff.v vm, xs1, vd Rust: vle16ff_v(vd, rs1, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vle1_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: Vle1VEmitter<T0, T1>,

RISC-V vle1.v instruction.

§Forms

Assembly: vle1.v vd rs1 Rust: vle1_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vle32_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
where Self: Vle32VEmitter<T0, T1, T2, T3>,

RISC-V vle32.v instruction.

§Forms

Assembly: vle32.v vm, xs1, vd Rust: vle32_v(vd, rs1, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vle32ff_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
where Self: Vle32FfVEmitter<T0, T1, T2, T3>,

RISC-V vle32ff.v instruction.

§Forms

Assembly: vle32ff.v vm, xs1, vd Rust: vle32ff_v(vd, rs1, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vle64_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
where Self: Vle64VEmitter<T0, T1, T2, T3>,

RISC-V vle64.v instruction.

§Forms

Assembly: vle64.v vm, xs1, vd Rust: vle64_v(vd, rs1, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vle64ff_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
where Self: Vle64FfVEmitter<T0, T1, T2, T3>,

RISC-V vle64ff.v instruction.

§Forms

Assembly: vle64ff.v vm, xs1, vd Rust: vle64ff_v(vd, rs1, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vle8_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
where Self: Vle8VEmitter<T0, T1, T2, T3>,

RISC-V vle8.v instruction.

§Forms

Assembly: vle8.v vm, xs1, vd Rust: vle8_v(vd, rs1, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vle8ff_v<T0, T1, T2, T3>(&mut self, vd: T0, rs1: T1, vm: T2, nf: T3)
where Self: Vle8FfVEmitter<T0, T1, T2, T3>,

RISC-V vle8ff.v instruction.

§Forms

Assembly: vle8ff.v vm, xs1, vd Rust: vle8ff_v(vd, rs1, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vlm_v<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: VlmVEmitter<T0, T1>,

RISC-V vlm.v instruction.

§Forms

Assembly: vlm.v xs1, vd Rust: vlm_v(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.

Source

pub fn vloxei16_v<T0, T1, T2, T3, T4>( &mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vloxei16VEmitter<T0, T1, T2, T3, T4>,

RISC-V vloxei16.v instruction.

§Forms

Assembly: vloxei16.v vm, vs2, xs1, vd Rust: vloxei16_v(vd, rs1, vs2, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vloxei32_v<T0, T1, T2, T3, T4>( &mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vloxei32VEmitter<T0, T1, T2, T3, T4>,

RISC-V vloxei32.v instruction.

§Forms

Assembly: vloxei32.v vm, vs2, xs1, vd Rust: vloxei32_v(vd, rs1, vs2, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vloxei64_v<T0, T1, T2, T3, T4>( &mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vloxei64VEmitter<T0, T1, T2, T3, T4>,

RISC-V vloxei64.v instruction.

§Forms

Assembly: vloxei64.v vm, vs2, xs1, vd Rust: vloxei64_v(vd, rs1, vs2, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vloxei8_v<T0, T1, T2, T3, T4>( &mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vloxei8VEmitter<T0, T1, T2, T3, T4>,

RISC-V vloxei8.v instruction.

§Forms

Assembly: vloxei8.v vm, vs2, xs1, vd Rust: vloxei8_v(vd, rs1, vs2, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vlse16_v<T0, T1, T2, T3, T4>( &mut self, vd: T0, rs1: T1, rs2: T2, vm: T3, nf: T4, )
where Self: Vlse16VEmitter<T0, T1, T2, T3, T4>,

RISC-V vlse16.v instruction.

§Forms

Assembly: vlse16.v vm, xs2, xs1, vd Rust: vlse16_v(vd, rs1, rs2, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
rs2 — Source register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vlse32_v<T0, T1, T2, T3, T4>( &mut self, vd: T0, rs1: T1, rs2: T2, vm: T3, nf: T4, )
where Self: Vlse32VEmitter<T0, T1, T2, T3, T4>,

RISC-V vlse32.v instruction.

§Forms

Assembly: vlse32.v vm, xs2, xs1, vd Rust: vlse32_v(vd, rs1, rs2, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
rs2 — Source register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vlse64_v<T0, T1, T2, T3, T4>( &mut self, vd: T0, rs1: T1, rs2: T2, vm: T3, nf: T4, )
where Self: Vlse64VEmitter<T0, T1, T2, T3, T4>,

RISC-V vlse64.v instruction.

§Forms

Assembly: vlse64.v vm, xs2, xs1, vd Rust: vlse64_v(vd, rs1, rs2, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
rs2 — Source register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vlse8_v<T0, T1, T2, T3, T4>( &mut self, vd: T0, rs1: T1, rs2: T2, vm: T3, nf: T4, )
where Self: Vlse8VEmitter<T0, T1, T2, T3, T4>,

RISC-V vlse8.v instruction.

§Forms

Assembly: vlse8.v vm, xs2, xs1, vd Rust: vlse8_v(vd, rs1, rs2, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
rs2 — Source register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vluxei16_v<T0, T1, T2, T3, T4>( &mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vluxei16VEmitter<T0, T1, T2, T3, T4>,

RISC-V vluxei16.v instruction.

§Forms

Assembly: vluxei16.v vm, vs2, xs1, vd Rust: vluxei16_v(vd, rs1, vs2, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vluxei32_v<T0, T1, T2, T3, T4>( &mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vluxei32VEmitter<T0, T1, T2, T3, T4>,

RISC-V vluxei32.v instruction.

§Forms

Assembly: vluxei32.v vm, vs2, xs1, vd Rust: vluxei32_v(vd, rs1, vs2, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vluxei64_v<T0, T1, T2, T3, T4>( &mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vluxei64VEmitter<T0, T1, T2, T3, T4>,

RISC-V vluxei64.v instruction.

§Forms

Assembly: vluxei64.v vm, vs2, xs1, vd Rust: vluxei64_v(vd, rs1, vs2, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vluxei8_v<T0, T1, T2, T3, T4>( &mut self, vd: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vluxei8VEmitter<T0, T1, T2, T3, T4>,

RISC-V vluxei8.v instruction.

§Forms

Assembly: vluxei8.v vm, vs2, xs1, vd Rust: vluxei8_v(vd, rs1, vs2, vm, nf)

§Arguments

vd — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vmacc_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmaccVvEmitter<T0, T1, T2, T3>,

RISC-V vmacc.vv instruction.

§Forms

Assembly: vmacc.vv vm, vs2, vs1, vd Rust: vmacc_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmacc_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmaccVxEmitter<T0, T1, T2, T3>,

RISC-V vmacc.vx instruction.

§Forms

Assembly: vmacc.vx vm, vs2, xs1, vd Rust: vmacc_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmadc_vi<T0, T1, T2>(&mut self, vd: T0, vs2: T1, simm5: T2)
where Self: VmadcViEmitter<T0, T1, T2>,

RISC-V vmadc.vi instruction.

§Forms

Assembly: vmadc.vi vs2, vd, imm Rust: vmadc_vi(vd, vs2, simm5)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.

Source

pub fn vmadc_vim<T0, T1, T2>(&mut self, vd: T0, vs2: T1, simm5: T2)
where Self: VmadcVimEmitter<T0, T1, T2>,

RISC-V vmadc.vim instruction.

§Forms

Assembly: vmadc.vim vs2, vd, imm Rust: vmadc_vim(vd, vs2, simm5)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.

Source

pub fn vmadc_vv<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VmadcVvEmitter<T0, T1, T2>,

RISC-V vmadc.vv instruction.

§Forms

Assembly: vmadc.vv vs2, vs1, vd Rust: vmadc_vv(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmadc_vvm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VmadcVvmEmitter<T0, T1, T2>,

RISC-V vmadc.vvm instruction.

§Forms

Assembly: vmadc.vvm vs2, vs1, vd Rust: vmadc_vvm(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmadc_vx<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
where Self: VmadcVxEmitter<T0, T1, T2>,

RISC-V vmadc.vx instruction.

§Forms

Assembly: vmadc.vx vs2, xs1, vd Rust: vmadc_vx(vd, rs1, vs2)

§Arguments

vd — Vector register operand.
rs1 — Source register.
vs2 — Vector register operand.

Source

pub fn vmadc_vxm<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
where Self: VmadcVxmEmitter<T0, T1, T2>,

RISC-V vmadc.vxm instruction.

§Forms

Assembly: vmadc.vxm vs2, xs1, vd Rust: vmadc_vxm(vd, rs1, vs2)

§Arguments

vd — Vector register operand.
rs1 — Source register.
vs2 — Vector register operand.

Source

pub fn vmadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmaddVvEmitter<T0, T1, T2, T3>,

RISC-V vmadd.vv instruction.

§Forms

Assembly: vmadd.vv vm, vs2, vs1, vd Rust: vmadd_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmadd_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmaddVxEmitter<T0, T1, T2, T3>,

RISC-V vmadd.vx instruction.

§Forms

Assembly: vmadd.vx vm, vs2, xs1, vd Rust: vmadd_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmand_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VmandMmEmitter<T0, T1, T2>,

RISC-V vmand.mm instruction.

§Forms

Assembly: vmand.mm vs2, vs1, vd Rust: vmand_mm(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmandn_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VmandnMmEmitter<T0, T1, T2>,

RISC-V vmandn.mm instruction.

§Forms

Assembly: vmandn.mm vs2, vs1, vd Rust: vmandn_mm(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmandnot_mm<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmandnotMmEmitter<T0, T1, T2, T3>,

RISC-V vmandnot.mm instruction.

§Forms

Assembly: vmandnot.mm vd vs1 vs2 vm Rust: vmandnot_mm(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmax_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmaxVvEmitter<T0, T1, T2, T3>,

RISC-V vmax.vv instruction.

§Forms

Assembly: vmax.vv vm, vs2, vs1, vd Rust: vmax_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmax_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmaxVxEmitter<T0, T1, T2, T3>,

RISC-V vmax.vx instruction.

§Forms

Assembly: vmax.vx vm, vs2, xs1, vd Rust: vmax_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmaxu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmaxuVvEmitter<T0, T1, T2, T3>,

RISC-V vmaxu.vv instruction.

§Forms

Assembly: vmaxu.vv vm, vs2, vs1, vd Rust: vmaxu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmaxu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmaxuVxEmitter<T0, T1, T2, T3>,

RISC-V vmaxu.vx instruction.

§Forms

Assembly: vmaxu.vx vm, vs2, xs1, vd Rust: vmaxu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmerge_vim<T0, T1, T2>(&mut self, vd: T0, vs2: T1, simm5: T2)
where Self: VmergeVimEmitter<T0, T1, T2>,

RISC-V vmerge.vim instruction.

§Forms

Assembly: vmerge.vim vs2, vd, imm Rust: vmerge_vim(vd, vs2, simm5)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.

Source

pub fn vmerge_vvm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VmergeVvmEmitter<T0, T1, T2>,

RISC-V vmerge.vvm instruction.

§Forms

Assembly: vmerge.vvm vs2, vs1, vd Rust: vmerge_vvm(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmerge_vxm<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
where Self: VmergeVxmEmitter<T0, T1, T2>,

RISC-V vmerge.vxm instruction.

§Forms

Assembly: vmerge.vxm vs2, xs1, vd Rust: vmerge_vxm(vd, rs1, vs2)

§Arguments

vd — Vector register operand.
rs1 — Source register.
vs2 — Vector register operand.

Source

pub fn vmfeq_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmfeqVfEmitter<T0, T1, T2, T3>,

RISC-V vmfeq.vf instruction.

§Forms

Assembly: vmfeq.vf vm, vs2, xs1, vd Rust: vmfeq_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmfeq_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmfeqVvEmitter<T0, T1, T2, T3>,

RISC-V vmfeq.vv instruction.

§Forms

Assembly: vmfeq.vv vm, vs2, vs1, vd Rust: vmfeq_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmfge_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmfgeVfEmitter<T0, T1, T2, T3>,

RISC-V vmfge.vf instruction.

§Forms

Assembly: vmfge.vf vm, vs2, xs1, vd Rust: vmfge_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmfgt_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmfgtVfEmitter<T0, T1, T2, T3>,

RISC-V vmfgt.vf instruction.

§Forms

Assembly: vmfgt.vf vm, vs2, xs1, vd Rust: vmfgt_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmfle_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmfleVfEmitter<T0, T1, T2, T3>,

RISC-V vmfle.vf instruction.

§Forms

Assembly: vmfle.vf vm, vs2, xs1, vd Rust: vmfle_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmfle_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmfleVvEmitter<T0, T1, T2, T3>,

RISC-V vmfle.vv instruction.

§Forms

Assembly: vmfle.vv vm, vs2, vs1, vd Rust: vmfle_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmflt_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmfltVfEmitter<T0, T1, T2, T3>,

RISC-V vmflt.vf instruction.

§Forms

Assembly: vmflt.vf vm, vs2, xs1, vd Rust: vmflt_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmflt_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmfltVvEmitter<T0, T1, T2, T3>,

RISC-V vmflt.vv instruction.

§Forms

Assembly: vmflt.vv vm, vs2, vs1, vd Rust: vmflt_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmfne_vf<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmfneVfEmitter<T0, T1, T2, T3>,

RISC-V vmfne.vf instruction.

§Forms

Assembly: vmfne.vf vm, vs2, xs1, vd Rust: vmfne_vf(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmfne_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmfneVvEmitter<T0, T1, T2, T3>,

RISC-V vmfne.vv instruction.

§Forms

Assembly: vmfne.vv vm, vs2, vs1, vd Rust: vmfne_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmin_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VminVvEmitter<T0, T1, T2, T3>,

RISC-V vmin.vv instruction.

§Forms

Assembly: vmin.vv vm, vs2, vs1, vd Rust: vmin_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmin_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VminVxEmitter<T0, T1, T2, T3>,

RISC-V vmin.vx instruction.

§Forms

Assembly: vmin.vx vm, vs2, xs1, vd Rust: vmin_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vminu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VminuVvEmitter<T0, T1, T2, T3>,

RISC-V vminu.vv instruction.

§Forms

Assembly: vminu.vv vm, vs2, vs1, vd Rust: vminu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vminu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VminuVxEmitter<T0, T1, T2, T3>,

RISC-V vminu.vx instruction.

§Forms

Assembly: vminu.vx vm, vs2, xs1, vd Rust: vminu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmnand_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VmnandMmEmitter<T0, T1, T2>,

RISC-V vmnand.mm instruction.

§Forms

Assembly: vmnand.mm vs2, vs1, vd Rust: vmnand_mm(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmnor_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VmnorMmEmitter<T0, T1, T2>,

RISC-V vmnor.mm instruction.

§Forms

Assembly: vmnor.mm vs2, vs1, vd Rust: vmnor_mm(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmor_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VmorMmEmitter<T0, T1, T2>,

RISC-V vmor.mm instruction.

§Forms

Assembly: vmor.mm vs2, vs1, vd Rust: vmor_mm(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmorn_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VmornMmEmitter<T0, T1, T2>,

RISC-V vmorn.mm instruction.

§Forms

Assembly: vmorn.mm vs2, vs1, vd Rust: vmorn_mm(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmornot_mm<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmornotMmEmitter<T0, T1, T2, T3>,

RISC-V vmornot.mm instruction.

§Forms

Assembly: vmornot.mm vd vs1 vs2 vm Rust: vmornot_mm(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmsbc_vv<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VmsbcVvEmitter<T0, T1, T2>,

RISC-V vmsbc.vv instruction.

§Forms

Assembly: vmsbc.vv vs2, vs1, vd Rust: vmsbc_vv(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmsbc_vvm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VmsbcVvmEmitter<T0, T1, T2>,

RISC-V vmsbc.vvm instruction.

§Forms

Assembly: vmsbc.vvm vs2, vs1, vd Rust: vmsbc_vvm(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmsbc_vx<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
where Self: VmsbcVxEmitter<T0, T1, T2>,

RISC-V vmsbc.vx instruction.

§Forms

Assembly: vmsbc.vx vs2, xs1, vd Rust: vmsbc_vx(vd, rs1, vs2)

§Arguments

vd — Vector register operand.
rs1 — Source register.
vs2 — Vector register operand.

Source

pub fn vmsbc_vxm<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
where Self: VmsbcVxmEmitter<T0, T1, T2>,

RISC-V vmsbc.vxm instruction.

§Forms

Assembly: vmsbc.vxm vs2, xs1, vd Rust: vmsbc_vxm(vd, rs1, vs2)

§Arguments

vd — Vector register operand.
rs1 — Source register.
vs2 — Vector register operand.

Source

pub fn vmsbf_m<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VmsbfMEmitter<T0, T1, T2>,

RISC-V vmsbf.m instruction.

§Forms

Assembly: vmsbf.m vm, vs2, vd Rust: vmsbf_m(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmseq_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
where Self: VmseqViEmitter<T0, T1, T2, T3>,

RISC-V vmseq.vi instruction.

§Forms

Assembly: vmseq.vi vm, vs2, vd, imm Rust: vmseq_vi(vd, vs2, simm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vmseq_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmseqVvEmitter<T0, T1, T2, T3>,

RISC-V vmseq.vv instruction.

§Forms

Assembly: vmseq.vv vm, vs2, vs1, vd Rust: vmseq_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmseq_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmseqVxEmitter<T0, T1, T2, T3>,

RISC-V vmseq.vx instruction.

§Forms

Assembly: vmseq.vx vm, vs2, xs1, vd Rust: vmseq_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmsgt_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
where Self: VmsgtViEmitter<T0, T1, T2, T3>,

RISC-V vmsgt.vi instruction.

§Forms

Assembly: vmsgt.vi vm, vs2, vd, imm Rust: vmsgt_vi(vd, vs2, simm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vmsgt_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmsgtVxEmitter<T0, T1, T2, T3>,

RISC-V vmsgt.vx instruction.

§Forms

Assembly: vmsgt.vx vm, vs2, xs1, vd Rust: vmsgt_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmsgtu_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
where Self: VmsgtuViEmitter<T0, T1, T2, T3>,

RISC-V vmsgtu.vi instruction.

§Forms

Assembly: vmsgtu.vi vm, vs2, vd, imm Rust: vmsgtu_vi(vd, vs2, simm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vmsgtu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmsgtuVxEmitter<T0, T1, T2, T3>,

RISC-V vmsgtu.vx instruction.

§Forms

Assembly: vmsgtu.vx vm, vs2, xs1, vd Rust: vmsgtu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmsif_m<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VmsifMEmitter<T0, T1, T2>,

RISC-V vmsif.m instruction.

§Forms

Assembly: vmsif.m vm, vs2, vd Rust: vmsif_m(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmsle_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
where Self: VmsleViEmitter<T0, T1, T2, T3>,

RISC-V vmsle.vi instruction.

§Forms

Assembly: vmsle.vi vm, vs2, vd, imm Rust: vmsle_vi(vd, vs2, simm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vmsle_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmsleVvEmitter<T0, T1, T2, T3>,

RISC-V vmsle.vv instruction.

§Forms

Assembly: vmsle.vv vm, vs2, vs1, vd Rust: vmsle_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmsle_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmsleVxEmitter<T0, T1, T2, T3>,

RISC-V vmsle.vx instruction.

§Forms

Assembly: vmsle.vx vm, vs2, xs1, vd Rust: vmsle_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmsleu_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
where Self: VmsleuViEmitter<T0, T1, T2, T3>,

RISC-V vmsleu.vi instruction.

§Forms

Assembly: vmsleu.vi vm, vs2, vd, imm Rust: vmsleu_vi(vd, vs2, simm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vmsleu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmsleuVvEmitter<T0, T1, T2, T3>,

RISC-V vmsleu.vv instruction.

§Forms

Assembly: vmsleu.vv vm, vs2, vs1, vd Rust: vmsleu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmsleu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmsleuVxEmitter<T0, T1, T2, T3>,

RISC-V vmsleu.vx instruction.

§Forms

Assembly: vmsleu.vx vm, vs2, xs1, vd Rust: vmsleu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmslt_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmsltVvEmitter<T0, T1, T2, T3>,

RISC-V vmslt.vv instruction.

§Forms

Assembly: vmslt.vv vm, vs2, vs1, vd Rust: vmslt_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmslt_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmsltVxEmitter<T0, T1, T2, T3>,

RISC-V vmslt.vx instruction.

§Forms

Assembly: vmslt.vx vm, vs2, xs1, vd Rust: vmslt_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmsltu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmsltuVvEmitter<T0, T1, T2, T3>,

RISC-V vmsltu.vv instruction.

§Forms

Assembly: vmsltu.vv vm, vs2, vs1, vd Rust: vmsltu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmsltu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmsltuVxEmitter<T0, T1, T2, T3>,

RISC-V vmsltu.vx instruction.

§Forms

Assembly: vmsltu.vx vm, vs2, xs1, vd Rust: vmsltu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmsne_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
where Self: VmsneViEmitter<T0, T1, T2, T3>,

RISC-V vmsne.vi instruction.

§Forms

Assembly: vmsne.vi vm, vs2, vd, imm Rust: vmsne_vi(vd, vs2, simm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vmsne_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmsneVvEmitter<T0, T1, T2, T3>,

RISC-V vmsne.vv instruction.

§Forms

Assembly: vmsne.vv vm, vs2, vs1, vd Rust: vmsne_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmsne_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmsneVxEmitter<T0, T1, T2, T3>,

RISC-V vmsne.vx instruction.

§Forms

Assembly: vmsne.vx vm, vs2, xs1, vd Rust: vmsne_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmsof_m<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VmsofMEmitter<T0, T1, T2>,

RISC-V vmsof.m instruction.

§Forms

Assembly: vmsof.m vm, vs2, vd Rust: vmsof_m(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmul_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmulVvEmitter<T0, T1, T2, T3>,

RISC-V vmul.vv instruction.

§Forms

Assembly: vmul.vv vm, vs2, vs1, vd Rust: vmul_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmul_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmulVxEmitter<T0, T1, T2, T3>,

RISC-V vmul.vx instruction.

§Forms

Assembly: vmul.vx vm, vs2, xs1, vd Rust: vmul_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmulh_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmulhVvEmitter<T0, T1, T2, T3>,

RISC-V vmulh.vv instruction.

§Forms

Assembly: vmulh.vv vm, vs2, vs1, vd Rust: vmulh_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmulh_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmulhVxEmitter<T0, T1, T2, T3>,

RISC-V vmulh.vx instruction.

§Forms

Assembly: vmulh.vx vm, vs2, xs1, vd Rust: vmulh_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmulhsu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmulhsuVvEmitter<T0, T1, T2, T3>,

RISC-V vmulhsu.vv instruction.

§Forms

Assembly: vmulhsu.vv vm, vs2, vs1, vd Rust: vmulhsu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmulhsu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmulhsuVxEmitter<T0, T1, T2, T3>,

RISC-V vmulhsu.vx instruction.

§Forms

Assembly: vmulhsu.vx vm, vs2, xs1, vd Rust: vmulhsu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmulhu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VmulhuVvEmitter<T0, T1, T2, T3>,

RISC-V vmulhu.vv instruction.

§Forms

Assembly: vmulhu.vv vm, vs2, vs1, vd Rust: vmulhu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vmulhu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VmulhuVxEmitter<T0, T1, T2, T3>,

RISC-V vmulhu.vx instruction.

§Forms

Assembly: vmulhu.vx vm, vs2, xs1, vd Rust: vmulhu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vmv1r_v<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: Vmv1RVEmitter<T0, T1>,

RISC-V vmv1r.v instruction.

§Forms

Assembly: vmv1r.v vs2, vd Rust: vmv1r_v(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmv2r_v<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: Vmv2RVEmitter<T0, T1>,

RISC-V vmv2r.v instruction.

§Forms

Assembly: vmv2r.v vs2, vd Rust: vmv2r_v(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmv4r_v<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: Vmv4RVEmitter<T0, T1>,

RISC-V vmv4r.v instruction.

§Forms

Assembly: vmv4r.v vs2, vd Rust: vmv4r_v(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmv8r_v<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: Vmv8RVEmitter<T0, T1>,

RISC-V vmv8r.v instruction.

§Forms

Assembly: vmv8r.v vs2, vd Rust: vmv8r_v(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmv_s_x<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: VmvSXEmitter<T0, T1>,

RISC-V vmv.s.x instruction.

§Forms

Assembly: vmv.s.x xs1, vd Rust: vmv_s_x(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Source register.

Source

pub fn vmv_v_i<T0, T1>(&mut self, vd: T0, simm5: T1)
where Self: VmvVIEmitter<T0, T1>,

RISC-V vmv.v.i instruction.

§Forms

Assembly: vmv.v.i vd, imm Rust: vmv_v_i(vd, simm5)

§Arguments

vd — Vector register operand.
simm5 — Immediate encoding value.

Source

pub fn vmv_v_v<T0, T1>(&mut self, vd: T0, vs1: T1)
where Self: VmvVVEmitter<T0, T1>,

RISC-V vmv.v.v instruction.

§Forms

Assembly: vmv.v.v vs1, vd Rust: vmv_v_v(vd, vs1)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.

Source

pub fn vmv_v_x<T0, T1>(&mut self, vd: T0, rs1: T1)
where Self: VmvVXEmitter<T0, T1>,

RISC-V vmv.v.x instruction.

§Forms

Assembly: vmv.v.x xs1, vd Rust: vmv_v_x(vd, rs1)

§Arguments

vd — Vector register operand.
rs1 — Source register.

Source

pub fn vmv_x_s<T0, T1>(&mut self, rd: T0, vs2: T1)
where Self: VmvXSEmitter<T0, T1>,

RISC-V vmv.x.s instruction.

§Forms

Assembly: vmv.x.s vs2, xd Rust: vmv_x_s(rd, vs2)

§Arguments

rd — Destination register.
vs2 — Vector register operand.

Source

pub fn vmxnor_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VmxnorMmEmitter<T0, T1, T2>,

RISC-V vmxnor.mm instruction.

§Forms

Assembly: vmxnor.mm vs2, vs1, vd Rust: vmxnor_mm(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vmxor_mm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VmxorMmEmitter<T0, T1, T2>,

RISC-V vmxor.mm instruction.

§Forms

Assembly: vmxor.mm vs2, vs1, vd Rust: vmxor_mm(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vnclip_wi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
where Self: VnclipWiEmitter<T0, T1, T2, T3>,

RISC-V vnclip.wi instruction.

§Forms

Assembly: vnclip.wi vm, vs2, vd, imm Rust: vnclip_wi(vd, vs2, zimm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vnclip_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VnclipWvEmitter<T0, T1, T2, T3>,

RISC-V vnclip.wv instruction.

§Forms

Assembly: vnclip.wv vm, vs2, vs1, vd Rust: vnclip_wv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vnclip_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VnclipWxEmitter<T0, T1, T2, T3>,

RISC-V vnclip.wx instruction.

§Forms

Assembly: vnclip.wx vm, vs2, xs1, vd Rust: vnclip_wx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vnclipu_wi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
where Self: VnclipuWiEmitter<T0, T1, T2, T3>,

RISC-V vnclipu.wi instruction.

§Forms

Assembly: vnclipu.wi vm, vs2, vd, imm Rust: vnclipu_wi(vd, vs2, zimm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vnclipu_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VnclipuWvEmitter<T0, T1, T2, T3>,

RISC-V vnclipu.wv instruction.

§Forms

Assembly: vnclipu.wv vm, vs2, vs1, vd Rust: vnclipu_wv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vnclipu_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VnclipuWxEmitter<T0, T1, T2, T3>,

RISC-V vnclipu.wx instruction.

§Forms

Assembly: vnclipu.wx vm, vs2, xs1, vd Rust: vnclipu_wx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vnmsac_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VnmsacVvEmitter<T0, T1, T2, T3>,

RISC-V vnmsac.vv instruction.

§Forms

Assembly: vnmsac.vv vm, vs2, vs1, vd Rust: vnmsac_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vnmsac_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VnmsacVxEmitter<T0, T1, T2, T3>,

RISC-V vnmsac.vx instruction.

§Forms

Assembly: vnmsac.vx vm, vs2, xs1, vd Rust: vnmsac_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vnmsub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VnmsubVvEmitter<T0, T1, T2, T3>,

RISC-V vnmsub.vv instruction.

§Forms

Assembly: vnmsub.vv vm, vs2, vs1, vd Rust: vnmsub_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vnmsub_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VnmsubVxEmitter<T0, T1, T2, T3>,

RISC-V vnmsub.vx instruction.

§Forms

Assembly: vnmsub.vx vm, vs2, xs1, vd Rust: vnmsub_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vnsra_wi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
where Self: VnsraWiEmitter<T0, T1, T2, T3>,

RISC-V vnsra.wi instruction.

§Forms

Assembly: vnsra.wi vm, vs2, vd, imm Rust: vnsra_wi(vd, vs2, zimm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vnsra_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VnsraWvEmitter<T0, T1, T2, T3>,

RISC-V vnsra.wv instruction.

§Forms

Assembly: vnsra.wv vm, vs2, vs1, vd Rust: vnsra_wv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vnsra_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VnsraWxEmitter<T0, T1, T2, T3>,

RISC-V vnsra.wx instruction.

§Forms

Assembly: vnsra.wx vm, vs2, xs1, vd Rust: vnsra_wx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vnsrl_wi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
where Self: VnsrlWiEmitter<T0, T1, T2, T3>,

RISC-V vnsrl.wi instruction.

§Forms

Assembly: vnsrl.wi vm, vs2, vd, imm Rust: vnsrl_wi(vd, vs2, zimm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vnsrl_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VnsrlWvEmitter<T0, T1, T2, T3>,

RISC-V vnsrl.wv instruction.

§Forms

Assembly: vnsrl.wv vm, vs2, vs1, vd Rust: vnsrl_wv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vnsrl_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VnsrlWxEmitter<T0, T1, T2, T3>,

RISC-V vnsrl.wx instruction.

§Forms

Assembly: vnsrl.wx vm, vs2, xs1, vd Rust: vnsrl_wx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vor_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
where Self: VorViEmitter<T0, T1, T2, T3>,

RISC-V vor.vi instruction.

§Forms

Assembly: vor.vi vm, vs2, vd, imm Rust: vor_vi(vd, vs2, simm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vor_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VorVvEmitter<T0, T1, T2, T3>,

RISC-V vor.vv instruction.

§Forms

Assembly: vor.vv vm, vs2, vs1, vd Rust: vor_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vor_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VorVxEmitter<T0, T1, T2, T3>,

RISC-V vor.vx instruction.

§Forms

Assembly: vor.vx vm, vs2, xs1, vd Rust: vor_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vpopc_m<T0, T1, T2>(&mut self, rd: T0, vs2: T1, vm: T2)
where Self: VpopcMEmitter<T0, T1, T2>,

RISC-V vpopc.m instruction.

§Forms

Assembly: vpopc.m rd vs2 vm Rust: vpopc_m(rd, vs2, vm)

§Arguments

rd — Destination register.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vredand_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VredandVsEmitter<T0, T1, T2, T3>,

RISC-V vredand.vs instruction.

§Forms

Assembly: vredand.vs vm, vs2, vs1, vd Rust: vredand_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vredmax_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VredmaxVsEmitter<T0, T1, T2, T3>,

RISC-V vredmax.vs instruction.

§Forms

Assembly: vredmax.vs vm, vs2, vs1, vd Rust: vredmax_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vredmaxu_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VredmaxuVsEmitter<T0, T1, T2, T3>,

RISC-V vredmaxu.vs instruction.

§Forms

Assembly: vredmaxu.vs vm, vs2, vs1, vd Rust: vredmaxu_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vredmin_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VredminVsEmitter<T0, T1, T2, T3>,

RISC-V vredmin.vs instruction.

§Forms

Assembly: vredmin.vs vm, vs2, vs1, vd Rust: vredmin_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vredminu_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VredminuVsEmitter<T0, T1, T2, T3>,

RISC-V vredminu.vs instruction.

§Forms

Assembly: vredminu.vs vm, vs2, vs1, vd Rust: vredminu_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vredor_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VredorVsEmitter<T0, T1, T2, T3>,

RISC-V vredor.vs instruction.

§Forms

Assembly: vredor.vs vm, vs2, vs1, vd Rust: vredor_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vredsum_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VredsumVsEmitter<T0, T1, T2, T3>,

RISC-V vredsum.vs instruction.

§Forms

Assembly: vredsum.vs vm, vs2, vs1, vd Rust: vredsum_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vredxor_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VredxorVsEmitter<T0, T1, T2, T3>,

RISC-V vredxor.vs instruction.

§Forms

Assembly: vredxor.vs vm, vs2, vs1, vd Rust: vredxor_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vrem_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VremVvEmitter<T0, T1, T2, T3>,

RISC-V vrem.vv instruction.

§Forms

Assembly: vrem.vv vm, vs2, vs1, vd Rust: vrem_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vrem_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VremVxEmitter<T0, T1, T2, T3>,

RISC-V vrem.vx instruction.

§Forms

Assembly: vrem.vx vm, vs2, xs1, vd Rust: vrem_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vremu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VremuVvEmitter<T0, T1, T2, T3>,

RISC-V vremu.vv instruction.

§Forms

Assembly: vremu.vv vm, vs2, vs1, vd Rust: vremu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vremu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VremuVxEmitter<T0, T1, T2, T3>,

RISC-V vremu.vx instruction.

§Forms

Assembly: vremu.vx vm, vs2, xs1, vd Rust: vremu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vrev8_v<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: Vrev8VEmitter<T0, T1, T2>,

RISC-V vrev8.v instruction.

§Forms

Assembly: vrev8.v vm, vs2, vd Rust: vrev8_v(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vrgather_vi<T0, T1, T2, T3>( &mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3, )
where Self: VrgatherViEmitter<T0, T1, T2, T3>,

RISC-V vrgather.vi instruction.

§Forms

Assembly: vrgather.vi vm, vs2, vd, imm Rust: vrgather_vi(vd, vs2, zimm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vrgather_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VrgatherVvEmitter<T0, T1, T2, T3>,

RISC-V vrgather.vv instruction.

§Forms

Assembly: vrgather.vv vm, vs2, vs1, vd Rust: vrgather_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vrgather_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VrgatherVxEmitter<T0, T1, T2, T3>,

RISC-V vrgather.vx instruction.

§Forms

Assembly: vrgather.vx vm, vs2, xs1, vd Rust: vrgather_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vrgatherei16_vv<T0, T1, T2, T3>( &mut self, vd: T0, vs1: T1, vs2: T2, vm: T3, )
where Self: Vrgatherei16VvEmitter<T0, T1, T2, T3>,

RISC-V vrgatherei16.vv instruction.

§Forms

Assembly: vrgatherei16.vv vm, vs2, vs1, vd Rust: vrgatherei16_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vrol_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VrolVvEmitter<T0, T1, T2, T3>,

RISC-V vrol.vv instruction.

§Forms

Assembly: vrol.vv vm, vs2, vs1, vd Rust: vrol_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vrol_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VrolVxEmitter<T0, T1, T2, T3>,

RISC-V vrol.vx instruction.

§Forms

Assembly: vrol.vx vm, vs2, xs1, vd Rust: vrol_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vror_vi<T0, T1, T2, T3>( &mut self, vd: T0, vs2: T1, zimm6lohi: T2, vm: T3, )
where Self: VrorViEmitter<T0, T1, T2, T3>,

RISC-V vror.vi instruction.

§Forms

Assembly: vror.vi vm, vs2, vd, imm Rust: vror_vi(vd, vs2, zimm6lohi, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm6lohi — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vror_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VrorVvEmitter<T0, T1, T2, T3>,

RISC-V vror.vv instruction.

§Forms

Assembly: vror.vv vm, vs2, vs1, vd Rust: vror_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vror_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VrorVxEmitter<T0, T1, T2, T3>,

RISC-V vror.vx instruction.

§Forms

Assembly: vror.vx vm, vs2, xs1, vd Rust: vror_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vrsub_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
where Self: VrsubViEmitter<T0, T1, T2, T3>,

RISC-V vrsub.vi instruction.

§Forms

Assembly: vrsub.vi vm, vs2, vd, imm Rust: vrsub_vi(vd, vs2, simm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vrsub_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VrsubVxEmitter<T0, T1, T2, T3>,

RISC-V vrsub.vx instruction.

§Forms

Assembly: vrsub.vx vm, vs2, xs1, vd Rust: vrsub_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vs1r_v<T0, T1>(&mut self, vs3: T0, rs1: T1)
where Self: Vs1RVEmitter<T0, T1>,

RISC-V vs1r.v instruction.

§Forms

Assembly: vs1r.v xs1, vs3 Rust: vs1r_v(vs3, rs1)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.

Source

pub fn vs2r_v<T0, T1>(&mut self, vs3: T0, rs1: T1)
where Self: Vs2RVEmitter<T0, T1>,

RISC-V vs2r.v instruction.

§Forms

Assembly: vs2r.v xs1, vs3 Rust: vs2r_v(vs3, rs1)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.

Source

pub fn vs4r_v<T0, T1>(&mut self, vs3: T0, rs1: T1)
where Self: Vs4RVEmitter<T0, T1>,

RISC-V vs4r.v instruction.

§Forms

Assembly: vs4r.v xs1, vs3 Rust: vs4r_v(vs3, rs1)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.

Source

pub fn vs8r_v<T0, T1>(&mut self, vs3: T0, rs1: T1)
where Self: Vs8RVEmitter<T0, T1>,

RISC-V vs8r.v instruction.

§Forms

Assembly: vs8r.v xs1, vs3 Rust: vs8r_v(vs3, rs1)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.

Source

pub fn vsadd_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
where Self: VsaddViEmitter<T0, T1, T2, T3>,

RISC-V vsadd.vi instruction.

§Forms

Assembly: vsadd.vi vm, vs2, vd, imm Rust: vsadd_vi(vd, vs2, simm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vsadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VsaddVvEmitter<T0, T1, T2, T3>,

RISC-V vsadd.vv instruction.

§Forms

Assembly: vsadd.vv vm, vs2, vs1, vd Rust: vsadd_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vsadd_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VsaddVxEmitter<T0, T1, T2, T3>,

RISC-V vsadd.vx instruction.

§Forms

Assembly: vsadd.vx vm, vs2, xs1, vd Rust: vsadd_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vsaddu_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
where Self: VsadduViEmitter<T0, T1, T2, T3>,

RISC-V vsaddu.vi instruction.

§Forms

Assembly: vsaddu.vi vm, vs2, vd, imm Rust: vsaddu_vi(vd, vs2, simm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vsaddu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VsadduVvEmitter<T0, T1, T2, T3>,

RISC-V vsaddu.vv instruction.

§Forms

Assembly: vsaddu.vv vm, vs2, vs1, vd Rust: vsaddu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vsaddu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VsadduVxEmitter<T0, T1, T2, T3>,

RISC-V vsaddu.vx instruction.

§Forms

Assembly: vsaddu.vx vm, vs2, xs1, vd Rust: vsaddu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vsbc_vvm<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: VsbcVvmEmitter<T0, T1, T2>,

RISC-V vsbc.vvm instruction.

§Forms

Assembly: vsbc.vvm vs2, vs1, vd Rust: vsbc_vvm(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vsbc_vxm<T0, T1, T2>(&mut self, vd: T0, rs1: T1, vs2: T2)
where Self: VsbcVxmEmitter<T0, T1, T2>,

RISC-V vsbc.vxm instruction.

§Forms

Assembly: vsbc.vxm vs2, xs1, vd Rust: vsbc_vxm(vd, rs1, vs2)

§Arguments

vd — Vector register operand.
rs1 — Source register.
vs2 — Vector register operand.

Source

pub fn vse16_v<T0, T1, T2, T3>(&mut self, vs3: T0, rs1: T1, vm: T2, nf: T3)
where Self: Vse16VEmitter<T0, T1, T2, T3>,

RISC-V vse16.v instruction.

§Forms

Assembly: vse16.v vm, xs1, vs3 Rust: vse16_v(vs3, rs1, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vse1_v<T0, T1>(&mut self, vs3: T0, rs1: T1)
where Self: Vse1VEmitter<T0, T1>,

RISC-V vse1.v instruction.

§Forms

Assembly: vse1.v vs3 rs1 Rust: vse1_v(vs3, rs1)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.

Source

pub fn vse32_v<T0, T1, T2, T3>(&mut self, vs3: T0, rs1: T1, vm: T2, nf: T3)
where Self: Vse32VEmitter<T0, T1, T2, T3>,

RISC-V vse32.v instruction.

§Forms

Assembly: vse32.v vm, xs1, vs3 Rust: vse32_v(vs3, rs1, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vse64_v<T0, T1, T2, T3>(&mut self, vs3: T0, rs1: T1, vm: T2, nf: T3)
where Self: Vse64VEmitter<T0, T1, T2, T3>,

RISC-V vse64.v instruction.

§Forms

Assembly: vse64.v vm, xs1, vs3 Rust: vse64_v(vs3, rs1, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vse8_v<T0, T1, T2, T3>(&mut self, vs3: T0, rs1: T1, vm: T2, nf: T3)
where Self: Vse8VEmitter<T0, T1, T2, T3>,

RISC-V vse8.v instruction.

§Forms

Assembly: vse8.v vm, xs1, vs3 Rust: vse8_v(vs3, rs1, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vsetivli<T0, T1, T2>(&mut self, rd: T0, zimm5: T1, zimm10: T2)
where Self: VsetivliEmitter<T0, T1, T2>,

RISC-V vsetivli instruction.

§Forms

Assembly: vsetivli xd, imm Rust: vsetivli(rd, zimm5, zimm10)

§Arguments

rd — Destination register.
zimm5 — Immediate encoding value.
zimm10 — Immediate encoding value.

Source

pub fn vsetvl<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: VsetvlEmitter<T0, T1, T2>,

RISC-V vsetvl instruction.

§Forms

Assembly: vsetvl xs2, xs1, xd Rust: vsetvl(rd, rs1, rs2)

§Arguments

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn vsetvli<T0, T1, T2>(&mut self, rd: T0, rs1: T1, zimm11: T2)
where Self: VsetvliEmitter<T0, T1, T2>,

RISC-V vsetvli instruction.

§Forms

Assembly: vsetvli xs1, xd, imm Rust: vsetvli(rd, rs1, zimm11)

§Arguments

rd — Destination register.
rs1 — Source register.
zimm11 — Immediate encoding value.

Source

pub fn vsext_vf2<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VsextVf2Emitter<T0, T1, T2>,

RISC-V vsext.vf2 instruction.

§Forms

Assembly: vsext.vf2 vm, vs2, vd Rust: vsext_vf2(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vsext_vf4<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VsextVf4Emitter<T0, T1, T2>,

RISC-V vsext.vf4 instruction.

§Forms

Assembly: vsext.vf4 vm, vs2, vd Rust: vsext_vf4(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vsext_vf8<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VsextVf8Emitter<T0, T1, T2>,

RISC-V vsext.vf8 instruction.

§Forms

Assembly: vsext.vf8 vm, vs2, vd Rust: vsext_vf8(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vsha2ch_vv<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: Vsha2ChVvEmitter<T0, T1, T2>,

RISC-V vsha2ch.vv instruction.

§Forms

Assembly: vsha2ch.vv vs2, vs1, vd Rust: vsha2ch_vv(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vsha2cl_vv<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: Vsha2ClVvEmitter<T0, T1, T2>,

RISC-V vsha2cl.vv instruction.

§Forms

Assembly: vsha2cl.vv vs2, vs1, vd Rust: vsha2cl_vv(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vsha2ms_vv<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: Vsha2MsVvEmitter<T0, T1, T2>,

RISC-V vsha2ms.vv instruction.

§Forms

Assembly: vsha2ms.vv vs2, vs1, vd Rust: vsha2ms_vv(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vslide1down_vx<T0, T1, T2, T3>( &mut self, vd: T0, vs2: T1, rs1: T2, vm: T3, )
where Self: Vslide1DownVxEmitter<T0, T1, T2, T3>,

RISC-V vslide1down.vx instruction.

§Forms

Assembly: vslide1down.vx vm, vs2, xs1, vd Rust: vslide1down_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vslide1up_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: Vslide1UpVxEmitter<T0, T1, T2, T3>,

RISC-V vslide1up.vx instruction.

§Forms

Assembly: vslide1up.vx vm, vs2, xs1, vd Rust: vslide1up_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vslidedown_vi<T0, T1, T2, T3>( &mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3, )
where Self: VslidedownViEmitter<T0, T1, T2, T3>,

RISC-V vslidedown.vi instruction.

§Forms

Assembly: vslidedown.vi vm, vs2, vd, imm Rust: vslidedown_vi(vd, vs2, zimm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vslidedown_vx<T0, T1, T2, T3>( &mut self, vd: T0, vs2: T1, rs1: T2, vm: T3, )
where Self: VslidedownVxEmitter<T0, T1, T2, T3>,

RISC-V vslidedown.vx instruction.

§Forms

Assembly: vslidedown.vx vm, vs2, xs1, vd Rust: vslidedown_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vslideup_vi<T0, T1, T2, T3>( &mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3, )
where Self: VslideupViEmitter<T0, T1, T2, T3>,

RISC-V vslideup.vi instruction.

§Forms

Assembly: vslideup.vi vm, vs2, vd, imm Rust: vslideup_vi(vd, vs2, zimm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vslideup_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VslideupVxEmitter<T0, T1, T2, T3>,

RISC-V vslideup.vx instruction.

§Forms

Assembly: vslideup.vx vm, vs2, xs1, vd Rust: vslideup_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vsll_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
where Self: VsllViEmitter<T0, T1, T2, T3>,

RISC-V vsll.vi instruction.

§Forms

Assembly: vsll.vi vm, vs2, vd, imm Rust: vsll_vi(vd, vs2, zimm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vsll_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VsllVvEmitter<T0, T1, T2, T3>,

RISC-V vsll.vv instruction.

§Forms

Assembly: vsll.vv vm, vs2, vs1, vd Rust: vsll_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vsll_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VsllVxEmitter<T0, T1, T2, T3>,

RISC-V vsll.vx instruction.

§Forms

Assembly: vsll.vx vm, vs2, xs1, vd Rust: vsll_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vsm3c_vi<T0, T1, T2>(&mut self, vd: T0, vs2: T1, zimm5: T2)
where Self: Vsm3CViEmitter<T0, T1, T2>,

RISC-V vsm3c.vi instruction.

§Forms

Assembly: vsm3c.vi vs2, vd, imm Rust: vsm3c_vi(vd, vs2, zimm5)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.

Source

pub fn vsm3me_vv<T0, T1, T2>(&mut self, vd: T0, vs1: T1, vs2: T2)
where Self: Vsm3MeVvEmitter<T0, T1, T2>,

RISC-V vsm3me.vv instruction.

§Forms

Assembly: vsm3me.vv vs2, vs1, vd Rust: vsm3me_vv(vd, vs1, vs2)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vsm4k_vi<T0, T1, T2>(&mut self, vd: T0, vs2: T1, zimm5: T2)
where Self: Vsm4KViEmitter<T0, T1, T2>,

RISC-V vsm4k.vi instruction.

§Forms

Assembly: vsm4k.vi vs2, vd, imm Rust: vsm4k_vi(vd, vs2, zimm5)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.

Source

pub fn vsm4r_vs<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: Vsm4RVsEmitter<T0, T1>,

RISC-V vsm4r.vs instruction.

§Forms

Assembly: vsm4r.vs vs2, vd Rust: vsm4r_vs(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vsm4r_vv<T0, T1>(&mut self, vd: T0, vs2: T1)
where Self: Vsm4RVvEmitter<T0, T1>,

RISC-V vsm4r.vv instruction.

§Forms

Assembly: vsm4r.vv vs2, vd Rust: vsm4r_vv(vd, vs2)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.

Source

pub fn vsm_v<T0, T1>(&mut self, vs3: T0, rs1: T1)
where Self: VsmVEmitter<T0, T1>,

RISC-V vsm.v instruction.

§Forms

Assembly: vsm.v xs1, vs3 Rust: vsm_v(vs3, rs1)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.

Source

pub fn vsmul_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VsmulVvEmitter<T0, T1, T2, T3>,

RISC-V vsmul.vv instruction.

§Forms

Assembly: vsmul.vv vm, vs2, vs1, vd Rust: vsmul_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vsmul_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VsmulVxEmitter<T0, T1, T2, T3>,

RISC-V vsmul.vx instruction.

§Forms

Assembly: vsmul.vx vm, vs2, xs1, vd Rust: vsmul_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vsoxei16_v<T0, T1, T2, T3, T4>( &mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vsoxei16VEmitter<T0, T1, T2, T3, T4>,

RISC-V vsoxei16.v instruction.

§Forms

Assembly: vsoxei16.v vm, vs2, xs1, vs3 Rust: vsoxei16_v(vs3, rs1, vs2, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vsoxei32_v<T0, T1, T2, T3, T4>( &mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vsoxei32VEmitter<T0, T1, T2, T3, T4>,

RISC-V vsoxei32.v instruction.

§Forms

Assembly: vsoxei32.v vm, vs2, xs1, vs3 Rust: vsoxei32_v(vs3, rs1, vs2, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vsoxei64_v<T0, T1, T2, T3, T4>( &mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vsoxei64VEmitter<T0, T1, T2, T3, T4>,

RISC-V vsoxei64.v instruction.

§Forms

Assembly: vsoxei64.v vm, vs2, xs1, vs3 Rust: vsoxei64_v(vs3, rs1, vs2, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vsoxei8_v<T0, T1, T2, T3, T4>( &mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vsoxei8VEmitter<T0, T1, T2, T3, T4>,

RISC-V vsoxei8.v instruction.

§Forms

Assembly: vsoxei8.v vm, vs2, xs1, vs3 Rust: vsoxei8_v(vs3, rs1, vs2, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vsra_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
where Self: VsraViEmitter<T0, T1, T2, T3>,

RISC-V vsra.vi instruction.

§Forms

Assembly: vsra.vi vm, vs2, vd, imm Rust: vsra_vi(vd, vs2, zimm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vsra_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VsraVvEmitter<T0, T1, T2, T3>,

RISC-V vsra.vv instruction.

§Forms

Assembly: vsra.vv vm, vs2, vs1, vd Rust: vsra_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vsra_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VsraVxEmitter<T0, T1, T2, T3>,

RISC-V vsra.vx instruction.

§Forms

Assembly: vsra.vx vm, vs2, xs1, vd Rust: vsra_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vsrl_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
where Self: VsrlViEmitter<T0, T1, T2, T3>,

RISC-V vsrl.vi instruction.

§Forms

Assembly: vsrl.vi vm, vs2, vd, imm Rust: vsrl_vi(vd, vs2, zimm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vsrl_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VsrlVvEmitter<T0, T1, T2, T3>,

RISC-V vsrl.vv instruction.

§Forms

Assembly: vsrl.vv vm, vs2, vs1, vd Rust: vsrl_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vsrl_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VsrlVxEmitter<T0, T1, T2, T3>,

RISC-V vsrl.vx instruction.

§Forms

Assembly: vsrl.vx vm, vs2, xs1, vd Rust: vsrl_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vsse16_v<T0, T1, T2, T3, T4>( &mut self, vs3: T0, rs1: T1, rs2: T2, vm: T3, nf: T4, )
where Self: Vsse16VEmitter<T0, T1, T2, T3, T4>,

RISC-V vsse16.v instruction.

§Forms

Assembly: vsse16.v vm, xs2, xs1, vs3 Rust: vsse16_v(vs3, rs1, rs2, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
rs2 — Source register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vsse32_v<T0, T1, T2, T3, T4>( &mut self, vs3: T0, rs1: T1, rs2: T2, vm: T3, nf: T4, )
where Self: Vsse32VEmitter<T0, T1, T2, T3, T4>,

RISC-V vsse32.v instruction.

§Forms

Assembly: vsse32.v vm, xs2, xs1, vs3 Rust: vsse32_v(vs3, rs1, rs2, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
rs2 — Source register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vsse64_v<T0, T1, T2, T3, T4>( &mut self, vs3: T0, rs1: T1, rs2: T2, vm: T3, nf: T4, )
where Self: Vsse64VEmitter<T0, T1, T2, T3, T4>,

RISC-V vsse64.v instruction.

§Forms

Assembly: vsse64.v vm, xs2, xs1, vs3 Rust: vsse64_v(vs3, rs1, rs2, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
rs2 — Source register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vsse8_v<T0, T1, T2, T3, T4>( &mut self, vs3: T0, rs1: T1, rs2: T2, vm: T3, nf: T4, )
where Self: Vsse8VEmitter<T0, T1, T2, T3, T4>,

RISC-V vsse8.v instruction.

§Forms

Assembly: vsse8.v vm, xs2, xs1, vs3 Rust: vsse8_v(vs3, rs1, rs2, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
rs2 — Source register.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vssra_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
where Self: VssraViEmitter<T0, T1, T2, T3>,

RISC-V vssra.vi instruction.

§Forms

Assembly: vssra.vi vm, vs2, vd, imm Rust: vssra_vi(vd, vs2, zimm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vssra_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VssraVvEmitter<T0, T1, T2, T3>,

RISC-V vssra.vv instruction.

§Forms

Assembly: vssra.vv vm, vs2, vs1, vd Rust: vssra_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vssra_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VssraVxEmitter<T0, T1, T2, T3>,

RISC-V vssra.vx instruction.

§Forms

Assembly: vssra.vx vm, vs2, xs1, vd Rust: vssra_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vssrl_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
where Self: VssrlViEmitter<T0, T1, T2, T3>,

RISC-V vssrl.vi instruction.

§Forms

Assembly: vssrl.vi vm, vs2, vd, imm Rust: vssrl_vi(vd, vs2, zimm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vssrl_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VssrlVvEmitter<T0, T1, T2, T3>,

RISC-V vssrl.vv instruction.

§Forms

Assembly: vssrl.vv vm, vs2, vs1, vd Rust: vssrl_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vssrl_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VssrlVxEmitter<T0, T1, T2, T3>,

RISC-V vssrl.vx instruction.

§Forms

Assembly: vssrl.vx vm, vs2, xs1, vd Rust: vssrl_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vssub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VssubVvEmitter<T0, T1, T2, T3>,

RISC-V vssub.vv instruction.

§Forms

Assembly: vssub.vv vm, vs2, vs1, vd Rust: vssub_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vssub_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VssubVxEmitter<T0, T1, T2, T3>,

RISC-V vssub.vx instruction.

§Forms

Assembly: vssub.vx vm, vs2, xs1, vd Rust: vssub_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vssubu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VssubuVvEmitter<T0, T1, T2, T3>,

RISC-V vssubu.vv instruction.

§Forms

Assembly: vssubu.vv vm, vs2, vs1, vd Rust: vssubu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vssubu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VssubuVxEmitter<T0, T1, T2, T3>,

RISC-V vssubu.vx instruction.

§Forms

Assembly: vssubu.vx vm, vs2, xs1, vd Rust: vssubu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vsub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VsubVvEmitter<T0, T1, T2, T3>,

RISC-V vsub.vv instruction.

§Forms

Assembly: vsub.vv vm, vs2, vs1, vd Rust: vsub_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vsub_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VsubVxEmitter<T0, T1, T2, T3>,

RISC-V vsub.vx instruction.

§Forms

Assembly: vsub.vx vm, vs2, xs1, vd Rust: vsub_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vsuxei16_v<T0, T1, T2, T3, T4>( &mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vsuxei16VEmitter<T0, T1, T2, T3, T4>,

RISC-V vsuxei16.v instruction.

§Forms

Assembly: vsuxei16.v vm, vs2, xs1, vs3 Rust: vsuxei16_v(vs3, rs1, vs2, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vsuxei32_v<T0, T1, T2, T3, T4>( &mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vsuxei32VEmitter<T0, T1, T2, T3, T4>,

RISC-V vsuxei32.v instruction.

§Forms

Assembly: vsuxei32.v vm, vs2, xs1, vs3 Rust: vsuxei32_v(vs3, rs1, vs2, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vsuxei64_v<T0, T1, T2, T3, T4>( &mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vsuxei64VEmitter<T0, T1, T2, T3, T4>,

RISC-V vsuxei64.v instruction.

§Forms

Assembly: vsuxei64.v vm, vs2, xs1, vs3 Rust: vsuxei64_v(vs3, rs1, vs2, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vsuxei8_v<T0, T1, T2, T3, T4>( &mut self, vs3: T0, rs1: T1, vs2: T2, vm: T3, nf: T4, )
where Self: Vsuxei8VEmitter<T0, T1, T2, T3, T4>,

RISC-V vsuxei8.v instruction.

§Forms

Assembly: vsuxei8.v vm, vs2, xs1, vs3 Rust: vsuxei8_v(vs3, rs1, vs2, vm, nf)

§Arguments

vs3 — Vector register operand.
rs1 — Memory base register.
vs2 — Vector register operand.
vm — Vector mask control.
nf — Vector segment field count.

Source

pub fn vwadd_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwaddVvEmitter<T0, T1, T2, T3>,

RISC-V vwadd.vv instruction.

§Forms

Assembly: vwadd.vv vm, vs2, vs1, vd Rust: vwadd_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwadd_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwaddVxEmitter<T0, T1, T2, T3>,

RISC-V vwadd.vx instruction.

§Forms

Assembly: vwadd.vx vm, vs2, xs1, vd Rust: vwadd_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vwadd_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwaddWvEmitter<T0, T1, T2, T3>,

RISC-V vwadd.wv instruction.

§Forms

Assembly: vwadd.wv vm, vs2, vs1, vd Rust: vwadd_wv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwadd_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwaddWxEmitter<T0, T1, T2, T3>,

RISC-V vwadd.wx instruction.

§Forms

Assembly: vwadd.wx vm, vs2, xs1, vd Rust: vwadd_wx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vwaddu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwadduVvEmitter<T0, T1, T2, T3>,

RISC-V vwaddu.vv instruction.

§Forms

Assembly: vwaddu.vv vm, vs2, vs1, vd Rust: vwaddu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwaddu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwadduVxEmitter<T0, T1, T2, T3>,

RISC-V vwaddu.vx instruction.

§Forms

Assembly: vwaddu.vx vm, vs2, xs1, vd Rust: vwaddu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vwaddu_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwadduWvEmitter<T0, T1, T2, T3>,

RISC-V vwaddu.wv instruction.

§Forms

Assembly: vwaddu.wv vm, vs2, vs1, vd Rust: vwaddu_wv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwaddu_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwadduWxEmitter<T0, T1, T2, T3>,

RISC-V vwaddu.wx instruction.

§Forms

Assembly: vwaddu.wx vm, vs2, xs1, vd Rust: vwaddu_wx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vwmacc_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwmaccVvEmitter<T0, T1, T2, T3>,

RISC-V vwmacc.vv instruction.

§Forms

Assembly: vwmacc.vv vm, vs2, vs1, vd Rust: vwmacc_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwmacc_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwmaccVxEmitter<T0, T1, T2, T3>,

RISC-V vwmacc.vx instruction.

§Forms

Assembly: vwmacc.vx vm, vs2, xs1, vd Rust: vwmacc_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vwmaccsu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwmaccsuVvEmitter<T0, T1, T2, T3>,

RISC-V vwmaccsu.vv instruction.

§Forms

Assembly: vwmaccsu.vv vm, vs2, vs1, vd Rust: vwmaccsu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwmaccsu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwmaccsuVxEmitter<T0, T1, T2, T3>,

RISC-V vwmaccsu.vx instruction.

§Forms

Assembly: vwmaccsu.vx vm, vs2, xs1, vd Rust: vwmaccsu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vwmaccu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwmaccuVvEmitter<T0, T1, T2, T3>,

RISC-V vwmaccu.vv instruction.

§Forms

Assembly: vwmaccu.vv vm, vs2, vs1, vd Rust: vwmaccu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwmaccu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwmaccuVxEmitter<T0, T1, T2, T3>,

RISC-V vwmaccu.vx instruction.

§Forms

Assembly: vwmaccu.vx vm, vs2, xs1, vd Rust: vwmaccu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vwmaccus_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwmaccusVxEmitter<T0, T1, T2, T3>,

RISC-V vwmaccus.vx instruction.

§Forms

Assembly: vwmaccus.vx vm, vs2, xs1, vd Rust: vwmaccus_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vwmul_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwmulVvEmitter<T0, T1, T2, T3>,

RISC-V vwmul.vv instruction.

§Forms

Assembly: vwmul.vv vm, vs2, vs1, vd Rust: vwmul_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwmul_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwmulVxEmitter<T0, T1, T2, T3>,

RISC-V vwmul.vx instruction.

§Forms

Assembly: vwmul.vx vm, vs2, xs1, vd Rust: vwmul_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vwmulsu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwmulsuVvEmitter<T0, T1, T2, T3>,

RISC-V vwmulsu.vv instruction.

§Forms

Assembly: vwmulsu.vv vm, vs2, vs1, vd Rust: vwmulsu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwmulsu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwmulsuVxEmitter<T0, T1, T2, T3>,

RISC-V vwmulsu.vx instruction.

§Forms

Assembly: vwmulsu.vx vm, vs2, xs1, vd Rust: vwmulsu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vwmulu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwmuluVvEmitter<T0, T1, T2, T3>,

RISC-V vwmulu.vv instruction.

§Forms

Assembly: vwmulu.vv vm, vs2, vs1, vd Rust: vwmulu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwmulu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwmuluVxEmitter<T0, T1, T2, T3>,

RISC-V vwmulu.vx instruction.

§Forms

Assembly: vwmulu.vx vm, vs2, xs1, vd Rust: vwmulu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vwredsum_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwredsumVsEmitter<T0, T1, T2, T3>,

RISC-V vwredsum.vs instruction.

§Forms

Assembly: vwredsum.vs vm, vs2, vs1, vd Rust: vwredsum_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwredsumu_vs<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwredsumuVsEmitter<T0, T1, T2, T3>,

RISC-V vwredsumu.vs instruction.

§Forms

Assembly: vwredsumu.vs vm, vs2, vs1, vd Rust: vwredsumu_vs(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwsll_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, zimm5: T2, vm: T3)
where Self: VwsllViEmitter<T0, T1, T2, T3>,

RISC-V vwsll.vi instruction.

§Forms

Assembly: vwsll.vi vm, vs2, vd, imm Rust: vwsll_vi(vd, vs2, zimm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
zimm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vwsll_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwsllVvEmitter<T0, T1, T2, T3>,

RISC-V vwsll.vv instruction.

§Forms

Assembly: vwsll.vv vm, vs2, vs1, vd Rust: vwsll_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwsll_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwsllVxEmitter<T0, T1, T2, T3>,

RISC-V vwsll.vx instruction.

§Forms

Assembly: vwsll.vx vm, vs2, xs1, vd Rust: vwsll_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vwsub_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwsubVvEmitter<T0, T1, T2, T3>,

RISC-V vwsub.vv instruction.

§Forms

Assembly: vwsub.vv vm, vs2, vs1, vd Rust: vwsub_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwsub_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwsubVxEmitter<T0, T1, T2, T3>,

RISC-V vwsub.vx instruction.

§Forms

Assembly: vwsub.vx vm, vs2, xs1, vd Rust: vwsub_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vwsub_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwsubWvEmitter<T0, T1, T2, T3>,

RISC-V vwsub.wv instruction.

§Forms

Assembly: vwsub.wv vm, vs2, vs1, vd Rust: vwsub_wv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwsub_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwsubWxEmitter<T0, T1, T2, T3>,

RISC-V vwsub.wx instruction.

§Forms

Assembly: vwsub.wx vm, vs2, xs1, vd Rust: vwsub_wx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vwsubu_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwsubuVvEmitter<T0, T1, T2, T3>,

RISC-V vwsubu.vv instruction.

§Forms

Assembly: vwsubu.vv vm, vs2, vs1, vd Rust: vwsubu_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwsubu_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwsubuVxEmitter<T0, T1, T2, T3>,

RISC-V vwsubu.vx instruction.

§Forms

Assembly: vwsubu.vx vm, vs2, xs1, vd Rust: vwsubu_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vwsubu_wv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VwsubuWvEmitter<T0, T1, T2, T3>,

RISC-V vwsubu.wv instruction.

§Forms

Assembly: vwsubu.wv vm, vs2, vs1, vd Rust: vwsubu_wv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vwsubu_wx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VwsubuWxEmitter<T0, T1, T2, T3>,

RISC-V vwsubu.wx instruction.

§Forms

Assembly: vwsubu.wx vm, vs2, xs1, vd Rust: vwsubu_wx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vxor_vi<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, simm5: T2, vm: T3)
where Self: VxorViEmitter<T0, T1, T2, T3>,

RISC-V vxor.vi instruction.

§Forms

Assembly: vxor.vi vm, vs2, vd, imm Rust: vxor_vi(vd, vs2, simm5, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
simm5 — Immediate encoding value.
vm — Vector mask control.

Source

pub fn vxor_vv<T0, T1, T2, T3>(&mut self, vd: T0, vs1: T1, vs2: T2, vm: T3)
where Self: VxorVvEmitter<T0, T1, T2, T3>,

RISC-V vxor.vv instruction.

§Forms

Assembly: vxor.vv vm, vs2, vs1, vd Rust: vxor_vv(vd, vs1, vs2, vm)

§Arguments

vd — Vector register operand.
vs1 — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vxor_vx<T0, T1, T2, T3>(&mut self, vd: T0, vs2: T1, rs1: T2, vm: T3)
where Self: VxorVxEmitter<T0, T1, T2, T3>,

RISC-V vxor.vx instruction.

§Forms

Assembly: vxor.vx vm, vs2, xs1, vd Rust: vxor_vx(vd, vs2, rs1, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
rs1 — Source register.
vm — Vector mask control.

Source

pub fn vzext_vf2<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VzextVf2Emitter<T0, T1, T2>,

RISC-V vzext.vf2 instruction.

§Forms

Assembly: vzext.vf2 vm, vs2, vd Rust: vzext_vf2(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vzext_vf4<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VzextVf4Emitter<T0, T1, T2>,

RISC-V vzext.vf4 instruction.

§Forms

Assembly: vzext.vf4 vm, vs2, vd Rust: vzext_vf4(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn vzext_vf8<T0, T1, T2>(&mut self, vd: T0, vs2: T1, vm: T2)
where Self: VzextVf8Emitter<T0, T1, T2>,

RISC-V vzext.vf8 instruction.

§Forms

Assembly: vzext.vf8 vm, vs2, vd Rust: vzext_vf8(vd, vs2, vm)

§Arguments

vd — Vector register operand.
vs2 — Vector register operand.
vm — Vector mask control.

Source

pub fn wfi(&mut self)
where Self: WfiEmitter,

Wait for interrupt

Can causes the processor to enter a low-power state until the next interrupt occurs.

<%- if ext?(:H) -%> The behavior of wfi is affected by the mstatus.TW and hstatus.VTW bits, as summarized below.

6+| Trap (I) - Trap with Illegal Instruction code + Trap (V) - Trap with Virtual Instruction code |===

<%- else -%> The wfi instruction is also affected by mstatus.TW, as shown below:

rd — Destination register.
rs1 — Source register.
rs2 — Source register.

Source

pub fn zext_b<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: ZextBEmitter<T0, T1>,

RISC-V zext.b instruction.

§Forms

Assembly: zext.b rd rs1 Rust: zext_b(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn zext_h<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: ZextHEmitter<T0, T1>,

Zero-extend halfword

This instruction zero-extends the least-significant halfword of the source to XLEN by inserting 0’s into all of the bits more significant than 15.

[NOTE] The zext.h instruction is a pseudo-op for pack when Zbkb is implemented and XLEN == 32.

[NOTE] The zext.h instruction is a pseudo-op for packw when Zbkb is implemented and XLEN == 64.

§Forms

Assembly: zext.h xd, xs1 Rust: zext_h(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn zext_h_rv32<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: ZextHRv32Emitter<T0, T1>,

Zero-extend halfword

This instruction zero-extends the least-significant halfword of the source to XLEN by inserting 0’s into all of the bits more significant than 15.

[NOTE] The zext.h instruction is a pseudo-op for pack when Zbkb is implemented and XLEN == 32.

[NOTE] The zext.h instruction is a pseudo-op for packw when Zbkb is implemented and XLEN == 64.

§Forms

Assembly: zext.h.rv32 xd, xs1 Rust: zext_h_rv32(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn zext_w<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: ZextWEmitter<T0, T1>,

RISC-V zext.w instruction.

§Forms

Assembly: zext.w rd rs1 Rust: zext_w(rd, rs1)

§Arguments

rd — Destination register.
rs1 — Source register.

Source

pub fn zip<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: ZipEmitter<T0, T1>,

Bit interleave

fn emit_inst(&mut self, inst: &Inst) -> Result<(), AsmError>

Emits one recorded instruction.

Source §

fn bind_label(&mut self, label: Label) -> Result<(), AsmError>

Binds a label at the current position.

fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>

Performs the conversion.

Source §

impl<T, U> TryInto for T
where U: TryFrom<T>,

Source §

type Error = >::Error

The type returned in the event of a conversion error.

Source §

fn try_into(self) -> Result<U, >::Error>

Performs the conversion.

Struct Assembler Copy item path

Implementations§

impl<'a> Assembler<'a>

pub fn new(buffer: &'a mut CodeBuffer) -> Self

pub fn try_new(buffer: &'a mut CodeBuffer) -> Result<Self, AsmError>

pub fn environment(&self) -> &Environment

pub fn is_32bit(&self) -> bool

pub fn is_64bit(&self) -> bool

pub fn get_label(&mut self) -> Label

pub fn bind_label(&mut self, label: Label)

pub fn try_bind_label(&mut self, label: Label) -> Result<(), AsmError>

pub fn add_constant(&mut self, c: impl Into<ConstantData>) -> Label

pub fn label_offset(&self, label: Label) -> CodeOffset

pub fn data(&self) -> &[u8]

pub fn error(&self) -> Option<&AsmError>

pub fn reserve_patch_block( &mut self, size: CodeOffset, align: CodeOffset, ) -> Result<PatchableBlock, AsmError>

pub fn patchable_j(&mut self, label: Label) -> PatchableSite

pub fn patchable_call(&mut self, label: Label) -> PatchableSite

pub fn patchable_li(&mut self, rd: Gp, imm: impl Into<i64>) -> PatchableBlock

pub fn la(&mut self, rd: Gp, target: impl OperandCast)

pub fn call(&mut self, target: impl OperandCast)

impl<'a> Assembler<'a>

pub fn emit_n(&mut self, opcode: i64, ops: &[&Operand])

pub fn try_emit_n( &mut self, opcode: i64, ops: &[&Operand], ) -> Result<(), AsmError>

impl Assembler<'_>

pub fn add<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)where Self: AddEmitter<T0, T1, T2>,

§Forms

§Arguments

pub fn add_uw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)where Self: AddUwEmitter<T0, T1, T2>,

§Forms

§Arguments

pub fn addi<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)where Self: AddiEmitter<T0, T1, T2>,

§Forms

§Arguments

pub fn addiw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)where Self: AddiwEmitter<T0, T1, T2>,

§Forms

§Arguments

pub fn addw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)where Self: AddwEmitter<T0, T1, T2>,

§Forms

§Arguments

pub fn aes32dsi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)where Self: Aes32DsiEmitter<T0, T1, T2, T3>,

§Forms

§Arguments

pub fn aes32dsmi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)where Self: Aes32DsmiEmitter<T0, T1, T2, T3>,

§Forms

§Arguments

pub fn aes32esi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)where Self: Aes32EsiEmitter<T0, T1, T2, T3>,

§Forms

§Arguments

pub fn aes32esmi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)where Self: Aes32EsmiEmitter<T0, T1, T2, T3>,

§Forms

§Arguments

pub fn aes64ds<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)where Self: Aes64DsEmitter<T0, T1, T2>,

§Forms

§Arguments

pub fn aes64dsm<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)where Self: Aes64DsmEmitter<T0, T1, T2>,

§Forms

§Arguments

pub fn aes64es<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)where Self: Aes64EsEmitter<T0, T1, T2>,

§Forms

§Arguments

pub fn aes64esm<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)where Self: Aes64EsmEmitter<T0, T1, T2>,

§Forms

§Arguments

pub fn aes64im<T0, T1>(&mut self, rd: T0, rs1: T1)where Self: Aes64ImEmitter<T0, T1>,

§Forms

§Arguments

pub fn aes64ks1i<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rnum: T2)where Self: Aes64Ks1IEmitter<T0, T1, T2>,

§Forms

§Arguments

pub fn aes64ks2<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)where Self: Aes64Ks2Emitter<T0, T1, T2>,

§Forms

§Arguments

pub fn amoadd_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )where Self: AmoaddBEmitter<T0, T1, T2, T3, T4>,

§Forms

§Arguments

pub fn amoadd_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )where Self: AmoaddDEmitter<T0, T1, T2, T3, T4>,

§Forms

§Arguments

pub fn amoadd_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )where Self: AmoaddHEmitter<T0, T1, T2, T3, T4>,

Struct Assembler

pub fn add<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: AddEmitter<T0, T1, T2>,

pub fn add_uw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: AddUwEmitter<T0, T1, T2>,

pub fn addi<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: AddiEmitter<T0, T1, T2>,

pub fn addiw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, imm: T2)
where Self: AddiwEmitter<T0, T1, T2>,

pub fn addw<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: AddwEmitter<T0, T1, T2>,

pub fn aes32dsi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
where Self: Aes32DsiEmitter<T0, T1, T2, T3>,

pub fn aes32dsmi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
where Self: Aes32DsmiEmitter<T0, T1, T2, T3>,

pub fn aes32esi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
where Self: Aes32EsiEmitter<T0, T1, T2, T3>,

pub fn aes32esmi<T0, T1, T2, T3>(&mut self, rd: T0, rs1: T1, rs2: T2, bs: T3)
where Self: Aes32EsmiEmitter<T0, T1, T2, T3>,

pub fn aes64ds<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Aes64DsEmitter<T0, T1, T2>,

pub fn aes64dsm<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Aes64DsmEmitter<T0, T1, T2>,

pub fn aes64es<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Aes64EsEmitter<T0, T1, T2>,

pub fn aes64esm<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Aes64EsmEmitter<T0, T1, T2>,

pub fn aes64im<T0, T1>(&mut self, rd: T0, rs1: T1)
where Self: Aes64ImEmitter<T0, T1>,

pub fn aes64ks1i<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rnum: T2)
where Self: Aes64Ks1IEmitter<T0, T1, T2>,

pub fn aes64ks2<T0, T1, T2>(&mut self, rd: T0, rs1: T1, rs2: T2)
where Self: Aes64Ks2Emitter<T0, T1, T2>,

pub fn amoadd_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoaddBEmitter<T0, T1, T2, T3, T4>,

pub fn amoadd_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoaddDEmitter<T0, T1, T2, T3, T4>,

pub fn amoadd_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoaddHEmitter<T0, T1, T2, T3, T4>,

pub fn amoadd_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoaddWEmitter<T0, T1, T2, T3, T4>,

pub fn amoand_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoandBEmitter<T0, T1, T2, T3, T4>,

pub fn amoand_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoandDEmitter<T0, T1, T2, T3, T4>,

pub fn amoand_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoandHEmitter<T0, T1, T2, T3, T4>,

pub fn amoand_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmoandWEmitter<T0, T1, T2, T3, T4>,

pub fn amocas_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmocasBEmitter<T0, T1, T2, T3, T4>,

pub fn amocas_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmocasDEmitter<T0, T1, T2, T3, T4>,

pub fn amocas_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmocasHEmitter<T0, T1, T2, T3, T4>,

pub fn amocas_q<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmocasQEmitter<T0, T1, T2, T3, T4>,

pub fn amocas_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmocasWEmitter<T0, T1, T2, T3, T4>,

pub fn amomax_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxBEmitter<T0, T1, T2, T3, T4>,

pub fn amomax_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxDEmitter<T0, T1, T2, T3, T4>,

pub fn amomax_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxHEmitter<T0, T1, T2, T3, T4>,

pub fn amomax_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxWEmitter<T0, T1, T2, T3, T4>,

pub fn amomaxu_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxuBEmitter<T0, T1, T2, T3, T4>,

pub fn amomaxu_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxuDEmitter<T0, T1, T2, T3, T4>,

pub fn amomaxu_h<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxuHEmitter<T0, T1, T2, T3, T4>,

pub fn amomaxu_w<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmomaxuWEmitter<T0, T1, T2, T3, T4>,

pub fn amomin_b<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmominBEmitter<T0, T1, T2, T3, T4>,

pub fn amomin_d<T0, T1, T2, T3, T4>( &mut self, rd: T0, rs1: T1, rs2: T2, aq: T3, rl: T4, )
where Self: AmominDEmitter<T0, T1, T2, T3, T4>,