Enum Opcode

Source

#[repr(u32)]pub enum Opcode {
Show 1040 variants    ADD = 0,
    ADDUW = 1,
    ADDI = 2,
    ADDIW = 3,
    ADDW = 4,
    AES32DSI = 5,
    AES32DSMI = 6,
    AES32ESI = 7,
    AES32ESMI = 8,
    AES64DS = 9,
    AES64DSM = 10,
    AES64ES = 11,
    AES64ESM = 12,
    AES64IM = 13,
    AES64KS1I = 14,
    AES64KS2 = 15,
    AMOADDB = 16,
    AMOADDD = 17,
    AMOADDH = 18,
    AMOADDW = 19,
    AMOANDB = 20,
    AMOANDD = 21,
    AMOANDH = 22,
    AMOANDW = 23,
    AMOCASB = 24,
    AMOCASD = 25,
    AMOCASH = 26,
    AMOCASQ = 27,
    AMOCASW = 28,
    AMOMAXB = 29,
    AMOMAXD = 30,
    AMOMAXH = 31,
    AMOMAXW = 32,
    AMOMAXUB = 33,
    AMOMAXUD = 34,
    AMOMAXUH = 35,
    AMOMAXUW = 36,
    AMOMINB = 37,
    AMOMIND = 38,
    AMOMINH = 39,
    AMOMINW = 40,
    AMOMINUB = 41,
    AMOMINUD = 42,
    AMOMINUH = 43,
    AMOMINUW = 44,
    AMOORB = 45,
    AMOORD = 46,
    AMOORH = 47,
    AMOORW = 48,
    AMOSWAPB = 49,
    AMOSWAPD = 50,
    AMOSWAPH = 51,
    AMOSWAPW = 52,
    AMOXORB = 53,
    AMOXORD = 54,
    AMOXORH = 55,
    AMOXORW = 56,
    AND = 57,
    ANDI = 58,
    ANDN = 59,
    AUIPC = 60,
    BCLR = 61,
    BCLRI = 62,
    BCLRIRV32 = 63,
    BEQ = 64,
    BEQZ = 65,
    BEXT = 66,
    BEXTI = 67,
    BEXTIRV32 = 68,
    BGE = 69,
    BGEU = 70,
    BGEZ = 71,
    BGT = 72,
    BGTU = 73,
    BGTZ = 74,
    BINV = 75,
    BINVI = 76,
    BINVIRV32 = 77,
    BLE = 78,
    BLEU = 79,
    BLEZ = 80,
    BLT = 81,
    BLTU = 82,
    BLTZ = 83,
    BNE = 84,
    BNEZ = 85,
    BREV8 = 86,
    BSET = 87,
    BSETI = 88,
    BSETIRV32 = 89,
    CADD = 90,
    CADDI = 91,
    CADDI16SP = 92,
    CADDI4SPN = 93,
    CADDIW = 94,
    CADDW = 95,
    CAND = 96,
    CANDI = 97,
    CBEQZ = 98,
    CBNEZ = 99,
    CEBREAK = 100,
    CFLD = 101,
    CFLDSP = 102,
    CFLW = 103,
    CFLWSP = 104,
    CFSD = 105,
    CFSDSP = 106,
    CFSW = 107,
    CFSWSP = 108,
    CJ = 109,
    CJAL = 110,
    CJALR = 111,
    CJR = 112,
    CLBU = 113,
    CLD = 114,
    CLDSP = 115,
    CLH = 116,
    CLHU = 117,
    CLI = 118,
    CLUI = 119,
    CLW = 120,
    CLWSP = 121,
    CMOP1 = 122,
    CMOP11 = 123,
    CMOP13 = 124,
    CMOP15 = 125,
    CMOP3 = 126,
    CMOP5 = 127,
    CMOP7 = 128,
    CMOP9 = 129,
    CMOPN = 130,
    CMUL = 131,
    CMV = 132,
    CNOP = 133,
    CNOT = 134,
    CNTLALL = 135,
    CNTLP1 = 136,
    CNTLPALL = 137,
    CNTLS1 = 138,
    COR = 139,
    CSB = 140,
    CSD = 141,
    CSDSP = 142,
    CSEXTB = 143,
    CSEXTH = 144,
    CSEXTW = 145,
    CSH = 146,
    CSLLI = 147,
    CSLLIRV32 = 148,
    CSRAI = 149,
    CSRAIRV32 = 150,
    CSRLI = 151,
    CSRLIRV32 = 152,
    CSSPOPCHKX5 = 153,
    CSSPUSHX1 = 154,
    CSUB = 155,
    CSUBW = 156,
    CSW = 157,
    CSWSP = 158,
    CXOR = 159,
    CZEXTB = 160,
    CZEXTH = 161,
    CZEXTW = 162,
    CBOCLEAN = 163,
    CBOFLUSH = 164,
    CBOINVAL = 165,
    CBOZERO = 166,
    CLMUL = 167,
    CLMULH = 168,
    CLMULR = 169,
    CLZ = 170,
    CLZW = 171,
    CMJALT = 172,
    CMMVA01S = 173,
    CMMVSA01 = 174,
    CMPOP = 175,
    CMPOPRET = 176,
    CMPOPRETZ = 177,
    CMPUSH = 178,
    CPOP = 179,
    CPOPW = 180,
    CSRC = 181,
    CSRCI = 182,
    CSRR = 183,
    CSRRC = 184,
    CSRRCI = 185,
    CSRRS = 186,
    CSRRSI = 187,
    CSRRW = 188,
    CSRRWI = 189,
    CSRS = 190,
    CSRSI = 191,
    CSRW = 192,
    CSRWI = 193,
    CTZ = 194,
    CTZW = 195,
    CZEROEQZ = 196,
    CZERONEZ = 197,
    DIV = 198,
    DIVU = 199,
    DIVUW = 200,
    DIVW = 201,
    DRET = 202,
    EBREAK = 203,
    ECALL = 204,
    FABSD = 205,
    FABSH = 206,
    FABSQ = 207,
    FABSS = 208,
    FADDD = 209,
    FADDH = 210,
    FADDQ = 211,
    FADDS = 212,
    FCLASSD = 213,
    FCLASSH = 214,
    FCLASSQ = 215,
    FCLASSS = 216,
    FCVTBF16S = 217,
    FCVTDH = 218,
    FCVTDL = 219,
    FCVTDLU = 220,
    FCVTDQ = 221,
    FCVTDS = 222,
    FCVTDW = 223,
    FCVTDWU = 224,
    FCVTHD = 225,
    FCVTHL = 226,
    FCVTHLU = 227,
    FCVTHQ = 228,
    FCVTHS = 229,
    FCVTHW = 230,
    FCVTHWU = 231,
    FCVTLD = 232,
    FCVTLH = 233,
    FCVTLQ = 234,
    FCVTLS = 235,
    FCVTLUD = 236,
    FCVTLUH = 237,
    FCVTLUQ = 238,
    FCVTLUS = 239,
    FCVTQD = 240,
    FCVTQH = 241,
    FCVTQL = 242,
    FCVTQLU = 243,
    FCVTQS = 244,
    FCVTQW = 245,
    FCVTQWU = 246,
    FCVTSBF16 = 247,
    FCVTSD = 248,
    FCVTSH = 249,
    FCVTSL = 250,
    FCVTSLU = 251,
    FCVTSQ = 252,
    FCVTSW = 253,
    FCVTSWU = 254,
    FCVTWD = 255,
    FCVTWH = 256,
    FCVTWQ = 257,
    FCVTWS = 258,
    FCVTWUD = 259,
    FCVTWUH = 260,
    FCVTWUQ = 261,
    FCVTWUS = 262,
    FCVTMODWD = 263,
    FDIVD = 264,
    FDIVH = 265,
    FDIVQ = 266,
    FDIVS = 267,
    FENCE = 268,
    FENCEI = 269,
    FENCETSO = 270,
    FEQD = 271,
    FEQH = 272,
    FEQQ = 273,
    FEQS = 274,
    FLD = 275,
    FLED = 276,
    FLEH = 277,
    FLEQ = 278,
    FLES = 279,
    FLEQD = 280,
    FLEQH = 281,
    FLEQQ = 282,
    FLEQS = 283,
    FLH = 284,
    FLID = 285,
    FLIH = 286,
    FLIQ = 287,
    FLIS = 288,
    FLQ = 289,
    FLTD = 290,
    FLTH = 291,
    FLTQ = 292,
    FLTS = 293,
    FLTQD = 294,
    FLTQH = 295,
    FLTQQ = 296,
    FLTQS = 297,
    FLW = 298,
    FMADDD = 299,
    FMADDH = 300,
    FMADDQ = 301,
    FMADDS = 302,
    FMAXD = 303,
    FMAXH = 304,
    FMAXQ = 305,
    FMAXS = 306,
    FMAXMD = 307,
    FMAXMH = 308,
    FMAXMQ = 309,
    FMAXMS = 310,
    FMIND = 311,
    FMINH = 312,
    FMINQ = 313,
    FMINS = 314,
    FMINMD = 315,
    FMINMH = 316,
    FMINMQ = 317,
    FMINMS = 318,
    FMSUBD = 319,
    FMSUBH = 320,
    FMSUBQ = 321,
    FMSUBS = 322,
    FMULD = 323,
    FMULH = 324,
    FMULQ = 325,
    FMULS = 326,
    FMVD = 327,
    FMVDX = 328,
    FMVH = 329,
    FMVHX = 330,
    FMVQ = 331,
    FMVS = 332,
    FMVSX = 333,
    FMVWX = 334,
    FMVXD = 335,
    FMVXH = 336,
    FMVXS = 337,
    FMVXW = 338,
    FMVHXD = 339,
    FMVHXQ = 340,
    FMVPDX = 341,
    FMVPQX = 342,
    FNEGD = 343,
    FNEGH = 344,
    FNEGQ = 345,
    FNEGS = 346,
    FNMADDD = 347,
    FNMADDH = 348,
    FNMADDQ = 349,
    FNMADDS = 350,
    FNMSUBD = 351,
    FNMSUBH = 352,
    FNMSUBQ = 353,
    FNMSUBS = 354,
    FRCSR = 355,
    FRFLAGS = 356,
    FROUNDD = 357,
    FROUNDH = 358,
    FROUNDQ = 359,
    FROUNDS = 360,
    FROUNDNXD = 361,
    FROUNDNXH = 362,
    FROUNDNXQ = 363,
    FROUNDNXS = 364,
    FRRM = 365,
    FSCSR = 366,
    FSD = 367,
    FSFLAGS = 368,
    FSFLAGSI = 369,
    FSGNJD = 370,
    FSGNJH = 371,
    FSGNJQ = 372,
    FSGNJS = 373,
    FSGNJND = 374,
    FSGNJNH = 375,
    FSGNJNQ = 376,
    FSGNJNS = 377,
    FSGNJXD = 378,
    FSGNJXH = 379,
    FSGNJXQ = 380,
    FSGNJXS = 381,
    FSH = 382,
    FSQ = 383,
    FSQRTD = 384,
    FSQRTH = 385,
    FSQRTQ = 386,
    FSQRTS = 387,
    FSRM = 388,
    FSRMI = 389,
    FSUBD = 390,
    FSUBH = 391,
    FSUBQ = 392,
    FSUBS = 393,
    FSW = 394,
    HFENCEGVMA = 395,
    HFENCEVVMA = 396,
    HINVALGVMA = 397,
    HINVALVVMA = 398,
    HLVB = 399,
    HLVBU = 400,
    HLVD = 401,
    HLVH = 402,
    HLVHU = 403,
    HLVW = 404,
    HLVWU = 405,
    HLVXHU = 406,
    HLVXWU = 407,
    HSVB = 408,
    HSVD = 409,
    HSVH = 410,
    HSVW = 411,
    J = 412,
    JAL = 413,
    JALPSEUDO = 414,
    JALR = 415,
    JALRPSEUDO = 416,
    JR = 417,
    LB = 418,
    LBU = 419,
    LD = 420,
    LH = 421,
    LHU = 422,
    LPAD = 423,
    LRD = 424,
    LRW = 425,
    LUI = 426,
    LW = 427,
    LWU = 428,
    MAX = 429,
    MAXU = 430,
    MIN = 431,
    MINU = 432,
    MNRET = 433,
    MOPR0 = 434,
    MOPR1 = 435,
    MOPR10 = 436,
    MOPR11 = 437,
    MOPR12 = 438,
    MOPR13 = 439,
    MOPR14 = 440,
    MOPR15 = 441,
    MOPR16 = 442,
    MOPR17 = 443,
    MOPR18 = 444,
    MOPR19 = 445,
    MOPR2 = 446,
    MOPR20 = 447,
    MOPR21 = 448,
    MOPR22 = 449,
    MOPR23 = 450,
    MOPR24 = 451,
    MOPR25 = 452,
    MOPR26 = 453,
    MOPR27 = 454,
    MOPR28 = 455,
    MOPR29 = 456,
    MOPR3 = 457,
    MOPR30 = 458,
    MOPR31 = 459,
    MOPR4 = 460,
    MOPR5 = 461,
    MOPR6 = 462,
    MOPR7 = 463,
    MOPR8 = 464,
    MOPR9 = 465,
    MOPRN = 466,
    MOPRR0 = 467,
    MOPRR1 = 468,
    MOPRR2 = 469,
    MOPRR3 = 470,
    MOPRR4 = 471,
    MOPRR5 = 472,
    MOPRR6 = 473,
    MOPRR7 = 474,
    MOPRRN = 475,
    MRET = 476,
    MUL = 477,
    MULH = 478,
    MULHSU = 479,
    MULHU = 480,
    MULW = 481,
    MV = 482,
    NEG = 483,
    NOP = 484,
    NTLALL = 485,
    NTLP1 = 486,
    NTLPALL = 487,
    NTLS1 = 488,
    OR = 489,
    ORCB = 490,
    ORI = 491,
    ORN = 492,
    PACK = 493,
    PACKH = 494,
    PACKW = 495,
    PAUSE = 496,
    PREFETCHI = 497,
    PREFETCHR = 498,
    PREFETCHW = 499,
    RDCYCLE = 500,
    RDCYCLEH = 501,
    RDINSTRET = 502,
    RDINSTRETH = 503,
    RDTIME = 504,
    RDTIMEH = 505,
    REM = 506,
    REMU = 507,
    REMUW = 508,
    REMW = 509,
    RET = 510,
    REV8 = 511,
    REV8RV32 = 512,
    ROL = 513,
    ROLW = 514,
    ROR = 515,
    RORI = 516,
    RORIRV32 = 517,
    RORIW = 518,
    RORW = 519,
    SB = 520,
    SBREAK = 521,
    SCD = 522,
    SCW = 523,
    SCALL = 524,
    SCTRCLR = 525,
    SD = 526,
    SEQZ = 527,
    SEXTB = 528,
    SEXTH = 529,
    SEXTW = 530,
    SFENCEINVALIR = 531,
    SFENCEVMA = 532,
    SFENCEWINVAL = 533,
    SGTZ = 534,
    SH = 535,
    SH1ADD = 536,
    SH1ADDUW = 537,
    SH2ADD = 538,
    SH2ADDUW = 539,
    SH3ADD = 540,
    SH3ADDUW = 541,
    SHA256SIG0 = 542,
    SHA256SIG1 = 543,
    SHA256SUM0 = 544,
    SHA256SUM1 = 545,
    SHA512SIG0 = 546,
    SHA512SIG0H = 547,
    SHA512SIG0L = 548,
    SHA512SIG1 = 549,
    SHA512SIG1H = 550,
    SHA512SIG1L = 551,
    SHA512SUM0 = 552,
    SHA512SUM0R = 553,
    SHA512SUM1 = 554,
    SHA512SUM1R = 555,
    SINVALVMA = 556,
    SLL = 557,
    SLLI = 558,
    SLLIRV32 = 559,
    SLLIUW = 560,
    SLLIW = 561,
    SLLW = 562,
    SLT = 563,
    SLTI = 564,
    SLTIU = 565,
    SLTU = 566,
    SLTZ = 567,
    SM3P0 = 568,
    SM3P1 = 569,
    SM4ED = 570,
    SM4KS = 571,
    SNEZ = 572,
    SRA = 573,
    SRAI = 574,
    SRAIRV32 = 575,
    SRAIW = 576,
    SRAW = 577,
    SRET = 578,
    SRL = 579,
    SRLI = 580,
    SRLIRV32 = 581,
    SRLIW = 582,
    SRLW = 583,
    SSAMOSWAPD = 584,
    SSAMOSWAPW = 585,
    SSPOPCHKX1 = 586,
    SSPOPCHKX5 = 587,
    SSPUSHX1 = 588,
    SSPUSHX5 = 589,
    SSRDP = 590,
    SUB = 591,
    SUBW = 592,
    SW = 593,
    UNZIP = 594,
    VAADDVV = 595,
    VAADDVX = 596,
    VAADDUVV = 597,
    VAADDUVX = 598,
    VADCVIM = 599,
    VADCVVM = 600,
    VADCVXM = 601,
    VADDVI = 602,
    VADDVV = 603,
    VADDVX = 604,
    VAESDFVS = 605,
    VAESDFVV = 606,
    VAESDMVS = 607,
    VAESDMVV = 608,
    VAESEFVS = 609,
    VAESEFVV = 610,
    VAESEMVS = 611,
    VAESEMVV = 612,
    VAESKF1VI = 613,
    VAESKF2VI = 614,
    VAESZVS = 615,
    VANDVI = 616,
    VANDVV = 617,
    VANDVX = 618,
    VANDNVV = 619,
    VANDNVX = 620,
    VASUBVV = 621,
    VASUBVX = 622,
    VASUBUVV = 623,
    VASUBUVX = 624,
    VBREV8V = 625,
    VBREVV = 626,
    VCLMULVV = 627,
    VCLMULVX = 628,
    VCLMULHVV = 629,
    VCLMULHVX = 630,
    VCLZV = 631,
    VCOMPRESSVM = 632,
    VCPOPM = 633,
    VCPOPV = 634,
    VCTZV = 635,
    VDIVVV = 636,
    VDIVVX = 637,
    VDIVUVV = 638,
    VDIVUVX = 639,
    VFADDVF = 640,
    VFADDVV = 641,
    VFCLASSV = 642,
    VFCVTFXV = 643,
    VFCVTFXUV = 644,
    VFCVTRTZXFV = 645,
    VFCVTRTZXUFV = 646,
    VFCVTXFV = 647,
    VFCVTXUFV = 648,
    VFDIVVF = 649,
    VFDIVVV = 650,
    VFIRSTM = 651,
    VFMACCVF = 652,
    VFMACCVV = 653,
    VFMADDVF = 654,
    VFMADDVV = 655,
    VFMAXVF = 656,
    VFMAXVV = 657,
    VFMERGEVFM = 658,
    VFMINVF = 659,
    VFMINVV = 660,
    VFMSACVF = 661,
    VFMSACVV = 662,
    VFMSUBVF = 663,
    VFMSUBVV = 664,
    VFMULVF = 665,
    VFMULVV = 666,
    VFMVFS = 667,
    VFMVSF = 668,
    VFMVVF = 669,
    VFNCVTFFW = 670,
    VFNCVTFXW = 671,
    VFNCVTFXUW = 672,
    VFNCVTRODFFW = 673,
    VFNCVTRTZXFW = 674,
    VFNCVTRTZXUFW = 675,
    VFNCVTXFW = 676,
    VFNCVTXUFW = 677,
    VFNCVTBF16FFW = 678,
    VFNMACCVF = 679,
    VFNMACCVV = 680,
    VFNMADDVF = 681,
    VFNMADDVV = 682,
    VFNMSACVF = 683,
    VFNMSACVV = 684,
    VFNMSUBVF = 685,
    VFNMSUBVV = 686,
    VFRDIVVF = 687,
    VFREC7V = 688,
    VFREDMAXVS = 689,
    VFREDMINVS = 690,
    VFREDOSUMVS = 691,
    VFREDSUMVS = 692,
    VFREDUSUMVS = 693,
    VFRSQRT7V = 694,
    VFRSUBVF = 695,
    VFSGNJVF = 696,
    VFSGNJVV = 697,
    VFSGNJNVF = 698,
    VFSGNJNVV = 699,
    VFSGNJXVF = 700,
    VFSGNJXVV = 701,
    VFSLIDE1DOWNVF = 702,
    VFSLIDE1UPVF = 703,
    VFSQRTV = 704,
    VFSUBVF = 705,
    VFSUBVV = 706,
    VFWADDVF = 707,
    VFWADDVV = 708,
    VFWADDWF = 709,
    VFWADDWV = 710,
    VFWCVTFFV = 711,
    VFWCVTFXV = 712,
    VFWCVTFXUV = 713,
    VFWCVTRTZXFV = 714,
    VFWCVTRTZXUFV = 715,
    VFWCVTXFV = 716,
    VFWCVTXUFV = 717,
    VFWCVTBF16FFV = 718,
    VFWMACCVF = 719,
    VFWMACCVV = 720,
    VFWMACCBF16VF = 721,
    VFWMACCBF16VV = 722,
    VFWMSACVF = 723,
    VFWMSACVV = 724,
    VFWMULVF = 725,
    VFWMULVV = 726,
    VFWNMACCVF = 727,
    VFWNMACCVV = 728,
    VFWNMSACVF = 729,
    VFWNMSACVV = 730,
    VFWREDOSUMVS = 731,
    VFWREDSUMVS = 732,
    VFWREDUSUMVS = 733,
    VFWSUBVF = 734,
    VFWSUBVV = 735,
    VFWSUBWF = 736,
    VFWSUBWV = 737,
    VGHSHVV = 738,
    VGMULVV = 739,
    VIDV = 740,
    VIOTAM = 741,
    VL1RV = 742,
    VL1RE16V = 743,
    VL1RE32V = 744,
    VL1RE64V = 745,
    VL1RE8V = 746,
    VL2RV = 747,
    VL2RE16V = 748,
    VL2RE32V = 749,
    VL2RE64V = 750,
    VL2RE8V = 751,
    VL4RV = 752,
    VL4RE16V = 753,
    VL4RE32V = 754,
    VL4RE64V = 755,
    VL4RE8V = 756,
    VL8RV = 757,
    VL8RE16V = 758,
    VL8RE32V = 759,
    VL8RE64V = 760,
    VL8RE8V = 761,
    VLE16V = 762,
    VLE16FFV = 763,
    VLE1V = 764,
    VLE32V = 765,
    VLE32FFV = 766,
    VLE64V = 767,
    VLE64FFV = 768,
    VLE8V = 769,
    VLE8FFV = 770,
    VLMV = 771,
    VLOXEI16V = 772,
    VLOXEI32V = 773,
    VLOXEI64V = 774,
    VLOXEI8V = 775,
    VLSE16V = 776,
    VLSE32V = 777,
    VLSE64V = 778,
    VLSE8V = 779,
    VLUXEI16V = 780,
    VLUXEI32V = 781,
    VLUXEI64V = 782,
    VLUXEI8V = 783,
    VMACCVV = 784,
    VMACCVX = 785,
    VMADCVI = 786,
    VMADCVIM = 787,
    VMADCVV = 788,
    VMADCVVM = 789,
    VMADCVX = 790,
    VMADCVXM = 791,
    VMADDVV = 792,
    VMADDVX = 793,
    VMANDMM = 794,
    VMANDNMM = 795,
    VMANDNOTMM = 796,
    VMAXVV = 797,
    VMAXVX = 798,
    VMAXUVV = 799,
    VMAXUVX = 800,
    VMERGEVIM = 801,
    VMERGEVVM = 802,
    VMERGEVXM = 803,
    VMFEQVF = 804,
    VMFEQVV = 805,
    VMFGEVF = 806,
    VMFGTVF = 807,
    VMFLEVF = 808,
    VMFLEVV = 809,
    VMFLTVF = 810,
    VMFLTVV = 811,
    VMFNEVF = 812,
    VMFNEVV = 813,
    VMINVV = 814,
    VMINVX = 815,
    VMINUVV = 816,
    VMINUVX = 817,
    VMNANDMM = 818,
    VMNORMM = 819,
    VMORMM = 820,
    VMORNMM = 821,
    VMORNOTMM = 822,
    VMSBCVV = 823,
    VMSBCVVM = 824,
    VMSBCVX = 825,
    VMSBCVXM = 826,
    VMSBFM = 827,
    VMSEQVI = 828,
    VMSEQVV = 829,
    VMSEQVX = 830,
    VMSGTVI = 831,
    VMSGTVX = 832,
    VMSGTUVI = 833,
    VMSGTUVX = 834,
    VMSIFM = 835,
    VMSLEVI = 836,
    VMSLEVV = 837,
    VMSLEVX = 838,
    VMSLEUVI = 839,
    VMSLEUVV = 840,
    VMSLEUVX = 841,
    VMSLTVV = 842,
    VMSLTVX = 843,
    VMSLTUVV = 844,
    VMSLTUVX = 845,
    VMSNEVI = 846,
    VMSNEVV = 847,
    VMSNEVX = 848,
    VMSOFM = 849,
    VMULVV = 850,
    VMULVX = 851,
    VMULHVV = 852,
    VMULHVX = 853,
    VMULHSUVV = 854,
    VMULHSUVX = 855,
    VMULHUVV = 856,
    VMULHUVX = 857,
    VMV1RV = 858,
    VMV2RV = 859,
    VMV4RV = 860,
    VMV8RV = 861,
    VMVSX = 862,
    VMVVI = 863,
    VMVVV = 864,
    VMVVX = 865,
    VMVXS = 866,
    VMXNORMM = 867,
    VMXORMM = 868,
    VNCLIPWI = 869,
    VNCLIPWV = 870,
    VNCLIPWX = 871,
    VNCLIPUWI = 872,
    VNCLIPUWV = 873,
    VNCLIPUWX = 874,
    VNMSACVV = 875,
    VNMSACVX = 876,
    VNMSUBVV = 877,
    VNMSUBVX = 878,
    VNSRAWI = 879,
    VNSRAWV = 880,
    VNSRAWX = 881,
    VNSRLWI = 882,
    VNSRLWV = 883,
    VNSRLWX = 884,
    VORVI = 885,
    VORVV = 886,
    VORVX = 887,
    VPOPCM = 888,
    VREDANDVS = 889,
    VREDMAXVS = 890,
    VREDMAXUVS = 891,
    VREDMINVS = 892,
    VREDMINUVS = 893,
    VREDORVS = 894,
    VREDSUMVS = 895,
    VREDXORVS = 896,
    VREMVV = 897,
    VREMVX = 898,
    VREMUVV = 899,
    VREMUVX = 900,
    VREV8V = 901,
    VRGATHERVI = 902,
    VRGATHERVV = 903,
    VRGATHERVX = 904,
    VRGATHEREI16VV = 905,
    VROLVV = 906,
    VROLVX = 907,
    VRORVI = 908,
    VRORVV = 909,
    VRORVX = 910,
    VRSUBVI = 911,
    VRSUBVX = 912,
    VS1RV = 913,
    VS2RV = 914,
    VS4RV = 915,
    VS8RV = 916,
    VSADDVI = 917,
    VSADDVV = 918,
    VSADDVX = 919,
    VSADDUVI = 920,
    VSADDUVV = 921,
    VSADDUVX = 922,
    VSBCVVM = 923,
    VSBCVXM = 924,
    VSE16V = 925,
    VSE1V = 926,
    VSE32V = 927,
    VSE64V = 928,
    VSE8V = 929,
    VSETIVLI = 930,
    VSETVL = 931,
    VSETVLI = 932,
    VSEXTVF2 = 933,
    VSEXTVF4 = 934,
    VSEXTVF8 = 935,
    VSHA2CHVV = 936,
    VSHA2CLVV = 937,
    VSHA2MSVV = 938,
    VSLIDE1DOWNVX = 939,
    VSLIDE1UPVX = 940,
    VSLIDEDOWNVI = 941,
    VSLIDEDOWNVX = 942,
    VSLIDEUPVI = 943,
    VSLIDEUPVX = 944,
    VSLLVI = 945,
    VSLLVV = 946,
    VSLLVX = 947,
    VSM3CVI = 948,
    VSM3MEVV = 949,
    VSM4KVI = 950,
    VSM4RVS = 951,
    VSM4RVV = 952,
    VSMV = 953,
    VSMULVV = 954,
    VSMULVX = 955,
    VSOXEI16V = 956,
    VSOXEI32V = 957,
    VSOXEI64V = 958,
    VSOXEI8V = 959,
    VSRAVI = 960,
    VSRAVV = 961,
    VSRAVX = 962,
    VSRLVI = 963,
    VSRLVV = 964,
    VSRLVX = 965,
    VSSE16V = 966,
    VSSE32V = 967,
    VSSE64V = 968,
    VSSE8V = 969,
    VSSRAVI = 970,
    VSSRAVV = 971,
    VSSRAVX = 972,
    VSSRLVI = 973,
    VSSRLVV = 974,
    VSSRLVX = 975,
    VSSUBVV = 976,
    VSSUBVX = 977,
    VSSUBUVV = 978,
    VSSUBUVX = 979,
    VSUBVV = 980,
    VSUBVX = 981,
    VSUXEI16V = 982,
    VSUXEI32V = 983,
    VSUXEI64V = 984,
    VSUXEI8V = 985,
    VWADDVV = 986,
    VWADDVX = 987,
    VWADDWV = 988,
    VWADDWX = 989,
    VWADDUVV = 990,
    VWADDUVX = 991,
    VWADDUWV = 992,
    VWADDUWX = 993,
    VWMACCVV = 994,
    VWMACCVX = 995,
    VWMACCSUVV = 996,
    VWMACCSUVX = 997,
    VWMACCUVV = 998,
    VWMACCUVX = 999,
    VWMACCUSVX = 1000,
    VWMULVV = 1001,
    VWMULVX = 1002,
    VWMULSUVV = 1003,
    VWMULSUVX = 1004,
    VWMULUVV = 1005,
    VWMULUVX = 1006,
    VWREDSUMVS = 1007,
    VWREDSUMUVS = 1008,
    VWSLLVI = 1009,
    VWSLLVV = 1010,
    VWSLLVX = 1011,
    VWSUBVV = 1012,
    VWSUBVX = 1013,
    VWSUBWV = 1014,
    VWSUBWX = 1015,
    VWSUBUVV = 1016,
    VWSUBUVX = 1017,
    VWSUBUWV = 1018,
    VWSUBUWX = 1019,
    VXORVI = 1020,
    VXORVV = 1021,
    VXORVX = 1022,
    VZEXTVF2 = 1023,
    VZEXTVF4 = 1024,
    VZEXTVF8 = 1025,
    WFI = 1026,
    WRSNTO = 1027,
    WRSSTO = 1028,
    XNOR = 1029,
    XOR = 1030,
    XORI = 1031,
    XPERM4 = 1032,
    XPERM8 = 1033,
    ZEXTB = 1034,
    ZEXTH = 1035,
    ZEXTHRV32 = 1036,
    ZEXTW = 1037,
    ZIP = 1038,
    Invalid = 1039,
}

Atomic fetch-and-add doubleword

Atomically:

Load the doubleword at address rs1
Write the loaded value into rd
Add the value of register rs2 to the loaded value
Write the sum to the address in rs1

§Forms

Assembly: amoadd.d xd, xs2, (xs1)

§

AMOADDH = 18

RISC-V amoadd.h instruction.

§Forms

Assembly: amoadd.h xd, xs1, xs2, aq, rl

§

AMOADDW = 19

Atomic fetch-and-add word

Atomically:

Load the word at address rs1
Write the sign-extended value into rd
Add the least-significant word of register rs2 to the loaded value
Write the sum to the address in rs1

§Forms

Assembly: amoadd.w xd, xs2, (xrs1)

§

AMOANDB = 20

RISC-V amoand.b instruction.

§Forms

Assembly: amoand.b xd, xs1, xs2, aq, rl

§

AMOANDD = 21

Atomic fetch-and-and doubleword

Atomically:

Load the doubleword at address rs1
Write the loaded value into rd
AND the value of register rs2 to the loaded value
Write the result to the address in rs1

§Forms

Assembly: amoand.d xd, xs2, (xrs1)

§

AMOANDH = 22

RISC-V amoand.h instruction.

§Forms

Assembly: amoand.h xd, xs1, xs2, aq, rl

§

AMOANDW = 23

Atomic fetch-and-and word

Atomically:

Load the word at address rs1
Write the sign-extended value into rd
AND the least-significant word of register rs2 to the loaded value
Write the result to the address in rs1

Load the word at address rs1
Write the sign-extended value into rd
XOR the least-significant word of register rs2 to the loaded value
Write the result to the address in rs1

Raise a MisalignedAddress exception if PC + imm is misaligned.

§Forms

Assembly: beq xs1, xs2, imm

§

Branch if greater than or equal

Branch to PC + imm if the signed value in register rs1 is greater than or equal to the signed value in register rs2.

Raise a MisalignedAddress exception if PC + imm is misaligned.

§Forms

Assembly: bge xs1, xs2, imm

§

BGEU = 70

Branch if greater than or equal unsigned

Branch to PC + imm if the unsigned value in register rs1 is greater than or equal to the unsigned value in register rs2.

Branch if less than

Branch to PC + imm if the signed value in register rs1 is less than the signed value in register rs2.

Raise a MisalignedAddress exception if PC + imm is misaligned.

§Forms

Assembly: blt xs1, xs2, imm

§

BLTU = 82

Branch if less than unsigned

Branch to PC + imm if the unsigned value in register rs1 is less than the unsigned value in register rs2.

Raise a MisalignedAddress exception if PC + imm is misaligned.

§Forms

Assembly: bltu xs1, xs2, imm

§

BLTZ = 83

RISC-V bltz instruction.

§Forms

Assembly: bltz rs1 bimm12lohi

§

BNE = 84

Branch if not equal

Branch to PC + imm if the value in register rs1 is not equal to the value in register rs2.

Raise a MisalignedAddress exception if PC + imm is misaligned.

§Forms

Assembly: bne xs1, xs2, imm

§

§Forms

Assembly: c.sspopchk.x5

§

Cache Block Clean

Cleans an entire cache block globally throughout the system.

Exactly what happens is coherence protocol-dependent, but in general it is expected that after this operation():

The cache block will be in the clean (not dirty) state in any coherent cache holding a valid copy of the line.
The data will be cleaned to a point such that an incoherent load can observe the cleaned data.

cbo.clean is ordered by FENCE instructions but not FENCE.I or SFENCE.VMA.

<%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%> Both PMP and PMA access control must be the same for all bytes in the block; otherwise, cbo.clean has UNSPECIFIED behavior. <%- end -%>

Clean operations are treated as stores for page and access permissions. If permission checks fail, one of the following exceptions will occur:

<%- if ext?(:H) -%>

Store/AMO Guest-Page Fault if virtual memory translation fails during G-stage translation. <%- end -%>
Store/AMO Page Fault if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
Store/AMO Access Fault if a PMP or PMA access check fails

<%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%> Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP and PMA access checks only need to check a single address in the line. <%- end -%>

CBO operations never raise a misaligned address fault.

§Forms

Assembly: cbo.clean "TODO"

§

CBOFLUSH = 164

Cache Block Flush

Flushes an entire cache block by cleaning it and then invalidating it in all caches.

cbo.flush is ordered by FENCE instructions but not FENCE.I or SFENCE.VMA.

<%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%> Both PMP and PMA access control must be the same for all bytes in the block; otherwise, cbo.flush has UNSPECIFIED behavior. <%- end -%>

Flush operations are treated as stores for page and access permissions. If permission checks fail, one of the following exceptions will occur:

<%- if ext?(:H) -%>

Store/AMO Guest-Page Fault if virtual memory translation fails during G-stage translation. <%- end -%>
Store/AMO Page Fault if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
Store/AMO Access Fault if a PMP or PMA access check fails.

<%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%> Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP and PMA access checks only need to check a single address in the line. <%- end -%>

CBO operations never raise a misaligned address fault.

§Forms

Assembly: cbo.flush "TODO"

§

CBOINVAL = 165

Cache Block Invalidate

Either invalidates or flushes (clean + invalidate) a cache block, depending on the current mode and value of menvcfg.CBIE, senvcfg.CBIE, and/or henvcfg.CBIE.

The instruction is an invalidate (without a clean) when:

In M-mode
In (H)S-mode and menvcfg.CBIE == 11
In U-mode and menvcfg.CBIE == 11 and senvcfg.CBIE == 11
In VS-mode and menvcfg.CBIE == 11 and henvcfg.CBIE == 11
In VU-mode and menvcfg.CBIE == 11 and henvcfg.CBIE == 11 and senvcfg.CBIE == 11

Otherwise, if the instruction does not trap (see Access section), the operation is a flush. The table below summarizes the options.

[%autowidth,cols=“1,1,1,1,1,1,1,1”,separator=“!”] !=== .2+h![.rotate]#menvcfg.CBIE# .2+h! [.rotate]#senvcfg.CBIE# .2+h! [.rotate]#henvcfg.CBIE# 5+^.>h! cbe.inval Operation .^h! M-mode .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode

! 00 ! - ! - ! Invalidate ! Illegal Instruction ! Illegal Instruction ! Virtual Instruction ! Virtual Instruction ! 01 ! 00 ! 00 ! Invalidate ! Flush ! Illegal Instruction ! Virtual Instruction ! Virtual Instruction ! 01 ! 00 ! 01 ! Invalidate ! Flush ! Illegal Instruction ! Flush ! Virtual Instruction ! 01 ! 00 ! 11 ! Invalidate ! Flush ! Illegal Instruction ! Flush ! Virtual Instruction ! 01 ! 01 ! 00 ! Invalidate ! Flush ! Flush ! Virtual Instruction ! Virtual Instruction ! 01 ! 01 ! 01 ! Invalidate ! Flush ! Flush ! Flush ! Flush ! 01 ! 01 ! 11 ! Invalidate ! Flush ! Flush ! Flush ! Flush ! 01 ! 11 ! 00 ! Invalidate ! Flush ! Flush ! Virtual Instruction ! Virtual Instruction ! 01 ! 11 ! 01 ! Invalidate ! Flush ! Flush ! Flush ! Flush ! 01 ! 11 ! 11 ! Invalidate ! Flush ! Flush ! Flush ! Flush ! 11 ! 00 ! 00 ! Invalidate ! Invalidate ! Illegal Instruction ! Virtual Instruction ! Virtual Instruction ! 11 ! 00 ! 01 ! Invalidate ! Invalidate ! Illegal Instruction ! Flush ! Virtual Instruction ! 11 ! 00 ! 11 ! Invalidate ! Invalidate ! Illegal Instruction ! Invalidate ! Virtual Instruction ! 11 ! 01 ! 00 ! Invalidate ! Invalidate ! Flush ! Virtual Instruction ! Virtual Instruction ! 11 ! 01 ! 01 ! Invalidate ! Invalidate ! Flush ! Flush ! Flush ! 11 ! 01 ! 11 ! Invalidate ! Invalidate ! Flush ! Invalidate ! Flush ! 11 ! 11 ! 00 ! Invalidate ! Invalidate ! Invalidate ! Virtual Instruction ! Virtual Instruction ! 11 ! 11 ! 01 ! Invalidate ! Invalidate ! Invalidate ! Flush ! Flush ! 11 ! 11 ! 11 ! Invalidate ! Invalidate ! Invalidate ! Invalidate ! Invalidate !===

cbo.inval is ordered by FENCE instructions but not FENCE.I or SFENCE.VMA.

<%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%> Both PMP and PMA access control must be the same for all bytes in the block; otherwise, cbo.zero has UNSPECIFIED behavior. <%- end -%>

Invalidate operations are treated as stores for page and access permissions. If permission checks fail, one of the following exceptions will occur:

<%- if ext?(:H) -%>

Store/AMO Guest-Page Fault if virtual memory translation fails during G-stage translation. <%- end -%>
Store/AMO Page Fault if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
Store/AMO Access Fault if a PMP or PMA access check fails.

<%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%> Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP and PMA access checks only need to check a single address in the line. <%- end -%>

CBO operations never raise a misaligned address fault.

§Forms

Assembly: cbo.inval "TODO"

§

CBOZERO = 166

Cache Block Zero

Zeros an entire cache block

The block zeroing does not need to be atomic.

cbo.zero is ordered by FENCE instructions but not FENCE.I or SFENCE.VMA.

<%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%> Both PMP and PMA access control must be the same for all bytes in the block; otherwise, cbo.zero has UNSPECIFIED behavior. <%- end -%>

Clean operations are treated as stores for page and access permissions. If permission checks fail, one of the following exceptions will occur:

<%- if ext?(:H) -%>

Store/AMO Guest-Page Fault if virtual memory translation fails during G-stage translation. <%- end -%>
Store/AMO Page Fault if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %>
Store/AMO Access Fault if a PMP or PMA access check fails.

RISC-V cm.jalt instruction.

§Forms

Assembly: cm.jalt c_index

§

CMMVA01S = 173

Move two s0-s7 registers into a0-a1

This instruction moves r1s’ into a0 and r2s’ into a1. The execution is atomic, so it is not possible to observe state where only one of a0 or a1 have been updated. The encoding uses sreg number specifiers instead of xreg number specifiers to save encoding space. The mapping between them is specified in the pseudo-code below.

§Forms

Assembly: cm.mva01s r1s, r2s

§

CMMVSA01 = 174

§.Software Hint [NOTE]

This operations is known as population count, popcount, sideways sum, bit summation, or Hamming weight.

§The GCC builtin function `__builtin_popcount (unsigned int x)` is implemented by cpop on RV32 and by cpopw on RV64. The GCC builtin function `__builtin_popcountl (unsigned long x)` for LP64 is implemented by cpop on RV64.

§Forms

Assembly: cpop xd, xs1

§

CPOPW = 180

Count set bits in word

This instructions counts the number of 1’s (i.e., set bits) in the least-significant word of the source register.

§.Software Hint [NOTE]

This operations is known as population count, popcount, sideways sum, bit summation, or Hamming weight.

Atomic Read and Set Bits in CSR

Atomically read and set bits in a CSR.

Reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are not explicitly written.

§Forms

Assembly: csrrs xd, xs1, csr

Count trailing zero bits

This instruction counts the number of 0’s before the first 1, starting at the least-significant bit (i.e., 0) and progressing to the most-significant bit (i.e., XLEN-1). Accordingly, if the input is 0, the output is XLEN, and if the least-significant bit of the input is a 1, the output is 0.

§Forms

Assembly: ctz xd, xs1

§

CTZW = 195

Count trailing zero bits in word

Assembly: ebreak ""

§

ECALL = 204

Environment call

The ECALL instruction is used to make a request to the supporting execution environment. When executed in U-mode, S-mode, or M-mode, it generates an environment-call-from-U-mode exception, environment-call-from-S-mode exception, or environment-call-from-M-mode exception, respectively, and performs no other operation.

[NOTE] ECALL generates a different exception for each originating privilege mode so that environment call exceptions can be selectively delegated. A typical use case for Unix-like operating systems is to delegate to S-mode the environment-call-from-U-mode exception but not the others.

Single-precision floating-point addition

For XLEN >32, fcvt.w.s sign-extends the 32-bit result to the destination register width.

If the rounded result is not representable as a 32-bit signed integer, it is clipped to the nearest value and the invalid flag is set.

The range of valid inputs and behavior for invalid inputs are:

Memory ordering fence

Orders memory operations.

The fence instruction is used to order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors. Any combination of device input (I), device output (O), memory reads (R), and memory writes (W) may be ordered with respect to any combination of the same. Informally, no other RISC-V hart or external device can observe any operation in the successor set following a fence before any operation in the predecessor set preceding the fence.

The predecessor and successor fields have the same format to specify operation types:

[%autowidth] |=== 4+| pred 4+| succ

| 27 | 26 |25 | 24 | 23 | 22 | 21| 20 | PI | PO |PR | PW | SI | SO |SR | SW |===

When the mode field fm is 0001 and both the predecessor and successor sets are ‘RW’, then the instruction acts as a special-case fence.tso. fence.tso orders all load operations in its predecessor set before all memory operations in its successor set, and all store operations in its predecessor set before all store operations in its successor set. This leaves non-AMO store operations in the ’fence.tso’s predecessor set unordered with non-AMO loads in its successor set.

When mode field fm is not 0001, or when mode field fm is 0001 but the pred and succ fields are not both ‘RW’ (0x3), then the fence acts as a baseline fence (e.g., fm is effectively 0000). This is unaffected by the FIOM bits, described below (implicit promotion does not change how fence.tso is decoded).

The rs1 and rd fields are unused and ignored.

In modes other than M-mode, fence is further affected by menvcfg.FIOM, senvcfg.FIOM<% if ext?(:H) %>, and/or henvcfg.FIOM<% end %> as follows:

.Effective PR/PW/SR/SW in (H)S-mode [%autowidth,cols=“,,,”,options=“header”,separator=“!”] !=== ! [.rotate]#menvcfg.FIOM# ! pred.PI + pred.PO + succ.SI + succ.SO ! -> + -> + -> + -> ! effective PR + effective PW + effective SR + effective SW

! 0 ! - ! ! from encoding ! 1 ! 0 ! ! from encoding ! 1 ! 1 ! ! 1 !===

.Effective PR/PW/SR/SW in U-mode [%autowidth,options=“header”,separator=“!”,cols=“,,,,”] !=== ! [.rotate]#menvcfg.FIOM# ! [.rotate]#senvcfg.FIOM# ! pred.PI + pred.PO + succ.SI + succ.SO ! -> + -> + -> + -> ! effective PR + effective PW + effective SR + effective SW

! 0 ! 0 ! - ! ! from encoding ! 0 ! 1 ! 0 ! ! from encoding ! 0 ! 1 ! 1 ! ! 1 ! 1 ! - ! 0 ! ! from encoding ! 1 ! - ! 1 ! ! 1 !===

<%- if ext?(:H) -%> .Effective PR/PW/SR/SW in VS-mode and VU-mode [%autowidth,options=“header”,separator=“!”,cols=“,,,,”] !=== ! [.rotate]#menvcfg.FIOM# ! [.rotate]#henvcfg.FIOM# ! pred.PI + pred.PO + succ.SI + succ.SO ! -> + -> + -> + -> ! effective PR + effective PW + effective SR + effective SW

! 0 ! 0 ! - ! ! from encoding ! 0 ! 1 ! 0 ! ! from encoding ! 0 ! 1 ! 1 ! ! 1 ! 1 ! - ! 0 ! ! from encoding ! 1 ! - ! 1 ! ! 1 !=== <%- end -%>

§Forms

Assembly: fence "TODO"

§

FENCEI = 269

Instruction fence

Assembly: feq.q xd, qs1, qs2

§

FEQS = 274

Single-precision floating-point equal

Writes 1 to rd if fs1 and fs2 are equal, and 0 otherwise.

If either operand is NaN, the result is 0 (not equal). If either operand is a signaling NaN, the invalid flag is set.

Single-precision floating-point less than

Writes 1 to rd if fs1 is less than fs2, and 0 otherwise.

Half-precision floating-point move from integer

Single-precision floating-point move from integer

Assembly: fmv.x.h rd, fs1

§

FMVXS = 337

RISC-V fmv.x.s instruction.

§Forms

Assembly: fmv.x.s rd rs1

§

FMVXW = 338

Single-precision sign inject

Writes fd with sign bit of fs2 and the exponent and mantissa of fs1.

Single-precision sign inject negate

Writes fd with the opposite of the sign bit of fs2 and the exponent and mantissa of fs1.

Single-precision sign inject exclusive or

Writes fd with the xor of the sign bits of fs2 and fs1 and the exponent and mantissa of fs1.

Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs.

§Forms

Assembly: fsgnjx.s fd, fs1, fs2

§

FSH = 382

Half-precision floating-point store

Single-precision floating-point subtraction

Do the single-precision floating-point subtraction of fs2 from fs1 and store the result in fd. rm is the dynamic Rounding Mode.

§Forms

Assembly: fsub.s fd, fs1, fs2, rm

§

FSW = 394

Single-precision floating-point store

The fsw instruction stores a single-precision floating-point value in fs2 to memory at address rs1 + imm.

Invalidate cached address translations

hinval.gvma has the same semantics as sinval.vma except that it combines with sfence.w.inval and sfence.inval.ir to replace hfence.gvma and uses VMID instead of ASID.

§Forms

Assembly: hinval.gvma xs1, xs2

§

HINVALVVMA = 398

RISC-V lpad instruction.

§Forms

Assembly: lpad imm

§

LRD = 424

Load reserved doubleword

Loads a word from the address in rs1, places the value in rd, and registers a reservation set – a set of bytes that subsumes the bytes in the addressed word.

The address in rs1 must be 8-byte aligned.

If the address is not naturally aligned, a LoadAddressMisaligned exception or an LoadAccessFault exception will be generated. The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.

An implementation can register an arbitrarily large reservation set on each LR, provided the reservation set includes all bytes of the addressed data word or doubleword. An SC can only pair with the most recent LR in program order. An SC may succeed only if no store from another hart to the reservation set can be observed to have occurred between the LR and the SC, and if there is no other SC between the LR and itself in program order. An SC may succeed only if no write from a device other than a hart to the bytes accessed by the LR instruction can be observed to have occurred between the LR and SC. Note this LR might have had a different effective address and data size, but reserved the SC’s address as part of the reservation set.

§[NOTE]

Following this model, in systems with memory translation, an SC is allowed to succeed if the earlier LR reserved the same location using an alias with a different virtual address, but is also allowed to fail if the virtual address is different.

§To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only required to invalidate reservations when they overlap the bytes accessed by the LR. These writes are not required to invalidate the reservation when they access other bytes in the reservation set.

Software should not set the rl bit on an LR instruction unless the aq bit is also set. LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those with both bits clear, but may result in lower performance.

§Forms

Assembly: lr.d xd, xs1

§

LRW = 425

Load reserved word

Loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set – a set of bytes that subsumes the bytes in the addressed word.

<%- if XLEN == 64 -%> The 32-bit load result is sign-extended to 64-bits. <%- end -%>

The address in rs1 must be naturally aligned to the size of the operand (i.e., eight-byte aligned for doublewords and four-byte aligned for words).

If the address is not naturally aligned, a LoadAddressMisaligned exception or an LoadAccessFault exception will be generated. The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.

An implementation can register an arbitrarily large reservation set on each LR, provided the reservation set includes all bytes of the addressed data word or doubleword. An SC can only pair with the most recent LR in program order. An SC may succeed only if no store from another hart to the reservation set can be observed to have occurred between the LR and the SC, and if there is no other SC between the LR and itself in program order. An SC may succeed only if no write from a device other than a hart to the bytes accessed by the LR instruction can be observed to have occurred between the LR and SC. Note this LR might have had a different effective address and data size, but reserved the SC’s address as part of the reservation set.

§[NOTE]

Following this model, in systems with memory translation, an SC is allowed to succeed if the earlier LR reserved the same location using an alias with a different virtual address, but is also allowed to fail if the virtual address is different.

Maximum

Machine Exception Return

Returns from an exception in M-mode.

§Forms

Assembly: mret ""

§

MUL = 477

Any overflow is thrown away.

Assembly: rem xd, xs1, xs2

§

REMU = 507

Unsigned remainder

Calculate the remainder of unsigned division of rs1 by rs2, and store the result in rd.

§Forms

Assembly: remu xd, xs1, xs2

§

REMUW = 508

Unsigned 32-bit remainder

Calculate the remainder of unsigned division of the 32-bit values in rs1 by rs2, and store the sign-extended result in rd.

If the value in rs2 is zero, rd gets the sign-extended value in rs1.

§Forms

Assembly: remuw xd, xs1, xs2

§

REMW = 509

Signed 32-bit remainder

Calculate the remainder of signed division of the 32-bit values rs1 by rs2, and store the sign-extended result in rd.

If the value in register rs2 is zero, write the sign-extended 32-bit value in rs1 into rd;

Assembly: rev8 xd, xs1

§

REV8RV32 = 512

RISC-V sbreak instruction.

§Forms

Assembly: sbreak

§

SCD = 522

Store conditional doubleword

sc.d conditionally writes a doubleword in rs2 to the address in rs1: the sc.d succeeds only if the reservation is still valid and the reservation set contains the bytes being written. If the sc.d succeeds, the instruction writes the doubleword in rs2 to memory, and it writes zero to rd. If the sc.d fails, the instruction does not write to memory, and it writes a nonzero value to rd. For the purposes of memory protection, a failed sc.d may be treated like a store. Regardless of success or failure, executing an sc.d instruction invalidates any reservation held by this hart.

The failure code with value 1 encodes an unspecified failure. Other failure codes are reserved at this time. Portable software should only assume the failure code will be non-zero.

A store-conditional instruction to a scratch word of memory should be used to forcibly invalidate any existing load reservation:

during a preemptive context switch, and
if necessary when changing virtual to physical address mappings, such as when migrating pages that might contain an active reservation.

§The invalidation of a hart’s reservation when it executes an LR or SC imply that a hart can only hold one reservation at a time, and that an SC can only pair with the most recent LR, and LR with the next following SC, in program order. This is a restriction to the Atomicity Axiom in Section 18.1 that ensures software runs correctly on expected common implementations that operate in this manner.

An SC instruction can never be observed by another RISC-V hart before the LR instruction that established the reservation.

§[NOTE]

The LR/SC sequence can be given acquire semantics by setting the aq bit on the LR instruction. The LR/SC sequence can be given release semantics by by setting the rl bit on the SC instruction. Assuming suitable mappings for other atomic operations, setting the aq bit on the LR instruction, and setting the rl bit on the SC instruction makes the LR/SC sequence sequentially consistent in the C++ memory_order_seq_cst sense. Such a sequence does not act as a fence for ordering ordinary load and store instructions before and after the sequence. Specific instruction mappings for other C++ atomic operations, or stronger notions of “sequential consistency”, may require both bits to be set on either or both of the LR or SC instruction.

§If neither bit is set on either LR or SC, the LR/SC sequence can be observed to occur before or after surrounding memory operations from the same RISC-V hart. This can be appropriate when the LR/SC sequence is used to implement a parallel reduction operation.

Software should not set the rl bit on an LR instruction unless the aq bit is also set. LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those with both bits clear, but may result in lower performance.

§Forms

Assembly: sc.d xd, xs2, xs1

§

SCW = 523

Store conditional word

sc.w conditionally writes a word in rs2 to the address in rs1: the sc.w succeeds only if the reservation is still valid and the reservation set contains the bytes being written. If the sc.w succeeds, the instruction writes the word in rs2 to memory, and it writes zero to rd. If the sc.w fails, the instruction does not write to memory, and it writes a nonzero value to rd. For the purposes of memory protection, a failed sc.w may be treated like a store. Regardless of success or failure, executing an sc.w instruction invalidates any reservation held by this hart.

<%- if XLEN == 64 -%> [NOTE] If a value other than 0 or 1 is defined as a result for sc.w, the value will before sign-extended into rd. <%- end -%>

The failure code with value 1 encodes an unspecified failure. Other failure codes are reserved at this time. Portable software should only assume the failure code will be non-zero.

A store-conditional instruction to a scratch word of memory should be used to forcibly invalidate any existing load reservation:

during a preemptive context switch, and
if necessary when changing virtual to physical address mappings, such as when migrating pages that might contain an active reservation.

§The invalidation of a hart’s reservation when it executes an LR or SC imply that a hart can only hold one reservation at a time, and that an SC can only pair with the most recent LR, and LR with the next following SC, in program order. This is a restriction to the Atomicity Axiom in Section 18.1 that ensures software runs correctly on expected common implementations that operate in this manner.

An SC instruction can never be observed by another RISC-V hart before the LR instruction that established the reservation.

Assembly: sctrclr sctrclr

§

SD = 526

Store doubleword

Store 64 bits of data from register rs2 to an address formed by adding rs1 to a signed offset.

§Forms

Assembly: sd xs2, imm(xs1)

§

RISC-V sext.w instruction.

§Forms

Assembly: sext.w rd rs1

§

SFENCEINVALIR = 531

Order implicit page table reads after invalidation

The sfence.inval.ir instruction guarantees that any previous sinval.vma instructions executed by the current hart are ordered before subsequent implicit references by that hart to the memory-management data structures.

§Forms

Assembly: sfence.inval.ir ""

§

SFENCEVMA = 532

Supervisor memory-management fence

The supervisor memory-management fence instruction SFENCE.VMA is used to synchronize updates to in-memory memory-management data structures with current execution. Instruction execution causes implicit reads and writes to these data structures; however, these implicit references are ordinarily not ordered with respect to explicit loads and stores. Executing an SFENCE.VMA instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before certain implicit references by subsequent instructions in that hart to the memory-management data structures. The specific set of operations ordered by SFENCE.VMA is determined by rs1 and rs2, as described below. SFENCE.VMA is also used to invalidate entries in the address-translation cache associated with a hart (see <<sv32algorithm>>). Further details on the behavior of this instruction are described in <<virt-control>> and <<pmp-vmem>>.

§[NOTE]

SFENCE.VMA orders only the local hart’s implicit references to the memory-management data structures.

§[NOTE]

§Consequently, other harts must be notified separately when the memory-management data structures have been modified. One approach is to use 1) a local data fence to ensure local writes are visible globally, then 2) an interprocessor interrupt to the other thread, then 3) a local SFENCE.VMA in the interrupt handler of the remote thread, and finally 4) signal back to originating thread that operation is complete. This is, of course, the RISC-V analog to a TLB shootdown.

For the common case that the translation data structures have only been modified for a single address mapping (i.e., one page or superpage), rs1 can specify a virtual address within that mapping to effect a translation fence for that mapping only. Furthermore, for the common case that the translation data structures have only been modified for a single address-space identifier, rs2 can specify the address space. The behavior of SFENCE.VMA depends on rs1 and rs2 as follows:

If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. The fence also invalidates all address-translation cache entries, for all address spaces.
If rs1=x0 and rs2≠x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see <<translation>>) are not ordered. The fence also invalidates all address-translation cache entries matching the address space identified by integer register rs2, except for entries containing global mappings.
If rs1≠x0 and rs2=x0, the fence orders only reads and writes made to leaf page table entries corresponding to the virtual address in rs1, for all address spaces. The fence also invalidates all address-translation cache entries that contain leaf page table entries corresponding to the virtual address in rs1, for all address spaces.
If rs1≠x0 and rs2≠x0, the fence orders only reads and writes made to leaf page table entries corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. The fence also invalidates all address-translation cache entries that contain leaf page table entries corresponding to the virtual address in rs1 and that match the address space identified by integer register rs2, except for entries containing global mappings.

§

SFENCEWINVAL = 533

Order writes before sfence

The sfence.w.inval instruction guarantees that any previous stores already visible to the current RISC-V hart are ordered before subsequent sinval.vma instructions executed by the same hart.

§Forms

Assembly: sfence.w.inval ""

§

Shift left unsigned word (Immediate)

Set on less than immediate unsigned

Places the value 1 in register rd if register rs1 is less than the sign-extended immediate when both are treated as unsigned numbers (i.e., the immediate is first sign-extended to XLEN bits then treated as an unsigned number), else 0 is written to rd.

NOTE: sltiu rd, rs1, 1 sets rd to 1 if rs1 equals zero, otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs).

§Forms

Assembly: sltiu xd, xs1, imm

§

SLTU = 566

Set on less than unsigned

Supervisor Exception Return

Returns from an exception.

When sret is allowed to execute, its behavior depends on whether or not the current privilege mode is virtualized.

When the current privilege mode is (H)S-mode or M-mode

sret sets hstatus.HPV = 0, mstatus.SPP = 0, mstatus.SIE = mstatus.SPIE, and mstatus.SPIE = 1, changes the privilege mode according to the table below, and then jumps to the address in sepc.

.Next privilege mode following an sret in (H)S-mode or M-mode [%autowidth] |=== | [.rotate]#mstatus.SPP# | [.rotate]#hstatus.SPV# .>| Mode after sret

| 0 | 0 | U-mode | 0 | 1 | VU-mode | 1 | 0 | (H)S-mode | 1 | 1 | VS-mode |===

When the current privilege mode is VS-mode

sret sets vsstatus.SPP = 0, vsstatus.SIE = vstatus.SPIE, and vsstatus.SPIE = 1, changes the privilege mode according to the table below, and then jumps to the address in vsepc.

Wait for interrupt

Can causes the processor to enter a low-power state until the next interrupt occurs.

<%- if ext?(:H) -%> The behavior of wfi is affected by the mstatus.TW and hstatus.VTW bits, as summarized below.

6+| Trap (I) - Trap with Illegal Instruction code + Trap (V) - Trap with Virtual Instruction code |===

<%- else -%> The wfi instruction is also affected by mstatus.TW, as shown below:

3+| Trap (I) - Trap with Illegal Instruction code |===

<%- end -%>

When wfi is marked as causing a trap above, the implementation is allowed to wait for an unspecified period of time to see if an interrupt occurs before raising the trap. That period of time can be zero (i.e., wfi always causes a trap in the cases identified above).

§Forms

Assembly: wfi ""

§

WRSNTO = 1027

RISC-V wrs.nto instruction.

§Forms

Assembly: wrs.nto wrs_nto

§

Invalid = 1039

Implementations§

Source §

impl Opcode

Source

pub fn inst_info(self) -> &'static InstInfo

Returns the effects database entry for this opcode.

Performs copy-assignment from source. Read more

Source §

impl Copy for Opcode

Source §

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=. Read more

Source §

impl StructuralPartialEq for Opcode

impl<T, U> Into for T
where U: From<T>,

Source §

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

Source §

impl<T> ToOwned for T
where T: Clone,

Source §

type Owned = T

The resulting type after obtaining ownership.

Variants§

ADD = 0

§Forms

ADDUW = 1

§Forms

ADDI = 2

§Forms

ADDIW = 3

§Forms

ADDW = 4

§Forms

AES32DSI = 5

§Forms

AES32DSMI = 6

§Forms

AES32ESI = 7

§Forms

AES32ESMI = 8

§Forms

AES64DS = 9

§Forms

AES64DSM = 10

§Forms

AES64ES = 11

§Forms

AES64ESM = 12

§Forms

AES64IM = 13

§Forms

AES64KS1I = 14

§Forms

AES64KS2 = 15

§Forms

AMOADDB = 16

§Forms

AMOADDD = 17

§Forms

AMOADDH = 18

§Forms

AMOADDW = 19

§Forms

AMOANDB = 20

§Forms

AMOANDD = 21

§Forms

AMOANDH = 22

§Forms

AMOANDW = 23

§Forms

AMOCASB = 24

§Forms

AMOCASD = 25

§Forms

AMOCASH = 26

§Forms

AMOCASQ = 27

§Forms

AMOCASW = 28

§Forms

AMOMAXB = 29

§Forms

AMOMAXD = 30

§Forms

AMOMAXH = 31

§Forms

AMOMAXW = 32

§Forms

AMOMAXUB = 33

§Forms

AMOMAXUD = 34

§Forms

AMOMAXUH = 35

§Forms

AMOMAXUW = 36

§Forms

AMOMINB = 37

§Forms

AMOMIND = 38

§Forms

Enum Opcode