pub enum Operand {
Show 13 variants
Missing,
Register(Register),
Immediate(i128),
Memory(Box<MemoryOperand>),
Label(String),
Expression(Expr),
RegisterList(Vec<Register>),
LiteralPoolValue(i128),
VectorRegister(Register, VectorArrangement),
SvePredicate(Register, SvePredQual),
VectorElement(Register, ElementSize, u8),
PsrField(PsrField),
Shift(ShiftOp, ShiftAmount),
}Expand description
A resolved or unresolved operand.
Variants§
Missing
No operand.
Fills the unused slots of an OperandList, and is what indexing past
the end of one yields. Operand counts come from parsed input, so an
encoder that indexes further than the instruction actually goes must
produce a diagnostic rather than panic — every operand-extraction
helper rejects this variant, so the error falls out naturally.
Register(Register)
A register operand.
Immediate(i128)
An immediate value.
Memory(Box<MemoryOperand>)
A memory (indirect) operand.
Label(String)
A label reference (resolved later).
Expression(Expr)
An expression (e.g., label + 4).
RegisterList(Vec<Register>)
A register list (ARM {R0, R1, R4, LR}).
LiteralPoolValue(i128)
A literal pool value (LDR Xn, =0x1234).
The assembler will place the constant in a nearby literal pool
and emit a PC-relative LDR to load it.
VectorRegister(Register, VectorArrangement)
A vector register with arrangement specifier (AArch64 NEON/SVE).
E.g., V0.4S, V1.16B, Z0.S, Z1.D.
SvePredicate(Register, SvePredQual)
SVE predicate register with qualifier (P0/M, P0/Z).
VectorElement(Register, ElementSize, u8)
A single lane of an AArch64 vector register: V0.S[0].
Element accesses name one lane rather than an arrangement, so they
carry an element size plus an index instead of a
VectorArrangement.
PsrField(PsrField)
An ARM32 program status register with a field selector
(cpsr_f, spsr_cxsf, …), as used by MSR and MRS.
Shift(ShiftOp, ShiftAmount)
A barrel-shift or register-extend modifier applied to the preceding operand (ARM32, Thumb, AArch64).
UAL writes these as a trailing operand — add x0, x1, x2, lsl #3 is
four operands, the last being lsl #3 — so they are modelled the same
way rather than being folded into the register operand. That keeps the
IR shaped like the source and lets a shift attach to an immediate
(movz x0, #0x5678, lsl #16) as naturally as to a register.