pub enum VectorArrangement {
B8,
B16,
H4,
H8,
S2,
S4,
D1,
D2,
SveB,
SveH,
SveS,
SveD,
}Expand description
AArch64 vector arrangement specifier.
Describes how a 128-bit (or 64-bit) SIMD register is divided into lanes.
Used with NEON/ASIMD instructions like ADD V0.4S, V1.4S, V2.4S.
Variants§
B8
8 bytes (64-bit: 8×B)
B16
16 bytes (128-bit: 16×B)
H4
4 half-words (64-bit: 4×H)
H8
8 half-words (128-bit: 8×H)
S2
2 single-words (64-bit: 2×S)
S4
4 single-words (128-bit: 4×S)
D1
1 double-word (64-bit: 1×D)
D2
2 double-words (128-bit: 2×D)
SveB
SVE byte elements (.B).
SveH
SVE half-word elements (.H).
SveS
SVE single-word elements (.S).
SveD
SVE double-word elements (.D).
Implementations§
Source§impl VectorArrangement
impl VectorArrangement
Sourcepub fn parse(s: &str) -> Option<Self>
pub fn parse(s: &str) -> Option<Self>
Parse a vector arrangement specifier string (e.g., “8b”, “16b”, “4h”). Case-insensitive, zero heap allocations.
Sourcepub fn element_bits(self) -> u32
pub fn element_bits(self) -> u32
Lane element size in bits.
Sourcepub fn total_bits(self) -> u32
pub fn total_bits(self) -> u32
Total vector width in bits (64 or 128 for NEON, 0 for SVE scalable).
Sourcepub fn lane_count(self) -> u32
pub fn lane_count(self) -> u32
Number of lanes (0 for SVE scalable arrangements).
Trait Implementations§
Source§impl Clone for VectorArrangement
impl Clone for VectorArrangement
Source§fn clone(&self) -> VectorArrangement
fn clone(&self) -> VectorArrangement
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more