[−][src]Module ambiq_apollo3p_pac::iom0
IO Peripheral Master
Modules
clkcfg | I/O Clock Configuration |
cmd | Command and Offset |
cmdstat | Command status |
cqaddr | CQ Target Read Address |
cqcfg | Command Queue Configuration |
cqcuridx | IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue |
cqendidx | IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue |
cqflags | Command Queue Flag |
cqpauseen | Command Queue Pause Enable |
cqsetclear | Command Queue Flag Set/Clear |
cqstat | Command Queue Status |
dcx | DCX Control |
devcfg | I2C Device Configuration register |
dmacfg | DMA Configuration |
dmastat | DMA Status |
dmatargaddr | DMA Target Address |
dmatotcount | DMA Total Transfer Count |
dmatrigen | DMA Trigger Enable |
dmatrigstat | DMA Trigger Status |
fifo | FIFO Access Port |
fifoctrl | FIFO Control |
fifoloc | FIFO Pointers |
fifopop | FIFO POP register |
fifoptr | FIFO size and remaining slots open values |
fifopush | FIFO PUSH register |
fifothr | FIFO Threshold Configuration |
intclr | IO Master Interrupts: Clear |
inten | IO Master Interrupts: Enable |
intset | IO Master Interrupts: Set |
intstat | IO Master Interrupts: Status |
iomdbg | IOM Debug |
mi2ccfg | I2C Master configuration |
mspicfg | SPI module master configuration |
offsethi | High order 2 bytes of 3 byte offset for IO transaction |
status | IOM Module Status |
submodctrl | Submodule control |
Structs
RegisterBlock | Register block |
Type Definitions
CLKCFG | I/O Clock Configuration |
CMD | Command and Offset |
CMDSTAT | Command status |
CQADDR | CQ Target Read Address |
CQCFG | Command Queue Configuration |
CQCURIDX | IOM Command Queue current index value . Compared to the CQENDIDX reg contents to generate the IDXEQ Pause event for command queue |
CQENDIDX | IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate the IDXEQ Pause event for command queue |
CQFLAGS | Command Queue Flag |
CQPAUSEEN | Command Queue Pause Enable |
CQSETCLEAR | Command Queue Flag Set/Clear |
CQSTAT | Command Queue Status |
DCX | DCX Control |
DEVCFG | I2C Device Configuration register |
DMACFG | DMA Configuration |
DMASTAT | DMA Status |
DMATARGADDR | DMA Target Address |
DMATOTCOUNT | DMA Total Transfer Count |
DMATRIGEN | DMA Trigger Enable |
DMATRIGSTAT | DMA Trigger Status |
FIFO | FIFO Access Port |
FIFOCTRL | FIFO Control |
FIFOLOC | FIFO Pointers |
FIFOPOP | FIFO POP register |
FIFOPTR | FIFO size and remaining slots open values |
FIFOPUSH | FIFO PUSH register |
FIFOTHR | FIFO Threshold Configuration |
INTCLR | IO Master Interrupts: Clear |
INTEN | IO Master Interrupts: Enable |
INTSET | IO Master Interrupts: Set |
INTSTAT | IO Master Interrupts: Status |
IOMDBG | IOM Debug |
MI2CCFG | I2C Master configuration |
MSPICFG | SPI module master configuration |
OFFSETHI | High order 2 bytes of 3 byte offset for IO transaction |
STATUS | IOM Module Status |
SUBMODCTRL | Submodule control |