[−][src]Module ambiq_apollo3p_pac::iom0::mi2ccfg

I2C Master configuration

Structs

ADDRSZ_W	Write proxy for field `ADDRSZ`
ARBEN_W	Write proxy for field `ARBEN`
I2CLSB_W	Write proxy for field `I2CLSB`
MI2CRST_W	Write proxy for field `MI2CRST`
SCLENDLY_W	Write proxy for field `SCLENDLY`
SDADLY_W	Write proxy for field `SDADLY`
SDAENDLY_W	Write proxy for field `SDAENDLY`
SMPCNT_W	Write proxy for field `SMPCNT`
STRDIS_W	Write proxy for field `STRDIS`

ADDRSZ_A	Sets the I2C master device address size to either 7 bits (0) or 10 bits (1).
ARBEN_A	Enables multi-master arbitration for the I2C master. If the bus is known to have only a single master, this function can be disabled to save clock cycles on I2C transactions
I2CLSB_A	Direction of data transmit and receive, MSB(0) or LSB(1) first. Default per I2C specification is MSB first. This applies to both read and write data, and read data will be bit