[−][src]Module ambiq_apollo3p_pac::iom0::mspicfg

SPI module master configuration

Structs

DINDLY_W	Write proxy for field `DINDLY`
DOUTDLY_W	Write proxy for field `DOUTDLY`
FULLDUP_W	Write proxy for field `FULLDUP`
MOSIINV_W	Write proxy for field `MOSIINV`
MSPIRST_W	Write proxy for field `MSPIRST`
RDFCPOL_W	Write proxy for field `RDFCPOL`
RDFC_W	Write proxy for field `RDFC`
SPHA_W	Write proxy for field `SPHA`
SPILSB_W	Write proxy for field `SPILSB`
SPOL_W	Write proxy for field `SPOL`
WTFCIRQ_W	Write proxy for field `WTFCIRQ`
WTFCPOL_W	Write proxy for field `WTFCPOL`
WTFC_W	Write proxy for field `WTFC`

MOSIINV_A	inverts MOSI when flow control is enabled.
RDFCPOL_A	selects the read flow control signal polarity.
RDFC_A	enables read mode flow control.
SPHA_A	selects SPI phase.
SPILSB_A	Selects data transfer as MSB first (0) or LSB first (1) for the data portion of the SPI transaction. The offset bytes are always transmitted MSB first.
SPOL_A	selects SPI polarity.
WTFCIRQ_A	selects the write mode flow control signal.
WTFCPOL_A	selects the write flow control signal polarity. The transfers are halted when the selected flow control signal is OPPOSITE polarity of bit. (For example: WTFCPOL = 0 will allow a IRQ=1 to pause transfers).
WTFC_A	enables write mode flow control.