pub type W = W<u32, CTRL>;Expand description
Writer for register CTRL
Aliased Type§
pub struct W { /* private fields */ }Implementations§
Source§impl W
impl W
Sourcepub fn flash1_slm_enable(&mut self) -> FLASH1_SLM_ENABLE_W<'_>
pub fn flash1_slm_enable(&mut self) -> FLASH1_SLM_ENABLE_W<'_>
Bit 10 - Enable Flash Sleep Mode. After writing this bit, the flash instance 1 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time.
Sourcepub fn flash1_slm_disable(&mut self) -> FLASH1_SLM_DISABLE_W<'_>
pub fn flash1_slm_disable(&mut self) -> FLASH1_SLM_DISABLE_W<'_>
Bit 9 - Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array.
Sourcepub fn flash1_slm_status(&mut self) -> FLASH1_SLM_STATUS_W<'_>
pub fn flash1_slm_status(&mut self) -> FLASH1_SLM_STATUS_W<'_>
Bit 8 - Flash Sleep Mode Status. When 1, flash instance 1 is asleep.
Sourcepub fn flash0_slm_enable(&mut self) -> FLASH0_SLM_ENABLE_W<'_>
pub fn flash0_slm_enable(&mut self) -> FLASH0_SLM_ENABLE_W<'_>
Bit 6 - Enable Flash Sleep Mode. After writing this bit, the flash instance 0 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time.
Sourcepub fn flash0_slm_disable(&mut self) -> FLASH0_SLM_DISABLE_W<'_>
pub fn flash0_slm_disable(&mut self) -> FLASH0_SLM_DISABLE_W<'_>
Bit 5 - Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array.
Sourcepub fn flash0_slm_status(&mut self) -> FLASH0_SLM_STATUS_W<'_>
pub fn flash0_slm_status(&mut self) -> FLASH0_SLM_STATUS_W<'_>
Bit 4 - Flash Sleep Mode Status. When 1, flash instance 0 is asleep.
Sourcepub fn cache_ready(&mut self) -> CACHE_READY_W<'_>
pub fn cache_ready(&mut self) -> CACHE_READY_W<'_>
Bit 2 - Cache Ready Status. A value of 1 indicates the cache is enabled and not processing an invalidate operation.
Sourcepub fn reset_stat(&mut self) -> RESET_STAT_W<'_>
pub fn reset_stat(&mut self) -> RESET_STAT_W<'_>
Bit 1 - Writing a 1 to this bitfield will reset the cache monitor statistics (DMON0-3, IMON0-3). Statistic gathering can be paused/stopped by disabling the MONITOR_ENABLE bit in CACHECFG, which will maintain the count values until the stats are reset by writing this bitfield.
Sourcepub fn invalidate(&mut self) -> INVALIDATE_W<'_>
pub fn invalidate(&mut self) -> INVALIDATE_W<'_>
Bit 0 - Writing a 1 to this bitfield invalidates the flash cache contents.