ambiq_apollo2_pac/cachectrl/
ctrl.rs

1#[doc = "Reader of register CTRL"]
2pub type R = crate::R<u32, super::CTRL>;
3#[doc = "Writer for register CTRL"]
4pub type W = crate::W<u32, super::CTRL>;
5#[doc = "Register CTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::CTRL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `FLASH1_SLM_ENABLE`"]
14pub type FLASH1_SLM_ENABLE_R = crate::R<bool, bool>;
15#[doc = "Write proxy for field `FLASH1_SLM_ENABLE`"]
16pub struct FLASH1_SLM_ENABLE_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> FLASH1_SLM_ENABLE_W<'a> {
20    #[doc = r"Sets the field bit"]
21    #[inline(always)]
22    pub fn set_bit(self) -> &'a mut W {
23        self.bit(true)
24    }
25    #[doc = r"Clears the field bit"]
26    #[inline(always)]
27    pub fn clear_bit(self) -> &'a mut W {
28        self.bit(false)
29    }
30    #[doc = r"Writes raw bits to the field"]
31    #[inline(always)]
32    pub fn bit(self, value: bool) -> &'a mut W {
33        self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
34        self.w
35    }
36}
37#[doc = "Reader of field `FLASH1_SLM_DISABLE`"]
38pub type FLASH1_SLM_DISABLE_R = crate::R<bool, bool>;
39#[doc = "Write proxy for field `FLASH1_SLM_DISABLE`"]
40pub struct FLASH1_SLM_DISABLE_W<'a> {
41    w: &'a mut W,
42}
43impl<'a> FLASH1_SLM_DISABLE_W<'a> {
44    #[doc = r"Sets the field bit"]
45    #[inline(always)]
46    pub fn set_bit(self) -> &'a mut W {
47        self.bit(true)
48    }
49    #[doc = r"Clears the field bit"]
50    #[inline(always)]
51    pub fn clear_bit(self) -> &'a mut W {
52        self.bit(false)
53    }
54    #[doc = r"Writes raw bits to the field"]
55    #[inline(always)]
56    pub fn bit(self, value: bool) -> &'a mut W {
57        self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
58        self.w
59    }
60}
61#[doc = "Reader of field `FLASH1_SLM_STATUS`"]
62pub type FLASH1_SLM_STATUS_R = crate::R<bool, bool>;
63#[doc = "Write proxy for field `FLASH1_SLM_STATUS`"]
64pub struct FLASH1_SLM_STATUS_W<'a> {
65    w: &'a mut W,
66}
67impl<'a> FLASH1_SLM_STATUS_W<'a> {
68    #[doc = r"Sets the field bit"]
69    #[inline(always)]
70    pub fn set_bit(self) -> &'a mut W {
71        self.bit(true)
72    }
73    #[doc = r"Clears the field bit"]
74    #[inline(always)]
75    pub fn clear_bit(self) -> &'a mut W {
76        self.bit(false)
77    }
78    #[doc = r"Writes raw bits to the field"]
79    #[inline(always)]
80    pub fn bit(self, value: bool) -> &'a mut W {
81        self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
82        self.w
83    }
84}
85#[doc = "Reader of field `FLASH0_SLM_ENABLE`"]
86pub type FLASH0_SLM_ENABLE_R = crate::R<bool, bool>;
87#[doc = "Write proxy for field `FLASH0_SLM_ENABLE`"]
88pub struct FLASH0_SLM_ENABLE_W<'a> {
89    w: &'a mut W,
90}
91impl<'a> FLASH0_SLM_ENABLE_W<'a> {
92    #[doc = r"Sets the field bit"]
93    #[inline(always)]
94    pub fn set_bit(self) -> &'a mut W {
95        self.bit(true)
96    }
97    #[doc = r"Clears the field bit"]
98    #[inline(always)]
99    pub fn clear_bit(self) -> &'a mut W {
100        self.bit(false)
101    }
102    #[doc = r"Writes raw bits to the field"]
103    #[inline(always)]
104    pub fn bit(self, value: bool) -> &'a mut W {
105        self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
106        self.w
107    }
108}
109#[doc = "Reader of field `FLASH0_SLM_DISABLE`"]
110pub type FLASH0_SLM_DISABLE_R = crate::R<bool, bool>;
111#[doc = "Write proxy for field `FLASH0_SLM_DISABLE`"]
112pub struct FLASH0_SLM_DISABLE_W<'a> {
113    w: &'a mut W,
114}
115impl<'a> FLASH0_SLM_DISABLE_W<'a> {
116    #[doc = r"Sets the field bit"]
117    #[inline(always)]
118    pub fn set_bit(self) -> &'a mut W {
119        self.bit(true)
120    }
121    #[doc = r"Clears the field bit"]
122    #[inline(always)]
123    pub fn clear_bit(self) -> &'a mut W {
124        self.bit(false)
125    }
126    #[doc = r"Writes raw bits to the field"]
127    #[inline(always)]
128    pub fn bit(self, value: bool) -> &'a mut W {
129        self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
130        self.w
131    }
132}
133#[doc = "Reader of field `FLASH0_SLM_STATUS`"]
134pub type FLASH0_SLM_STATUS_R = crate::R<bool, bool>;
135#[doc = "Write proxy for field `FLASH0_SLM_STATUS`"]
136pub struct FLASH0_SLM_STATUS_W<'a> {
137    w: &'a mut W,
138}
139impl<'a> FLASH0_SLM_STATUS_W<'a> {
140    #[doc = r"Sets the field bit"]
141    #[inline(always)]
142    pub fn set_bit(self) -> &'a mut W {
143        self.bit(true)
144    }
145    #[doc = r"Clears the field bit"]
146    #[inline(always)]
147    pub fn clear_bit(self) -> &'a mut W {
148        self.bit(false)
149    }
150    #[doc = r"Writes raw bits to the field"]
151    #[inline(always)]
152    pub fn bit(self, value: bool) -> &'a mut W {
153        self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
154        self.w
155    }
156}
157#[doc = "Reader of field `CACHE_READY`"]
158pub type CACHE_READY_R = crate::R<bool, bool>;
159#[doc = "Write proxy for field `CACHE_READY`"]
160pub struct CACHE_READY_W<'a> {
161    w: &'a mut W,
162}
163impl<'a> CACHE_READY_W<'a> {
164    #[doc = r"Sets the field bit"]
165    #[inline(always)]
166    pub fn set_bit(self) -> &'a mut W {
167        self.bit(true)
168    }
169    #[doc = r"Clears the field bit"]
170    #[inline(always)]
171    pub fn clear_bit(self) -> &'a mut W {
172        self.bit(false)
173    }
174    #[doc = r"Writes raw bits to the field"]
175    #[inline(always)]
176    pub fn bit(self, value: bool) -> &'a mut W {
177        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
178        self.w
179    }
180}
181#[doc = "Writing a 1 to this bitfield will reset the cache monitor statistics (DMON0-3, IMON0-3). Statistic gathering can be paused/stopped by disabling the MONITOR_ENABLE bit in CACHECFG, which will maintain the count values until the stats are reset by writing this bitfield.\n\nValue on reset: 0"]
182#[derive(Clone, Copy, Debug, PartialEq)]
183pub enum RESET_STAT_A {
184    #[doc = "1: Clear Cache Stats"]
185    CLEAR = 1,
186}
187impl From<RESET_STAT_A> for bool {
188    #[inline(always)]
189    fn from(variant: RESET_STAT_A) -> Self {
190        variant as u8 != 0
191    }
192}
193#[doc = "Reader of field `RESET_STAT`"]
194pub type RESET_STAT_R = crate::R<bool, RESET_STAT_A>;
195impl RESET_STAT_R {
196    #[doc = r"Get enumerated values variant"]
197    #[inline(always)]
198    pub fn variant(&self) -> crate::Variant<bool, RESET_STAT_A> {
199        use crate::Variant::*;
200        match self.bits {
201            true => Val(RESET_STAT_A::CLEAR),
202            i => Res(i),
203        }
204    }
205    #[doc = "Checks if the value of the field is `CLEAR`"]
206    #[inline(always)]
207    pub fn is_clear(&self) -> bool {
208        *self == RESET_STAT_A::CLEAR
209    }
210}
211#[doc = "Write proxy for field `RESET_STAT`"]
212pub struct RESET_STAT_W<'a> {
213    w: &'a mut W,
214}
215impl<'a> RESET_STAT_W<'a> {
216    #[doc = r"Writes `variant` to the field"]
217    #[inline(always)]
218    pub fn variant(self, variant: RESET_STAT_A) -> &'a mut W {
219        {
220            self.bit(variant.into())
221        }
222    }
223    #[doc = "Clear Cache Stats"]
224    #[inline(always)]
225    pub fn clear(self) -> &'a mut W {
226        self.variant(RESET_STAT_A::CLEAR)
227    }
228    #[doc = r"Sets the field bit"]
229    #[inline(always)]
230    pub fn set_bit(self) -> &'a mut W {
231        self.bit(true)
232    }
233    #[doc = r"Clears the field bit"]
234    #[inline(always)]
235    pub fn clear_bit(self) -> &'a mut W {
236        self.bit(false)
237    }
238    #[doc = r"Writes raw bits to the field"]
239    #[inline(always)]
240    pub fn bit(self, value: bool) -> &'a mut W {
241        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
242        self.w
243    }
244}
245#[doc = "Writing a 1 to this bitfield invalidates the flash cache contents.\n\nValue on reset: 0"]
246#[derive(Clone, Copy, Debug, PartialEq)]
247pub enum INVALIDATE_A {
248    #[doc = "1: Initiate a programming operation to flash info."]
249    GO = 1,
250}
251impl From<INVALIDATE_A> for bool {
252    #[inline(always)]
253    fn from(variant: INVALIDATE_A) -> Self {
254        variant as u8 != 0
255    }
256}
257#[doc = "Reader of field `INVALIDATE`"]
258pub type INVALIDATE_R = crate::R<bool, INVALIDATE_A>;
259impl INVALIDATE_R {
260    #[doc = r"Get enumerated values variant"]
261    #[inline(always)]
262    pub fn variant(&self) -> crate::Variant<bool, INVALIDATE_A> {
263        use crate::Variant::*;
264        match self.bits {
265            true => Val(INVALIDATE_A::GO),
266            i => Res(i),
267        }
268    }
269    #[doc = "Checks if the value of the field is `GO`"]
270    #[inline(always)]
271    pub fn is_go(&self) -> bool {
272        *self == INVALIDATE_A::GO
273    }
274}
275#[doc = "Write proxy for field `INVALIDATE`"]
276pub struct INVALIDATE_W<'a> {
277    w: &'a mut W,
278}
279impl<'a> INVALIDATE_W<'a> {
280    #[doc = r"Writes `variant` to the field"]
281    #[inline(always)]
282    pub fn variant(self, variant: INVALIDATE_A) -> &'a mut W {
283        {
284            self.bit(variant.into())
285        }
286    }
287    #[doc = "Initiate a programming operation to flash info."]
288    #[inline(always)]
289    pub fn go(self) -> &'a mut W {
290        self.variant(INVALIDATE_A::GO)
291    }
292    #[doc = r"Sets the field bit"]
293    #[inline(always)]
294    pub fn set_bit(self) -> &'a mut W {
295        self.bit(true)
296    }
297    #[doc = r"Clears the field bit"]
298    #[inline(always)]
299    pub fn clear_bit(self) -> &'a mut W {
300        self.bit(false)
301    }
302    #[doc = r"Writes raw bits to the field"]
303    #[inline(always)]
304    pub fn bit(self, value: bool) -> &'a mut W {
305        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
306        self.w
307    }
308}
309impl R {
310    #[doc = "Bit 10 - Enable Flash Sleep Mode. After writing this bit, the flash instance 1 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time."]
311    #[inline(always)]
312    pub fn flash1_slm_enable(&self) -> FLASH1_SLM_ENABLE_R {
313        FLASH1_SLM_ENABLE_R::new(((self.bits >> 10) & 0x01) != 0)
314    }
315    #[doc = "Bit 9 - Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array."]
316    #[inline(always)]
317    pub fn flash1_slm_disable(&self) -> FLASH1_SLM_DISABLE_R {
318        FLASH1_SLM_DISABLE_R::new(((self.bits >> 9) & 0x01) != 0)
319    }
320    #[doc = "Bit 8 - Flash Sleep Mode Status. When 1, flash instance 1 is asleep."]
321    #[inline(always)]
322    pub fn flash1_slm_status(&self) -> FLASH1_SLM_STATUS_R {
323        FLASH1_SLM_STATUS_R::new(((self.bits >> 8) & 0x01) != 0)
324    }
325    #[doc = "Bit 6 - Enable Flash Sleep Mode. After writing this bit, the flash instance 0 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time."]
326    #[inline(always)]
327    pub fn flash0_slm_enable(&self) -> FLASH0_SLM_ENABLE_R {
328        FLASH0_SLM_ENABLE_R::new(((self.bits >> 6) & 0x01) != 0)
329    }
330    #[doc = "Bit 5 - Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array."]
331    #[inline(always)]
332    pub fn flash0_slm_disable(&self) -> FLASH0_SLM_DISABLE_R {
333        FLASH0_SLM_DISABLE_R::new(((self.bits >> 5) & 0x01) != 0)
334    }
335    #[doc = "Bit 4 - Flash Sleep Mode Status. When 1, flash instance 0 is asleep."]
336    #[inline(always)]
337    pub fn flash0_slm_status(&self) -> FLASH0_SLM_STATUS_R {
338        FLASH0_SLM_STATUS_R::new(((self.bits >> 4) & 0x01) != 0)
339    }
340    #[doc = "Bit 2 - Cache Ready Status. A value of 1 indicates the cache is enabled and not processing an invalidate operation."]
341    #[inline(always)]
342    pub fn cache_ready(&self) -> CACHE_READY_R {
343        CACHE_READY_R::new(((self.bits >> 2) & 0x01) != 0)
344    }
345    #[doc = "Bit 1 - Writing a 1 to this bitfield will reset the cache monitor statistics (DMON0-3, IMON0-3). Statistic gathering can be paused/stopped by disabling the MONITOR_ENABLE bit in CACHECFG, which will maintain the count values until the stats are reset by writing this bitfield."]
346    #[inline(always)]
347    pub fn reset_stat(&self) -> RESET_STAT_R {
348        RESET_STAT_R::new(((self.bits >> 1) & 0x01) != 0)
349    }
350    #[doc = "Bit 0 - Writing a 1 to this bitfield invalidates the flash cache contents."]
351    #[inline(always)]
352    pub fn invalidate(&self) -> INVALIDATE_R {
353        INVALIDATE_R::new((self.bits & 0x01) != 0)
354    }
355}
356impl W {
357    #[doc = "Bit 10 - Enable Flash Sleep Mode. After writing this bit, the flash instance 1 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time."]
358    #[inline(always)]
359    pub fn flash1_slm_enable(&mut self) -> FLASH1_SLM_ENABLE_W {
360        FLASH1_SLM_ENABLE_W { w: self }
361    }
362    #[doc = "Bit 9 - Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array."]
363    #[inline(always)]
364    pub fn flash1_slm_disable(&mut self) -> FLASH1_SLM_DISABLE_W {
365        FLASH1_SLM_DISABLE_W { w: self }
366    }
367    #[doc = "Bit 8 - Flash Sleep Mode Status. When 1, flash instance 1 is asleep."]
368    #[inline(always)]
369    pub fn flash1_slm_status(&mut self) -> FLASH1_SLM_STATUS_W {
370        FLASH1_SLM_STATUS_W { w: self }
371    }
372    #[doc = "Bit 6 - Enable Flash Sleep Mode. After writing this bit, the flash instance 0 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time."]
373    #[inline(always)]
374    pub fn flash0_slm_enable(&mut self) -> FLASH0_SLM_ENABLE_W {
375        FLASH0_SLM_ENABLE_W { w: self }
376    }
377    #[doc = "Bit 5 - Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array."]
378    #[inline(always)]
379    pub fn flash0_slm_disable(&mut self) -> FLASH0_SLM_DISABLE_W {
380        FLASH0_SLM_DISABLE_W { w: self }
381    }
382    #[doc = "Bit 4 - Flash Sleep Mode Status. When 1, flash instance 0 is asleep."]
383    #[inline(always)]
384    pub fn flash0_slm_status(&mut self) -> FLASH0_SLM_STATUS_W {
385        FLASH0_SLM_STATUS_W { w: self }
386    }
387    #[doc = "Bit 2 - Cache Ready Status. A value of 1 indicates the cache is enabled and not processing an invalidate operation."]
388    #[inline(always)]
389    pub fn cache_ready(&mut self) -> CACHE_READY_W {
390        CACHE_READY_W { w: self }
391    }
392    #[doc = "Bit 1 - Writing a 1 to this bitfield will reset the cache monitor statistics (DMON0-3, IMON0-3). Statistic gathering can be paused/stopped by disabling the MONITOR_ENABLE bit in CACHECFG, which will maintain the count values until the stats are reset by writing this bitfield."]
393    #[inline(always)]
394    pub fn reset_stat(&mut self) -> RESET_STAT_W {
395        RESET_STAT_W { w: self }
396    }
397    #[doc = "Bit 0 - Writing a 1 to this bitfield invalidates the flash cache contents."]
398    #[inline(always)]
399    pub fn invalidate(&mut self) -> INVALIDATE_W {
400        INVALIDATE_W { w: self }
401    }
402}
ambiq_apollo2_pac/cachectrl/ctrl.rs

ambiq_apollo2_pac/cachectrl/
ctrl.rs
