Type Alias R 

pub type R = R<u32, CTRL>;

Reader of register CTRL

Aliased Type

pub struct R { /* private fields */ }

Implementations

impl R

pub fn flash1_slm_enable(&self) -> FLASH1_SLM_ENABLE_R

Bit 10 - Enable Flash Sleep Mode. After writing this bit, the flash instance 1 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time.

pub fn flash1_slm_disable(&self) -> FLASH1_SLM_DISABLE_R

Bit 9 - Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array.

pub fn flash1_slm_status(&self) -> FLASH1_SLM_STATUS_R

Bit 8 - Flash Sleep Mode Status. When 1, flash instance 1 is asleep.

pub fn flash0_slm_enable(&self) -> FLASH0_SLM_ENABLE_R

Bit 6 - Enable Flash Sleep Mode. After writing this bit, the flash instance 0 will enter a low-power mode until the CPU writes the SLM_DISABLE bit or a flash access occurs. Wake from SLM requires ~5us, so this should only be set if the flash will not be accessed for reasonably long time.

pub fn flash0_slm_disable(&self) -> FLASH0_SLM_DISABLE_R

Bit 5 - Disable Flash Sleep Mode. Allows CPU to manually disable SLM mode. Performing a flash read will also wake the array.

pub fn flash0_slm_status(&self) -> FLASH0_SLM_STATUS_R

Bit 4 - Flash Sleep Mode Status. When 1, flash instance 0 is asleep.

pub fn cache_ready(&self) -> CACHE_READY_R

Bit 2 - Cache Ready Status. A value of 1 indicates the cache is enabled and not processing an invalidate operation.

pub fn reset_stat(&self) -> RESET_STAT_R

Bit 1 - Writing a 1 to this bitfield will reset the cache monitor statistics (DMON0-3, IMON0-3). Statistic gathering can be paused/stopped by disabling the MONITOR_ENABLE bit in CACHECFG, which will maintain the count values until the stats are reset by writing this bitfield.

pub fn invalidate(&self) -> INVALIDATE_R

Bit 0 - Writing a 1 to this bitfield invalidates the flash cache contents.