Enum Register

Source

#[repr(u8)]pub enum Register {
Show 16 variants    AFreq8bitFinetone = 0,
    AFreq4bitRoughtone = 1,
    BFreq8bitFinetone = 2,
    BFreq4bitRoughtone = 3,
    CFreq8bitFinetone = 4,
    CFreq4bitRoughtone = 5,
    NoiseFreq5bit = 6,
    IoPortMixerSettings = 7,
    ALevel = 8,
    BLevel = 9,
    CLevel = 10,
    EFreq8bitFineAdj = 11,
    EFreq8bitRoughAdj = 12,
    EShape = 13,
    DataIoA = 14,
    DataIoB = 15,
}

Expand description

One of the 16 registers (0-15) of the YM2149 sound chip.

Used to select which register to write / read. Each register controls different aspects of tone generation, noise, mixing, amplitude, and envelope.

Check the datasheet / docs for detailed information.

Variants§

§

AFreq8bitFinetone = 0

Frequency of channel A: 8 bit fine tone adjustment

§

AFreq4bitRoughtone = 1

Frequency of channel A: 4 bit rough tone adjustment

Mask: 0x0F

§

BFreq8bitFinetone = 2

Frequency of channel B: 8 bit fine tone adjustment

§

BFreq4bitRoughtone = 3

Frequency of channel B: 4 bit rough tone adjustment

Mask: 0x0F

§

CFreq8bitFinetone = 4

Frequency of channel C: 8 bit fine tone adjustment

§

CFreq4bitRoughtone = 5

Frequency of channel C: 4 bit rough tone adjustment

Mask: 0x0F

§

NoiseFreq5bit = 6

Frequency of noise: 5 bit noise frequency

Mask: 0x1F

§

IoPortMixerSettings = 7

I/O Port and mixer settings

From the datasheet:

Sound is output when ‘0’ is written to the register.
Selection of input/output for the I/O ports is determined by bits B7 and B6 of register R7.
Input is selected when ‘0’ is written to the register bits.

Bit:	B7	B6	B5	B4	B3	B2	B1	B0
Type:	I/O	I/O	Noise	Noise	Noise	Tone	Tone	Tone
Channel:	IOB	IOA	C	B	A	C	B	A

Example:

// Enables only channel A, with IOA and IOB functioning as outputs.
use ym2149_core::{
    command::{Command, CommandOutput},
    register::Register,
    chip::YM2149
};

struct DebugWriter;

impl CommandOutput for DebugWriter {
    fn execute(&mut self, command: Command) {
        let arr = command.as_array();
        println!("Writing 0b{:08b} to register 0b{:08b}.", arr[0], arr[1]);
    }
}

let mut chip = YM2149::new(
    DebugWriter{},
    2_000_000,
).expect("Error building chip");

chip.command(
    Register::IoPortMixerSettings,
    0b11111110
);

§

ALevel = 8

§Level of channel A

Level control (formats identical for ALevel, BLevel and CLevel)

From the datasheet:

Mode M selects whether the level is fixed (when M = 0) or variable (M = 1).
When M = 0, the level is determined from one of 16 by level selection signals L3, L2, L1, and L0 which compromise the lower four bits.
When M = 1, the level is determined by the 5 bit output of E4, E3, E2, E1, and E0 of the envelope generator of the SSG.