Enum xtensa_lx_rt::exception::ExceptionCause

#[repr(C)]
pub enum ExceptionCause {
    Illegal,
    Syscall,
    InstrError,
    LoadStoreError,
    LevelOneInterrupt,
    Alloca,
    DivideByZero,
    NextPCValueIllegal,
    Privileged,
    Unaligned,
    ExternalRegisterPrivilegeError,
    ExclusiveError,
    InstrDataError,
    LoadStoreDataError,
    InstrAddrError,
    LoadStoreAddrError,
    ItlbMiss,
    ItlbMultiHit,
    InstrRing,
    Reserved19,
    InstrProhibited,
    Reserved21,
    Reserved22,
    Reserved23,
    DtlbMiss,
    DtlbMultiHit,
    LoadStoreRing,
    Reserved27,
    LoadProhibited,
    StoreProhibited,
    Reserved30,
    Reserved31,
    Cp0Disabled,
    Cp1Disabled,
    Cp2Disabled,
    Cp3Disabled,
    Cp4Disabled,
    Cp5Disabled,
    Cp6Disabled,
    Cp7Disabled,
    None,
}

EXCCAUSE register values

General Exception Causes. (Values of EXCCAUSE special register set by general exceptions, which vector to the user, kernel, or double-exception vectors).

Variants

Illegal

Illegal Instruction

Syscall

System Call (Syscall Instruction)

InstrError

Instruction Fetch Error

LoadStoreError

Load Store Error

LevelOneInterrupt

Level 1 Interrupt

Alloca

Stack Extension Assist (movsp Instruction) For Alloca

DivideByZero

Integer Divide By Zero

NextPCValueIllegal

Use Of Failed Speculative Access (Not Implemented)

Privileged

Privileged Instruction

Unaligned

Unaligned Load Or Store

ExternalRegisterPrivilegeError

Reserved

ExclusiveError

Reserved

InstrDataError

Pif Data Error On Instruction Fetch (Rb-200x And Later)

LoadStoreDataError

Pif Data Error On Load Or Store (Rb-200x And Later)

InstrAddrError

Pif Address Error On Instruction Fetch (Rb-200x And Later)

LoadStoreAddrError

Pif Address Error On Load Or Store (Rb-200x And Later)

ItlbMiss

Itlb Miss (No Itlb Entry Matches, Hw Refill Also Missed)

ItlbMultiHit

Itlb Multihit (Multiple Itlb Entries Match)

InstrRing

Ring Privilege Violation On Instruction Fetch

Reserved19

Size Restriction On Ifetch (Not Implemented)

InstrProhibited

Cache Attribute Does Not Allow Instruction Fetch

Reserved21

Reserved

Reserved22

Reserved

Reserved23

Reserved

DtlbMiss

Dtlb Miss (No Dtlb Entry Matches, Hw Refill Also Missed)

DtlbMultiHit

Dtlb Multihit (Multiple Dtlb Entries Match)

LoadStoreRing

Ring Privilege Violation On Load Or Store

Reserved27

Size Restriction On Load/Store (Not Implemented)

LoadProhibited

Cache Attribute Does Not Allow Load

StoreProhibited

Cache Attribute Does Not Allow Store

Reserved30

Reserved

Reserved31

Reserved

Cp0Disabled

Access To Coprocessor 0 When Disabled

Cp1Disabled

Access To Coprocessor 1 When Disabled

Cp2Disabled

Access To Coprocessor 2 When Disabled

Cp3Disabled

Access To Coprocessor 3 When Disabled

Cp4Disabled

Access To Coprocessor 4 When Disabled

Cp5Disabled

Access To Coprocessor 5 When Disabled

Cp6Disabled

Access To Coprocessor 6 When Disabled

Cp7Disabled

Access To Coprocessor 7 When Disabled

None

Trait Implementations

impl Debug for ExceptionCause

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.