Type Alias xmc4800::ebu::busrcon0::W

pub type W = W<BUSRCON0_SPEC>;

Register BUSRCON0 writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn fetblen(&mut self) -> FETBLEN_W<'_, BUSRCON0_SPEC>

Bits 0:2 - Burst Length for Synchronous Burst

pub fn fbbmsel(&mut self) -> FBBMSEL_W<'_, BUSRCON0_SPEC>

Bit 3 - Synchronous burst buffer mode select

pub fn bfsss(&mut self) -> BFSSS_W<'_, BUSRCON0_SPEC>

Bit 4 - Read Single Stage Synchronization:

pub fn fdbken(&mut self) -> FDBKEN_W<'_, BUSRCON0_SPEC>

Bit 5 - Burst FLASH Clock Feedback Enable

pub fn bfcmsel(&mut self) -> BFCMSEL_W<'_, BUSRCON0_SPEC>

Bit 6 - Burst Flash Clock Mode Select

pub fn naa(&mut self) -> NAA_W<'_, BUSRCON0_SPEC>

Bit 7 - Enable flash non-array access workaround

pub fn ecse(&mut self) -> ECSE_W<'_, BUSRCON0_SPEC>

Bit 16 - Early Chip Select for Synchronous Burst

pub fn ebse(&mut self) -> EBSE_W<'_, BUSRCON0_SPEC>

Bit 17 - Early Burst Signal Enable for Synchronous Burst

pub fn dba(&mut self) -> DBA_W<'_, BUSRCON0_SPEC>

Bit 18 - Disable Burst Address Wrapping

pub fn waitinv(&mut self) -> WAITINV_W<'_, BUSRCON0_SPEC>

Bit 19 - Reversed polarity at WAIT

pub fn bcgen(&mut self) -> BCGEN_W<'_, BUSRCON0_SPEC>

Bits 20:21 - Byte Control Signal Control

pub fn portw(&mut self) -> PORTW_W<'_, BUSRCON0_SPEC>

Bits 22:23 - Device Addressing Mode

pub fn wait(&mut self) -> WAIT_W<'_, BUSRCON0_SPEC>

Bits 24:25 - External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access.,

pub fn aap(&mut self) -> AAP_W<'_, BUSRCON0_SPEC>

Bit 26 - Asynchronous Address phase:

pub fn agen(&mut self) -> AGEN_W<'_, BUSRCON0_SPEC>

Bits 28:31 - Device Type for Region