Type Alias xmc4800::eth0::mmc_receive_interrupt_mask::W
source · pub type W = W<MmcReceiveInterruptMaskSpec>;
Expand description
Register MMC_RECEIVE_INTERRUPT_MASK
writer
Aliased Type§
struct W { /* private fields */ }
Implementations§
source§impl W
impl W
sourcepub fn rxgbfrmim(&mut self) -> RxgbfrmimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxgbfrmim(&mut self) -> RxgbfrmimW<'_, MmcReceiveInterruptMaskSpec>
Bit 0 - MMC Receive Good Bad Frame Counter Interrupt Mask
sourcepub fn rxgboctim(&mut self) -> RxgboctimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxgboctim(&mut self) -> RxgboctimW<'_, MmcReceiveInterruptMaskSpec>
Bit 1 - MMC Receive Good Bad Octet Counter Interrupt Mask
sourcepub fn rxgoctim(&mut self) -> RxgoctimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxgoctim(&mut self) -> RxgoctimW<'_, MmcReceiveInterruptMaskSpec>
Bit 2 - MMC Receive Good Octet Counter Interrupt Mask
sourcepub fn rxbcgfim(&mut self) -> RxbcgfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxbcgfim(&mut self) -> RxbcgfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 3 - MMC Receive Broadcast Good Frame Counter Interrupt Mask
sourcepub fn rxmcgfim(&mut self) -> RxmcgfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxmcgfim(&mut self) -> RxmcgfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 4 - MMC Receive Multicast Good Frame Counter Interrupt Mask
sourcepub fn rxcrcerfim(&mut self) -> RxcrcerfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxcrcerfim(&mut self) -> RxcrcerfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 5 - MMC Receive CRC Error Frame Counter Interrupt Mask
sourcepub fn rxalgnerfim(&mut self) -> RxalgnerfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxalgnerfim(&mut self) -> RxalgnerfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 6 - MMC Receive Alignment Error Frame Counter Interrupt Mask
sourcepub fn rxruntfim(&mut self) -> RxruntfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxruntfim(&mut self) -> RxruntfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 7 - MMC Receive Runt Frame Counter Interrupt Mask
sourcepub fn rxjaberfim(&mut self) -> RxjaberfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxjaberfim(&mut self) -> RxjaberfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 8 - MMC Receive Jabber Error Frame Counter Interrupt Mask
sourcepub fn rxusizegfim(&mut self) -> RxusizegfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxusizegfim(&mut self) -> RxusizegfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 9 - MMC Receive Undersize Good Frame Counter Interrupt Mask
sourcepub fn rxosizegfim(&mut self) -> RxosizegfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxosizegfim(&mut self) -> RxosizegfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 10 - MMC Receive Oversize Good Frame Counter Interrupt Mask
sourcepub fn rx64octgbfim(&mut self) -> Rx64octgbfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rx64octgbfim(&mut self) -> Rx64octgbfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 11 - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask
sourcepub fn rx65t127octgbfim(
&mut self
) -> Rx65t127octgbfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rx65t127octgbfim( &mut self ) -> Rx65t127octgbfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 12 - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask
sourcepub fn rx128t255octgbfim(
&mut self
) -> Rx128t255octgbfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rx128t255octgbfim( &mut self ) -> Rx128t255octgbfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 13 - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask
sourcepub fn rx256t511octgbfim(
&mut self
) -> Rx256t511octgbfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rx256t511octgbfim( &mut self ) -> Rx256t511octgbfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 14 - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask
sourcepub fn rx512t1023octgbfim(
&mut self
) -> Rx512t1023octgbfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rx512t1023octgbfim( &mut self ) -> Rx512t1023octgbfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 15 - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask
sourcepub fn rx1024tmaxoctgbfim(
&mut self
) -> Rx1024tmaxoctgbfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rx1024tmaxoctgbfim( &mut self ) -> Rx1024tmaxoctgbfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 16 - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask
sourcepub fn rxucgfim(&mut self) -> RxucgfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxucgfim(&mut self) -> RxucgfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 17 - MMC Receive Unicast Good Frame Counter Interrupt Mask
sourcepub fn rxlenerfim(&mut self) -> RxlenerfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxlenerfim(&mut self) -> RxlenerfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 18 - MMC Receive Length Error Frame Counter Interrupt Mask
sourcepub fn rxorangefim(&mut self) -> RxorangefimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxorangefim(&mut self) -> RxorangefimW<'_, MmcReceiveInterruptMaskSpec>
Bit 19 - MMC Receive Out Of Range Error Frame Counter Interrupt Mask
sourcepub fn rxpausfim(&mut self) -> RxpausfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxpausfim(&mut self) -> RxpausfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 20 - MMC Receive Pause Frame Counter Interrupt Mask
sourcepub fn rxfovfim(&mut self) -> RxfovfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxfovfim(&mut self) -> RxfovfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 21 - MMC Receive FIFO Overflow Frame Counter Interrupt Mask
sourcepub fn rxvlangbfim(&mut self) -> RxvlangbfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxvlangbfim(&mut self) -> RxvlangbfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 22 - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask
sourcepub fn rxwdogfim(&mut self) -> RxwdogfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxwdogfim(&mut self) -> RxwdogfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 23 - MMC Receive Watchdog Error Frame Counter Interrupt Mask
sourcepub fn rxrcverrfim(&mut self) -> RxrcverrfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxrcverrfim(&mut self) -> RxrcverrfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 24 - MMC Receive Error Frame Counter Interrupt Mask
sourcepub fn rxctrlfim(&mut self) -> RxctrlfimW<'_, MmcReceiveInterruptMaskSpec>
pub fn rxctrlfim(&mut self) -> RxctrlfimW<'_, MmcReceiveInterruptMaskSpec>
Bit 25 - MMC Receive Control Frame Counter Interrupt Mask