Type Alias xmc4800::eth0::mmc_receive_interrupt_mask::W

pub type W = W<MMC_RECEIVE_INTERRUPT_MASK_SPEC>;

Register MMC_RECEIVE_INTERRUPT_MASK writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn rxgbfrmim(&mut self) -> RXGBFRMIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 0 - MMC Receive Good Bad Frame Counter Interrupt Mask

pub fn rxgboctim(&mut self) -> RXGBOCTIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 1 - MMC Receive Good Bad Octet Counter Interrupt Mask

pub fn rxgoctim(&mut self) -> RXGOCTIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 2 - MMC Receive Good Octet Counter Interrupt Mask

pub fn rxbcgfim(&mut self) -> RXBCGFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 3 - MMC Receive Broadcast Good Frame Counter Interrupt Mask

pub fn rxmcgfim(&mut self) -> RXMCGFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 4 - MMC Receive Multicast Good Frame Counter Interrupt Mask

pub fn rxcrcerfim( &mut self ) -> RXCRCERFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 5 - MMC Receive CRC Error Frame Counter Interrupt Mask

pub fn rxalgnerfim( &mut self ) -> RXALGNERFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 6 - MMC Receive Alignment Error Frame Counter Interrupt Mask

pub fn rxruntfim(&mut self) -> RXRUNTFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 7 - MMC Receive Runt Frame Counter Interrupt Mask

pub fn rxjaberfim( &mut self ) -> RXJABERFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 8 - MMC Receive Jabber Error Frame Counter Interrupt Mask

pub fn rxusizegfim( &mut self ) -> RXUSIZEGFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 9 - MMC Receive Undersize Good Frame Counter Interrupt Mask

pub fn rxosizegfim( &mut self ) -> RXOSIZEGFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 10 - MMC Receive Oversize Good Frame Counter Interrupt Mask

pub fn rx64octgbfim( &mut self ) -> RX64OCTGBFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 11 - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask

pub fn rx65t127octgbfim( &mut self ) -> RX65T127OCTGBFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 12 - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask

pub fn rx128t255octgbfim( &mut self ) -> RX128T255OCTGBFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 13 - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask

pub fn rx256t511octgbfim( &mut self ) -> RX256T511OCTGBFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 14 - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask

pub fn rx512t1023octgbfim( &mut self ) -> RX512T1023OCTGBFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 15 - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask

pub fn rx1024tmaxoctgbfim( &mut self ) -> RX1024TMAXOCTGBFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 16 - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask

pub fn rxucgfim(&mut self) -> RXUCGFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 17 - MMC Receive Unicast Good Frame Counter Interrupt Mask

pub fn rxlenerfim( &mut self ) -> RXLENERFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 18 - MMC Receive Length Error Frame Counter Interrupt Mask

pub fn rxorangefim( &mut self ) -> RXORANGEFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 19 - MMC Receive Out Of Range Error Frame Counter Interrupt Mask

pub fn rxpausfim(&mut self) -> RXPAUSFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 20 - MMC Receive Pause Frame Counter Interrupt Mask

pub fn rxfovfim(&mut self) -> RXFOVFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 21 - MMC Receive FIFO Overflow Frame Counter Interrupt Mask

pub fn rxvlangbfim( &mut self ) -> RXVLANGBFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 22 - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask

pub fn rxwdogfim(&mut self) -> RXWDOGFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 23 - MMC Receive Watchdog Error Frame Counter Interrupt Mask

pub fn rxrcverrfim( &mut self ) -> RXRCVERRFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 24 - MMC Receive Error Frame Counter Interrupt Mask

pub fn rxctrlfim(&mut self) -> RXCTRLFIM_W<'_, MMC_RECEIVE_INTERRUPT_MASK_SPEC>

Bit 25 - MMC Receive Control Frame Counter Interrupt Mask