Type Alias xmc4300::usic0_ch0::pcr_ascmode::MCLK_W

pub type MCLK_W<'a, REG> = BitWriter<'a, REG, MCLK_A>;

Field MCLK writer - Master Clock Enable

Aliased Type

struct MCLK_W<'a, REG> { /* private fields */ }

Implementations

impl<'a, REG> MCLK_W<'a, REG>

where REG: Writable + RegisterSpec,

pub fn value1(self) -> &'a mut W<REG>

The MCLK generation is disabled and the MCLK signal is 0.

pub fn value2(self) -> &'a mut W<REG>

The MCLK generation is enabled.