Struct NetlistModule 

pub struct NetlistModule {
    pub name: PortId,
    pub net_index_range: Range<usize>,
    pub ports: Vec<NetlistPort>,
    pub wires: Vec<NetIndex>,
    pub assigns: Vec<NetlistAssign>,
    pub instances: Vec<NetlistInstance>,
}

Parsed gate-level module.

Invariants enforced by the parser:

• instances is the list of instance declarations in the module body.
• instance_name values are unique within a module; if the input netlist contains multiple instances with the same name, parsing fails with a ScanError instead of constructing a NetlistModule.
• Gate-level parsing honors Verilog implicit-wire semantics: if an identifier is used in a net context but has not been explicitly declared, the parser (by default) synthesizes an implicit 1-bit wire for that name, scoped to the current module.

Fields

name: PortId

net_index_range: Range<usize>

Range into the file-global nets table that belongs to this module.

ports: Vec<NetlistPort>

wires: Vec<NetIndex>

assigns: Vec<NetlistAssign>

instances: Vec<NetlistInstance>

Implementations

impl NetlistModule

pub fn find_net_index(&self, net_name: NetId, nets: &[Net]) -> Option<NetIndex>

Looks up a net by name within this module’s namespace.

Trait Implementations

impl Clone for NetlistModule

fn clone(&self) -> NetlistModule

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for NetlistModule

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for NetlistModule

fn eq(&self, other: &NetlistModule) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Eq for NetlistModule

impl StructuralPartialEq for NetlistModule