Struct RegisterBlock

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pub struct RegisterBlock { /* private fields */ }

Expand description

Register block

Implementations§

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impl RegisterBlock

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pub const fn spi_er(&self) -> &SpiEr

0x00 - SPI enable register

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pub const fn spi_ctra(&self) -> &SpiCtra

0x04 - SPI control register 0

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pub const fn spi_ctrb(&self) -> &SpiCtrb

0x08 - SPI control register 1 (master only)

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pub const fn spi_enhctl(&self) -> &SpiEnhctl

0x0c - Enhanced control register (Dual/Quad/Octal)

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pub const fn spi_brs(&self) -> &SpiBrs

0x14 - Baud rate select register

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pub const fn spi_dcr(&self) -> &SpiDcr

0x18 - DMA control register

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pub const fn spi_drdl(&self) -> &SpiDrdl

0x1c - DMA RX data level

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pub const fn spi_dtdl(&self) -> &SpiDtdl

0x20 - DMA TX data level

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pub const fn spi_dr(&self) -> &SpiDr

0x60 - Data register (FIFO read/write)

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pub const fn spi_rainsr(&self) -> &SpiRainsr

0xbc - Raw interrupt status register

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pub const fn spi_insr(&self) -> &SpiInsr

0xc0 - Interrupt status register (masked)

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pub const fn spi_inmar(&self) -> &SpiInmar

0xc4 - Interrupt mask register

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pub const fn spi_slenr(&self) -> &SpiSlenr

0xc8 - Slave enable register (master only)

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pub const fn spi_twlr(&self) -> &SpiTwlr

0xcc - TX FIFO threshold level

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pub const fn spi_tlr(&self) -> &SpiTlr

0xd0 - TX FIFO level register

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pub const fn spi_rwlr(&self) -> &SpiRwlr

0xd8 - RX FIFO threshold level

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pub const fn spi_rlr(&self) -> &SpiRlr

0xdc - RX FIFO level register

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pub const fn spi_wsr(&self) -> &SpiWsr

0xe4 - Status register. Bit layout matches the HiSilicon SSI v151 silicon (vendor hal_spi_v151_regs_def.h spi_wsr_data), NOT the textbook DesignWare SR: the FIFO/busy flags are spread out, not packed in bits 0..6. Verified on WS63 silicon 2026-06-14 (idle reads 0x1800 = TXFNF | TXFE).

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