Expand description
UART driver for WS63 (UART0/1/2, 16C550-compatible with FIFO).
Baud rate: div = (div_h << 8 | div_l) + div_fra / 64.
Clock source: the 160 MHz PLL-derived UART clock (crate::soc::ws63::UART_CLOCK_HZ),
NOT the 240 MHz CPU clock (vendor clock_init sets the baud base to 160 MHz).