Module clock_init 

Clock initialization for WS63.

Based on the fbb_ws63 C SDK boot sequence analysis:

What the boot ROM / bootloader does

The flashboot bootloader (flashboot_ws63/startup/main.c) runs before the application and performs:

1. boot_clock_adapt() — detects TCXO (24/40MHz), configures UART/WDT tick rates
2. switch_flash_clock_to_pll() — sets CLDO_CRG_CLK_SEL bit 18 to switch the flash controller clock source from TCXO to PLL. Does NOT switch CPU, UART, or other peripheral clocks.
3. Initializes watchdog, eFuse, SPI flash, partition table
4. Loads and jumps to the application image

The CPU PLL (240MHz) is configured by the boot ROM before the bootloader runs. The bootloader inherits this configuration.

What the application must do

The application-level clock_init.c in the LiteOS SDK performs:

1. switch_clock() — switches peripheral clocks from TCXO to PLL:
   • UART0/1/2: CLDO_CRG_CLK_SEL bits 1,2,3
   • WiFi MAC: bit 20, WiFi PHY: bit 19
   • RF_CTL: bit 0
   • SPI: bit 6 (spi_porting.c)
2. set_uart_tcxo_clock_period() — configures UART baud base, timer tick, watchdog period, I2C clock based on detected TCXO frequency

For a bare-metal Rust application (no LiteOS), we provide:

• probe_clocks() — non-invasive: detect TCXO and PLL status
• init_clocks() — full init: switch flash to PLL + switch UART/SPI to PLL

CLDO_CRG_CLK_SEL bit map (from fbb_ws63 clock_init.c)

Bit	Peripheral	Description
0	RF_CTL	RF control clock → PLL
1	UART0	UART0 clock → PLL
2	UART1	UART1 clock → PLL
3	UART2	UART2 clock → PLL
6	SPI	SPI clock → PLL
18	FLASH	Flash/SFC controller → PLL
19	WiFi PHY	WiFi PHY clock → PLL
20	WiFi MAC	WiFi MAC clock → PLL

Register map (from fbb_ws63)

Register	Address	Description
HW_CTL	0x4000_0014	TCXO frequency detect (bit[0]: 0=24MHz, 1=40MHz)
REG_EXCEP_RO_RG	0x4000_319C	PLL lock status (bit 12)
CMU_NEW_CFG1	0x4000_34A4	Flash clock control
CLDO_CRG_CLK_SEL	0x4400_1134	Clock source select
CLDO_SUB_CRG_CKEN_CTL1	0x4400_1104	UART clock gate control

Clock tree (from ws63-guide ch2_system.md)

Domain	Frequency	Clock Source
CPU	240 MHz	PLL
CPU Bus	240 MHz	PLL
GPIO	120 MHz	PLL / 2
UART	160 MHz	PLL-derived
SPI	160 MHz	PLL-derived
I2C	80 MHz	PLL-derived
QSPI	64 MHz	PLL-derived
Timer	32 kHz	Crystal
WDT	32 kHz	Crystal
RTC	32 kHz	Crystal
Crystal	40/24 MHz	TCXO

Structs

SystemClocks

System clock configuration after initialization.

Enums

PllStatus

Result of PLL lock check.

TcxoFreq

TCXO crystal frequency in Hz.

Functions

init_clocks

Initialize the system clock tree.

probe_clocks

Simple version: detect clocks without modifying them.