Struct wishbone_tool::riscv::RiscvCpu

pub struct RiscvCpu { /* fields omitted */ }

Implementations

impl RiscvCpu

pub fn new(bridge: &Bridge, offset: u32) -> Result<RiscvCpu, RiscvCpuError>

pub fn get_feature(&self, name: &str) -> Result<Vec<u8>, RiscvCpuError>

pub fn get_threads(&self) -> Result<Vec<u8>, RiscvCpuError>

pub fn explain(&self, bridge: &Bridge) -> Result<String, RiscvCpuError>

Print information about why the CPU got into its current state

pub fn add_breakpoint(
    &self,
    bridge: &Bridge,
    addr: u32
) -> Result<(), RiscvCpuError>

pub fn remove_breakpoint(
    &self,
    bridge: &Bridge,
    addr: u32
) -> Result<(), RiscvCpuError>

pub fn halt(&self, bridge: &Bridge) -> Result<(), RiscvCpuError>

pub fn reset(&self, bridge: &Bridge) -> Result<(), RiscvCpuError>

Reset the target CPU, restore any breakpoints, and leave it in the "halted" state.

pub fn resume(&self, bridge: &Bridge) -> Result<Option<String>, RiscvCpuError>

Restore the CPU state and continue execution.

pub fn step(&self, bridge: &Bridge) -> Result<Option<String>, RiscvCpuError>

Step the CPU forward by one instruction.

pub fn read_register(
    &self,
    bridge: &Bridge,
    gdb_idx: u32
) -> Result<u32, RiscvCpuError>

Read the specified register and return its value.

The gdb_idx is the GDB index, and may include both CPU registers and CSR-index registers, which are offset by an index.

pub fn all_cpu_registers(&self) -> Vec<u32>

Return a vec containing all valid CPU registers.

pub fn write_register(
    &self,
    bridge: &Bridge,
    gdb_idx: u32,
    value: u32
) -> Result<(), RiscvCpuError>

Write a register on the device.

For general-purpose registers, simply place the new value in the cache, to be updated when we resume the CPU.

For CSRs, initiate the write immediately.

pub fn read_memory(
    &self,
    bridge: &Bridge,
    addr: u32,
    sz: u32
) -> Result<u32, RiscvCpuError>

pub fn write_memory(
    &self,
    bridge: &Bridge,
    addr: u32,
    sz: u32,
    value: u32
) -> Result<(), RiscvCpuError>

pub fn get_controller(&self) -> RiscvCpuController

pub fn flush_cache(&self, bridge: &Bridge) -> Result<(), RiscvCpuError>