Struct wip_s32k144::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _EMBEDDEDRAM>>

pub fn byte_3(&mut self) -> BYTE_3_W

Bits 0:7 - BYTE_3 stores the fourth 8 bits of the 32 bit CRC.

pub fn byte_2(&mut self) -> BYTE_2_W

Bits 8:15 - BYTE_2 stores the third 8 bits of the 32 bit CRC.

pub fn byte_1(&mut self) -> BYTE_1_W

Bits 16:23 - BYTE_1 stores the second 8 bits of the 32 bit CRC.

pub fn byte_0(&mut self) -> BYTE_0_W

Bits 24:31 - BYTE_0 stores the first 8 bits of the 32 bit CRC.

impl W<u32, Reg<u32, _MPRA>>

pub fn mpl2(&mut self) -> MPL2_W

Bit 20 - Master 2 Privilege Level

pub fn mtw2(&mut self) -> MTW2_W

Bit 21 - Master 2 Trusted For Writes

pub fn mtr2(&mut self) -> MTR2_W

Bit 22 - Master 2 Trusted For Read

pub fn mpl1(&mut self) -> MPL1_W

Bit 24 - Master 1 Privilege Level

pub fn mtw1(&mut self) -> MTW1_W

Bit 25 - Master 1 Trusted for Writes

pub fn mtr1(&mut self) -> MTR1_W

Bit 26 - Master 1 Trusted for Read

pub fn mpl0(&mut self) -> MPL0_W

Bit 28 - Master 0 Privilege Level

pub fn mtw0(&mut self) -> MTW0_W

Bit 29 - Master 0 Trusted For Writes

pub fn mtr0(&mut self) -> MTR0_W

Bit 30 - Master 0 Trusted For Read

impl W<u32, Reg<u32, _PACRA>>

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted Protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRB>>

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted Protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRD>>

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted Protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _OPACRA>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted Protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor Protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted Protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _OPACRB>>

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted Protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor Protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write Protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

impl W<u32, Reg<u32, _OPACRC>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted Protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor Protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

impl W<u32, Reg<u32, _OPACRD>>

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write Protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted Protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor Protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted Protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _OPACRE>>

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted Protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _OPACRF>>

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted Protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor Protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write Protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted Protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor Protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted Protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _OPACRG>>

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted Protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor Protect

impl W<u32, Reg<u32, _OPACRH>>

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted Protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor Protect

impl W<u32, Reg<u32, _OPACRI>>

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted Protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor Protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write Protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

impl W<u32, Reg<u32, _OPACRJ>>

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted Protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor Protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write Protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted Protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor Protect

impl W<u32, Reg<u32, _OPACRK>>

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write Protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

impl W<u32, Reg<u32, _OPACRL>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

impl W<u32, Reg<u32, _OCMDR0>>

pub fn ocm0(&mut self) -> OCM0_W

Bits 0:3 - OCMEM Control Field 0

pub fn ocm1(&mut self) -> OCM1_W

Bits 4:7 - OCMEM Control Field 1

pub fn ocm2(&mut self) -> OCM2_W

Bits 8:11 - OCMEM Control Field 2

pub fn ro(&mut self) -> RO_W

Bit 16 - RO

impl W<u32, Reg<u32, _OCMDR1>>

pub fn ocm0(&mut self) -> OCM0_W

Bits 0:3 - OCMEM Control Field 0

pub fn ocm1(&mut self) -> OCM1_W

Bits 4:7 - OCMEM Control Field 1

pub fn ocm2(&mut self) -> OCM2_W

Bits 8:11 - OCMEM Control Field 2

pub fn ro(&mut self) -> RO_W

Bit 16 - RO

impl W<u32, Reg<u32, _OCMDR2>>

pub fn ocm0(&mut self) -> OCM0_W

Bits 0:3 - OCMEM Control Field 0

pub fn ocm1(&mut self) -> OCM1_W

Bits 4:7 - OCMEM Control Field 1

pub fn ocm2(&mut self) -> OCM2_W

Bits 8:11 - OCMEM Control Field 2

pub fn ro(&mut self) -> RO_W

Bit 16 - RO

impl W<u32, Reg<u32, _OCMDR3>>

pub fn ocm0(&mut self) -> OCM0_W

Bits 0:3 - OCMEM Control Field 0

pub fn ocm1(&mut self) -> OCM1_W

Bits 4:7 - OCMEM Control Field 1

pub fn ocm2(&mut self) -> OCM2_W

Bits 8:11 - OCMEM Control Field 2

pub fn ro(&mut self) -> RO_W

Bit 16 - RO

impl W<u32, Reg<u32, _CR>>

pub fn edbg(&mut self) -> EDBG_W

Bit 1 - Enable Debug

pub fn erca(&mut self) -> ERCA_W

Bit 2 - Enable Round Robin Channel Arbitration

pub fn hoe(&mut self) -> HOE_W

Bit 4 - Halt On Error

pub fn halt(&mut self) -> HALT_W

Bit 5 - Halt DMA Operations

pub fn clm(&mut self) -> CLM_W

Bit 6 - Continuous Link Mode

pub fn emlm(&mut self) -> EMLM_W

Bit 7 - Enable Minor Loop Mapping

pub fn ecx(&mut self) -> ECX_W

Bit 16 - Error Cancel Transfer

pub fn cx(&mut self) -> CX_W

Bit 17 - Cancel Transfer

impl W<u32, Reg<u32, _ERQ>>

pub fn erq0(&mut self) -> ERQ0_W

Bit 0 - Enable DMA Request 0

pub fn erq1(&mut self) -> ERQ1_W

Bit 1 - Enable DMA Request 1

pub fn erq2(&mut self) -> ERQ2_W

Bit 2 - Enable DMA Request 2

pub fn erq3(&mut self) -> ERQ3_W

Bit 3 - Enable DMA Request 3

pub fn erq4(&mut self) -> ERQ4_W

Bit 4 - Enable DMA Request 4

pub fn erq5(&mut self) -> ERQ5_W

Bit 5 - Enable DMA Request 5

pub fn erq6(&mut self) -> ERQ6_W

Bit 6 - Enable DMA Request 6

pub fn erq7(&mut self) -> ERQ7_W

Bit 7 - Enable DMA Request 7

pub fn erq8(&mut self) -> ERQ8_W

Bit 8 - Enable DMA Request 8

pub fn erq9(&mut self) -> ERQ9_W

Bit 9 - Enable DMA Request 9

pub fn erq10(&mut self) -> ERQ10_W

Bit 10 - Enable DMA Request 10

pub fn erq11(&mut self) -> ERQ11_W

Bit 11 - Enable DMA Request 11

pub fn erq12(&mut self) -> ERQ12_W

Bit 12 - Enable DMA Request 12

pub fn erq13(&mut self) -> ERQ13_W

Bit 13 - Enable DMA Request 13

pub fn erq14(&mut self) -> ERQ14_W

Bit 14 - Enable DMA Request 14

pub fn erq15(&mut self) -> ERQ15_W

Bit 15 - Enable DMA Request 15

impl W<u32, Reg<u32, _EEI>>

pub fn eei0(&mut self) -> EEI0_W

Bit 0 - Enable Error Interrupt 0

pub fn eei1(&mut self) -> EEI1_W

Bit 1 - Enable Error Interrupt 1

pub fn eei2(&mut self) -> EEI2_W

Bit 2 - Enable Error Interrupt 2

pub fn eei3(&mut self) -> EEI3_W

Bit 3 - Enable Error Interrupt 3

pub fn eei4(&mut self) -> EEI4_W

Bit 4 - Enable Error Interrupt 4

pub fn eei5(&mut self) -> EEI5_W

Bit 5 - Enable Error Interrupt 5

pub fn eei6(&mut self) -> EEI6_W

Bit 6 - Enable Error Interrupt 6

pub fn eei7(&mut self) -> EEI7_W

Bit 7 - Enable Error Interrupt 7

pub fn eei8(&mut self) -> EEI8_W

Bit 8 - Enable Error Interrupt 8

pub fn eei9(&mut self) -> EEI9_W

Bit 9 - Enable Error Interrupt 9

pub fn eei10(&mut self) -> EEI10_W

Bit 10 - Enable Error Interrupt 10

pub fn eei11(&mut self) -> EEI11_W

Bit 11 - Enable Error Interrupt 11

pub fn eei12(&mut self) -> EEI12_W

Bit 12 - Enable Error Interrupt 12

pub fn eei13(&mut self) -> EEI13_W

Bit 13 - Enable Error Interrupt 13

pub fn eei14(&mut self) -> EEI14_W

Bit 14 - Enable Error Interrupt 14

pub fn eei15(&mut self) -> EEI15_W

Bit 15 - Enable Error Interrupt 15

impl W<u8, Reg<u8, _CEEI>>

pub fn ceei(&mut self) -> CEEI_W

Bits 0:3 - Clear Enable Error Interrupt

pub fn caee(&mut self) -> CAEE_W

Bit 6 - Clear All Enable Error Interrupts

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u8, Reg<u8, _SEEI>>

pub fn seei(&mut self) -> SEEI_W

Bits 0:3 - Set Enable Error Interrupt

pub fn saee(&mut self) -> SAEE_W

Bit 6 - Sets All Enable Error Interrupts

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u8, Reg<u8, _CERQ>>

pub fn cerq(&mut self) -> CERQ_W

Bits 0:3 - Clear Enable Request

pub fn caer(&mut self) -> CAER_W

Bit 6 - Clear All Enable Requests

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u8, Reg<u8, _SERQ>>

pub fn serq(&mut self) -> SERQ_W

Bits 0:3 - Set Enable Request

pub fn saer(&mut self) -> SAER_W

Bit 6 - Set All Enable Requests

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u8, Reg<u8, _CDNE>>

pub fn cdne(&mut self) -> CDNE_W

Bits 0:3 - Clear DONE Bit

pub fn cadn(&mut self) -> CADN_W

Bit 6 - Clears All DONE Bits

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u8, Reg<u8, _SSRT>>

pub fn ssrt(&mut self) -> SSRT_W

Bits 0:3 - Set START Bit

pub fn sast(&mut self) -> SAST_W

Bit 6 - Set All START Bits (activates all channels)

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u8, Reg<u8, _CERR>>

pub fn cerr(&mut self) -> CERR_W

Bits 0:3 - Clear Error Indicator

pub fn caei(&mut self) -> CAEI_W

Bit 6 - Clear All Error Indicators

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u8, Reg<u8, _CINT>>

pub fn cint(&mut self) -> CINT_W

Bits 0:3 - Clear Interrupt Request

pub fn cair(&mut self) -> CAIR_W

Bit 6 - Clear All Interrupt Requests

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u32, Reg<u32, _INT>>

pub fn int0(&mut self) -> INT0_W

Bit 0 - Interrupt Request 0

pub fn int1(&mut self) -> INT1_W

Bit 1 - Interrupt Request 1

pub fn int2(&mut self) -> INT2_W

Bit 2 - Interrupt Request 2

pub fn int3(&mut self) -> INT3_W

Bit 3 - Interrupt Request 3

pub fn int4(&mut self) -> INT4_W

Bit 4 - Interrupt Request 4

pub fn int5(&mut self) -> INT5_W

Bit 5 - Interrupt Request 5

pub fn int6(&mut self) -> INT6_W

Bit 6 - Interrupt Request 6

pub fn int7(&mut self) -> INT7_W

Bit 7 - Interrupt Request 7

pub fn int8(&mut self) -> INT8_W

Bit 8 - Interrupt Request 8

pub fn int9(&mut self) -> INT9_W

Bit 9 - Interrupt Request 9

pub fn int10(&mut self) -> INT10_W

Bit 10 - Interrupt Request 10

pub fn int11(&mut self) -> INT11_W

Bit 11 - Interrupt Request 11

pub fn int12(&mut self) -> INT12_W

Bit 12 - Interrupt Request 12

pub fn int13(&mut self) -> INT13_W

Bit 13 - Interrupt Request 13

pub fn int14(&mut self) -> INT14_W

Bit 14 - Interrupt Request 14

pub fn int15(&mut self) -> INT15_W

Bit 15 - Interrupt Request 15

impl W<u32, Reg<u32, _ERR>>

pub fn err0(&mut self) -> ERR0_W

Bit 0 - Error In Channel 0

pub fn err1(&mut self) -> ERR1_W

Bit 1 - Error In Channel 1

pub fn err2(&mut self) -> ERR2_W

Bit 2 - Error In Channel 2

pub fn err3(&mut self) -> ERR3_W

Bit 3 - Error In Channel 3

pub fn err4(&mut self) -> ERR4_W

Bit 4 - Error In Channel 4

pub fn err5(&mut self) -> ERR5_W

Bit 5 - Error In Channel 5

pub fn err6(&mut self) -> ERR6_W

Bit 6 - Error In Channel 6

pub fn err7(&mut self) -> ERR7_W

Bit 7 - Error In Channel 7

pub fn err8(&mut self) -> ERR8_W

Bit 8 - Error In Channel 8

pub fn err9(&mut self) -> ERR9_W

Bit 9 - Error In Channel 9

pub fn err10(&mut self) -> ERR10_W

Bit 10 - Error In Channel 10

pub fn err11(&mut self) -> ERR11_W

Bit 11 - Error In Channel 11

pub fn err12(&mut self) -> ERR12_W

Bit 12 - Error In Channel 12

pub fn err13(&mut self) -> ERR13_W

Bit 13 - Error In Channel 13

pub fn err14(&mut self) -> ERR14_W

Bit 14 - Error In Channel 14

pub fn err15(&mut self) -> ERR15_W

Bit 15 - Error In Channel 15

impl W<u32, Reg<u32, _EARS>>

pub fn edreq_0(&mut self) -> EDREQ_0_W

Bit 0 - Enable asynchronous DMA request in stop mode for channel 0.

pub fn edreq_1(&mut self) -> EDREQ_1_W

Bit 1 - Enable asynchronous DMA request in stop mode for channel 1.

pub fn edreq_2(&mut self) -> EDREQ_2_W

Bit 2 - Enable asynchronous DMA request in stop mode for channel 2.

pub fn edreq_3(&mut self) -> EDREQ_3_W

Bit 3 - Enable asynchronous DMA request in stop mode for channel 3.

pub fn edreq_4(&mut self) -> EDREQ_4_W

Bit 4 - Enable asynchronous DMA request in stop mode for channel 4

pub fn edreq_5(&mut self) -> EDREQ_5_W

Bit 5 - Enable asynchronous DMA request in stop mode for channel 5

pub fn edreq_6(&mut self) -> EDREQ_6_W

Bit 6 - Enable asynchronous DMA request in stop mode for channel 6

pub fn edreq_7(&mut self) -> EDREQ_7_W

Bit 7 - Enable asynchronous DMA request in stop mode for channel 7

pub fn edreq_8(&mut self) -> EDREQ_8_W

Bit 8 - Enable asynchronous DMA request in stop mode for channel 8

pub fn edreq_9(&mut self) -> EDREQ_9_W

Bit 9 - Enable asynchronous DMA request in stop mode for channel 9

pub fn edreq_10(&mut self) -> EDREQ_10_W

Bit 10 - Enable asynchronous DMA request in stop mode for channel 10

pub fn edreq_11(&mut self) -> EDREQ_11_W

Bit 11 - Enable asynchronous DMA request in stop mode for channel 11

pub fn edreq_12(&mut self) -> EDREQ_12_W

Bit 12 - Enable asynchronous DMA request in stop mode for channel 12

pub fn edreq_13(&mut self) -> EDREQ_13_W

Bit 13 - Enable asynchronous DMA request in stop mode for channel 13

pub fn edreq_14(&mut self) -> EDREQ_14_W

Bit 14 - Enable asynchronous DMA request in stop mode for channel 14

pub fn edreq_15(&mut self) -> EDREQ_15_W

Bit 15 - Enable asynchronous DMA request in stop mode for channel 15

impl W<u8, Reg<u8, _DCHPRI3>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u8, Reg<u8, _DCHPRI2>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u8, Reg<u8, _DCHPRI1>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u8, Reg<u8, _DCHPRI0>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u8, Reg<u8, _DCHPRI7>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u8, Reg<u8, _DCHPRI6>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u8, Reg<u8, _DCHPRI5>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u8, Reg<u8, _DCHPRI4>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u8, Reg<u8, _DCHPRI11>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u8, Reg<u8, _DCHPRI10>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u8, Reg<u8, _DCHPRI9>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u8, Reg<u8, _DCHPRI8>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u8, Reg<u8, _DCHPRI15>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u8, Reg<u8, _DCHPRI14>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u8, Reg<u8, _DCHPRI13>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u8, Reg<u8, _DCHPRI12>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability. This field resets to 0.

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption. This field resets to 0.

impl W<u32, Reg<u32, _TCD_SADDR>>

pub fn saddr(&mut self) -> SADDR_W

Bits 0:31 - Source Address

impl W<u16, Reg<u16, _TCD_SOFF>>

pub fn soff(&mut self) -> SOFF_W

Bits 0:15 - Source address signed offset

impl W<u16, Reg<u16, _TCD_ATTR>>

pub fn dsize(&mut self) -> DSIZE_W

Bits 0:2 - Destination data transfer size

pub fn dmod(&mut self) -> DMOD_W

Bits 3:7 - Destination Address Modulo

pub fn ssize(&mut self) -> SSIZE_W

Bits 8:10 - Source data transfer size

pub fn smod(&mut self) -> SMOD_W

Bits 11:15 - Source Address Modulo

impl W<u32, Reg<u32, _TCD_NBYTES_MLNO>>

pub fn nbytes(&mut self) -> NBYTES_W

Bits 0:31 - Minor Byte Transfer Count

impl W<u32, Reg<u32, _TCD_NBYTES_MLOFFNO>>

pub fn nbytes(&mut self) -> NBYTES_W

Bits 0:29 - Minor Byte Transfer Count

pub fn dmloe(&mut self) -> DMLOE_W

Bit 30 - Destination Minor Loop Offset enable

pub fn smloe(&mut self) -> SMLOE_W

Bit 31 - Source Minor Loop Offset Enable

impl W<u32, Reg<u32, _TCD_NBYTES_MLOFFYES>>

pub fn nbytes(&mut self) -> NBYTES_W

Bits 0:9 - Minor Byte Transfer Count

pub fn mloff(&mut self) -> MLOFF_W

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

pub fn dmloe(&mut self) -> DMLOE_W

Bit 30 - Destination Minor Loop Offset enable

pub fn smloe(&mut self) -> SMLOE_W

Bit 31 - Source Minor Loop Offset Enable

impl W<u32, Reg<u32, _TCD_SLAST>>

pub fn slast(&mut self) -> SLAST_W

Bits 0:31 - Last Source Address Adjustment

impl W<u32, Reg<u32, _TCD_DADDR>>

pub fn daddr(&mut self) -> DADDR_W

Bits 0:31 - Destination Address

impl W<u16, Reg<u16, _TCD_DOFF>>

pub fn doff(&mut self) -> DOFF_W

Bits 0:15 - Destination Address Signed Offset

impl W<u16, Reg<u16, _TCD_CITER_ELINKNO>>

pub fn citer(&mut self) -> CITER_W

Bits 0:14 - Current Major Iteration Count

pub fn elink(&mut self) -> ELINK_W

Bit 15 - Enable channel-to-channel linking on minor-loop complete

impl W<u16, Reg<u16, _TCD_CITER_ELINKYES>>

pub fn citer_le(&mut self) -> CITER_LE_W

Bits 0:8 - Current Major Iteration Count

pub fn linkch(&mut self) -> LINKCH_W

Bits 9:12 - Minor Loop Link Channel Number

pub fn elink(&mut self) -> ELINK_W

Bit 15 - Enable channel-to-channel linking on minor-loop complete

impl W<u32, Reg<u32, _TCD_DLASTSGA>>

pub fn dlastsga(&mut self) -> DLASTSGA_W

Bits 0:31 - DLASTSGA

impl W<u16, Reg<u16, _TCD_CSR>>

pub fn start(&mut self) -> START_W

Bit 0 - Channel Start

pub fn intmajor(&mut self) -> INTMAJOR_W

Bit 1 - Enable an interrupt when major iteration count completes.

pub fn inthalf(&mut self) -> INTHALF_W

Bit 2 - Enable an interrupt when major counter is half complete.

pub fn dreq(&mut self) -> DREQ_W

Bit 3 - Disable Request

pub fn esg(&mut self) -> ESG_W

Bit 4 - Enable Scatter/Gather Processing

pub fn majorelink(&mut self) -> MAJORELINK_W

Bit 5 - Enable channel-to-channel linking on major loop complete

pub fn active(&mut self) -> ACTIVE_W

Bit 6 - Channel Active

pub fn done(&mut self) -> DONE_W

Bit 7 - Channel Done

pub fn majorlinkch(&mut self) -> MAJORLINKCH_W

Bits 8:11 - Major Loop Link Channel Number

pub fn bwc(&mut self) -> BWC_W

Bits 14:15 - Bandwidth Control

impl W<u16, Reg<u16, _TCD_BITER_ELINKNO>>

pub fn biter(&mut self) -> BITER_W

Bits 0:14 - Starting Major Iteration Count

pub fn elink(&mut self) -> ELINK_W

Bit 15 - Enables channel-to-channel linking on minor loop complete

impl W<u16, Reg<u16, _TCD_BITER_ELINKYES>>

pub fn biter(&mut self) -> BITER_W

Bits 0:8 - Starting major iteration count

pub fn linkch(&mut self) -> LINKCH_W

Bits 9:12 - Link Channel Number

pub fn elink(&mut self) -> ELINK_W

Bit 15 - Enables channel-to-channel linking on minor loop complete

impl W<u32, Reg<u32, _CR0>>

pub fn encie1(&mut self) -> ENCIE1_W

Bit 26 - ENCIE1

pub fn escie1(&mut self) -> ESCIE1_W

Bit 27 - ESCIE1

pub fn encie0(&mut self) -> ENCIE0_W

Bit 30 - ENCIE0

pub fn escie0(&mut self) -> ESCIE0_W

Bit 31 - ESCIE0

impl W<u32, Reg<u32, _SR0>>

pub fn nce1(&mut self) -> NCE1_W

Bit 26 - NCE1

pub fn sbc1(&mut self) -> SBC1_W

Bit 27 - SBC1

pub fn nce0(&mut self) -> NCE0_W

Bit 30 - NCE0

pub fn sbc0(&mut self) -> SBC0_W

Bit 31 - SBC0

impl W<u32, Reg<u32, _EIMCR>>

pub fn geien(&mut self) -> GEIEN_W

Bit 0 - Global Error Injection Enable

impl W<u32, Reg<u32, _EICHEN>>

pub fn eich1en(&mut self) -> EICH1EN_W

Bit 30 - Error Injection Channel 1 Enable

pub fn eich0en(&mut self) -> EICH0EN_W

Bit 31 - Error Injection Channel 0 Enable

impl W<u32, Reg<u32, _EICHD0_WORD0>>

pub fn chkbit_mask(&mut self) -> CHKBIT_MASK_W

Bits 25:31 - Checkbit Mask

impl W<u32, Reg<u32, _EICHD0_WORD1>>

pub fn b0_3data_mask(&mut self) -> B0_3DATA_MASK_W

Bits 0:31 - Data Mask Bytes 0-3

impl W<u32, Reg<u32, _EICHD1_WORD0>>

pub fn chkbit_mask(&mut self) -> CHKBIT_MASK_W

Bits 25:31 - Checkbit Mask

impl W<u32, Reg<u32, _EICHD1_WORD1>>

pub fn b0_3data_mask(&mut self) -> B0_3DATA_MASK_W

Bits 0:31 - Data Mask Bytes 0-3

impl W<u8, Reg<u8, _FSTAT>>

pub fn fpviol(&mut self) -> FPVIOL_W

Bit 4 - Flash Protection Violation Flag

pub fn accerr(&mut self) -> ACCERR_W

Bit 5 - Flash Access Error Flag

pub fn rdcolerr(&mut self) -> RDCOLERR_W

Bit 6 - FTFC Read Collision Error Flag

pub fn ccif(&mut self) -> CCIF_W

Bit 7 - Command Complete Interrupt Flag

impl W<u8, Reg<u8, _FCNFG>>

pub fn erssusp(&mut self) -> ERSSUSP_W

Bit 4 - Erase Suspend

pub fn rdcollie(&mut self) -> RDCOLLIE_W

Bit 6 - Read Collision Error Interrupt Enable

pub fn ccie(&mut self) -> CCIE_W

Bit 7 - Command Complete Interrupt Enable

impl W<u8, Reg<u8, _FCCOB3>>

pub fn ccobn(&mut self) -> CCOBN_W

Bits 0:7 - CCOBn

impl W<u8, Reg<u8, _FCCOB2>>

pub fn ccobn(&mut self) -> CCOBN_W

Bits 0:7 - CCOBn

impl W<u8, Reg<u8, _FCCOB1>>

pub fn ccobn(&mut self) -> CCOBN_W

Bits 0:7 - CCOBn

impl W<u8, Reg<u8, _FCCOB0>>

pub fn ccobn(&mut self) -> CCOBN_W

Bits 0:7 - CCOBn

impl W<u8, Reg<u8, _FCCOB7>>

pub fn ccobn(&mut self) -> CCOBN_W

Bits 0:7 - CCOBn

impl W<u8, Reg<u8, _FCCOB6>>

pub fn ccobn(&mut self) -> CCOBN_W

Bits 0:7 - CCOBn

impl W<u8, Reg<u8, _FCCOB5>>

pub fn ccobn(&mut self) -> CCOBN_W

Bits 0:7 - CCOBn

impl W<u8, Reg<u8, _FCCOB4>>

pub fn ccobn(&mut self) -> CCOBN_W

Bits 0:7 - CCOBn

impl W<u8, Reg<u8, _FCCOBB>>

pub fn ccobn(&mut self) -> CCOBN_W

Bits 0:7 - CCOBn

impl W<u8, Reg<u8, _FCCOBA>>

pub fn ccobn(&mut self) -> CCOBN_W

Bits 0:7 - CCOBn

impl W<u8, Reg<u8, _FCCOB9>>

pub fn ccobn(&mut self) -> CCOBN_W

Bits 0:7 - CCOBn

impl W<u8, Reg<u8, _FCCOB8>>

pub fn ccobn(&mut self) -> CCOBN_W

Bits 0:7 - CCOBn

impl W<u8, Reg<u8, _FPROT3>>

pub fn prot(&mut self) -> PROT_W

Bits 0:7 - Program Flash Region Protect

impl W<u8, Reg<u8, _FPROT2>>

pub fn prot(&mut self) -> PROT_W

Bits 0:7 - Program Flash Region Protect

impl W<u8, Reg<u8, _FPROT1>>

pub fn prot(&mut self) -> PROT_W

Bits 0:7 - Program Flash Region Protect

impl W<u8, Reg<u8, _FPROT0>>

pub fn prot(&mut self) -> PROT_W

Bits 0:7 - Program Flash Region Protect

impl W<u8, Reg<u8, _FEPROT>>

pub fn eprot(&mut self) -> EPROT_W

Bits 0:7 - EEPROM Region Protect

impl W<u8, Reg<u8, _FDPROT>>

pub fn dprot(&mut self) -> DPROT_W

Bits 0:7 - Data Flash Region Protect

impl W<u8, Reg<u8, _FERSTAT>>

pub fn dfdif(&mut self) -> DFDIF_W

Bit 1 - Double Bit Fault Detect Interrupt Flag

impl W<u8, Reg<u8, _FERCNFG>>

pub fn dfdie(&mut self) -> DFDIE_W

Bit 1 - Double Bit Fault Detect Interrupt Enable

pub fn fdfd(&mut self) -> FDFD_W

Bit 5 - Force Double Bit Fault Detect

impl W<u8, Reg<u8, _CHCFG>>

pub fn source(&mut self) -> SOURCE_W

Bits 0:5 - DMA Channel Source (Slot)

pub fn trig(&mut self) -> TRIG_W

Bit 6 - DMA Channel Trigger Enable

pub fn enbl(&mut self) -> ENBL_W

Bit 7 - DMA Channel Enable

impl W<u32, Reg<u32, _MCR>>

pub fn maxmb(&mut self) -> MAXMB_W

Bits 0:6 - Number Of The Last Message Buffer

pub fn idam(&mut self) -> IDAM_W

Bits 8:9 - ID Acceptance Mode

pub fn fden(&mut self) -> FDEN_W

Bit 11 - CAN FD operation enable

pub fn aen(&mut self) -> AEN_W

Bit 12 - Abort Enable

pub fn lprioen(&mut self) -> LPRIOEN_W

Bit 13 - Local Priority Enable

pub fn pnet_en(&mut self) -> PNET_EN_W

Bit 14 - Pretended Networking Enable

pub fn dma(&mut self) -> DMA_W

Bit 15 - DMA Enable

pub fn irmq(&mut self) -> IRMQ_W

Bit 16 - Individual Rx Masking And Queue Enable

pub fn srxdis(&mut self) -> SRXDIS_W

Bit 17 - Self Reception Disable

pub fn wrnen(&mut self) -> WRNEN_W

Bit 21 - Warning Interrupt Enable

pub fn supv(&mut self) -> SUPV_W

Bit 23 - Supervisor Mode

pub fn softrst(&mut self) -> SOFTRST_W

Bit 25 - Soft Reset

pub fn halt(&mut self) -> HALT_W

Bit 28 - Halt FlexCAN

pub fn rfen(&mut self) -> RFEN_W

Bit 29 - Rx FIFO Enable

pub fn frz(&mut self) -> FRZ_W

Bit 30 - Freeze Enable

pub fn mdis(&mut self) -> MDIS_W

Bit 31 - Module Disable

impl W<u32, Reg<u32, _CTRL1>>

pub fn propseg(&mut self) -> PROPSEG_W

Bits 0:2 - Propagation Segment

pub fn lom(&mut self) -> LOM_W

Bit 3 - Listen-Only Mode

pub fn lbuf(&mut self) -> LBUF_W

Bit 4 - Lowest Buffer Transmitted First

pub fn tsyn(&mut self) -> TSYN_W

Bit 5 - Timer Sync

pub fn boffrec(&mut self) -> BOFFREC_W

Bit 6 - Bus Off Recovery

pub fn smp(&mut self) -> SMP_W

Bit 7 - CAN Bit Sampling

pub fn rwrnmsk(&mut self) -> RWRNMSK_W

Bit 10 - Rx Warning Interrupt Mask

pub fn twrnmsk(&mut self) -> TWRNMSK_W

Bit 11 - Tx Warning Interrupt Mask

pub fn lpb(&mut self) -> LPB_W

Bit 12 - Loop Back Mode

pub fn clksrc(&mut self) -> CLKSRC_W

Bit 13 - CAN Engine Clock Source

pub fn errmsk(&mut self) -> ERRMSK_W

Bit 14 - Error Interrupt Mask

pub fn boffmsk(&mut self) -> BOFFMSK_W

Bit 15 - Bus Off Interrupt Mask

pub fn pseg2(&mut self) -> PSEG2_W

Bits 16:18 - Phase Segment 2

pub fn pseg1(&mut self) -> PSEG1_W

Bits 19:21 - Phase Segment 1

pub fn rjw(&mut self) -> RJW_W

Bits 22:23 - Resync Jump Width

pub fn presdiv(&mut self) -> PRESDIV_W

Bits 24:31 - Prescaler Division Factor

impl W<u32, Reg<u32, _TIMER>>

pub fn timer(&mut self) -> TIMER_W

Bits 0:15 - Timer Value

impl W<u32, Reg<u32, _RXMGMASK>>

pub fn mg(&mut self) -> MG_W

Bits 0:31 - Rx Mailboxes Global Mask Bits

impl W<u32, Reg<u32, _RX14MASK>>

pub fn rx14m(&mut self) -> RX14M_W

Bits 0:31 - Rx Buffer 14 Mask Bits

impl W<u32, Reg<u32, _RX15MASK>>

pub fn rx15m(&mut self) -> RX15M_W

Bits 0:31 - Rx Buffer 15 Mask Bits

impl W<u32, Reg<u32, _ECR>>

pub fn txerrcnt(&mut self) -> TXERRCNT_W

Bits 0:7 - Transmit Error Counter

pub fn rxerrcnt(&mut self) -> RXERRCNT_W

Bits 8:15 - Receive Error Counter

pub fn txerrcnt_fast(&mut self) -> TXERRCNT_FAST_W

Bits 16:23 - Transmit Error Counter for fast bits

pub fn rxerrcnt_fast(&mut self) -> RXERRCNT_FAST_W

Bits 24:31 - Receive Error Counter for fast bits

impl W<u32, Reg<u32, _ESR1>>

pub fn errint(&mut self) -> ERRINT_W

Bit 1 - Error Interrupt

pub fn boffint(&mut self) -> BOFFINT_W

Bit 2 - Bus Off Interrupt

pub fn rwrnint(&mut self) -> RWRNINT_W

Bit 16 - Rx Warning Interrupt Flag

pub fn twrnint(&mut self) -> TWRNINT_W

Bit 17 - Tx Warning Interrupt Flag

pub fn boffdoneint(&mut self) -> BOFFDONEINT_W

Bit 19 - Bus Off Done Interrupt

pub fn errint_fast(&mut self) -> ERRINT_FAST_W

Bit 20 - Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set

pub fn errovr(&mut self) -> ERROVR_W

Bit 21 - Error Overrun bit

impl W<u32, Reg<u32, _IMASK1>>

pub fn buf31to0m(&mut self) -> BUF31TO0M_W

Bits 0:31 - Buffer MB i Mask

impl W<u32, Reg<u32, _IFLAG1>>

pub fn buf0i(&mut self) -> BUF0I_W

Bit 0 - Buffer MB0 Interrupt Or Clear FIFO bit

pub fn buf4to1i(&mut self) -> BUF4TO1I_W

Bits 1:4 - Buffer MB i Interrupt Or "reserved"

pub fn buf5i(&mut self) -> BUF5I_W

Bit 5 - Buffer MB5 Interrupt Or "Frames available in Rx FIFO"

pub fn buf6i(&mut self) -> BUF6I_W

Bit 6 - Buffer MB6 Interrupt Or "Rx FIFO Warning"

pub fn buf7i(&mut self) -> BUF7I_W

Bit 7 - Buffer MB7 Interrupt Or "Rx FIFO Overflow"

pub fn buf31to8i(&mut self) -> BUF31TO8I_W

Bits 8:31 - Buffer MBi Interrupt

impl W<u32, Reg<u32, _CTRL2>>

pub fn edfltdis(&mut self) -> EDFLTDIS_W

Bit 11 - Edge Filter Disable

pub fn isocanfden(&mut self) -> ISOCANFDEN_W

Bit 12 - ISO CAN FD Enable

pub fn prexcen(&mut self) -> PREXCEN_W

Bit 14 - Protocol Exception Enable

pub fn timer_src(&mut self) -> TIMER_SRC_W

Bit 15 - Timer Source

pub fn eacen(&mut self) -> EACEN_W

Bit 16 - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes

pub fn rrs(&mut self) -> RRS_W

Bit 17 - Remote Request Storing

pub fn mrp(&mut self) -> MRP_W

Bit 18 - Mailboxes Reception Priority

pub fn tasd(&mut self) -> TASD_W

Bits 19:23 - Tx Arbitration Start Delay

pub fn rffn(&mut self) -> RFFN_W

Bits 24:27 - Number Of Rx FIFO Filters

pub fn boffdonemsk(&mut self) -> BOFFDONEMSK_W

Bit 30 - Bus Off Done Interrupt Mask

pub fn errmsk_fast(&mut self) -> ERRMSK_FAST_W

Bit 31 - Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames

impl W<u32, Reg<u32, _RXFGMASK>>

pub fn fgm(&mut self) -> FGM_W

Bits 0:31 - Rx FIFO Global Mask Bits

impl W<u32, Reg<u32, _CBT>>

pub fn epseg2(&mut self) -> EPSEG2_W

Bits 0:4 - Extended Phase Segment 2

pub fn epseg1(&mut self) -> EPSEG1_W

Bits 5:9 - Extended Phase Segment 1

pub fn epropseg(&mut self) -> EPROPSEG_W

Bits 10:15 - Extended Propagation Segment

pub fn erjw(&mut self) -> ERJW_W

Bits 16:20 - Extended Resync Jump Width

pub fn epresdiv(&mut self) -> EPRESDIV_W

Bits 21:30 - Extended Prescaler Division Factor

pub fn btf(&mut self) -> BTF_W

Bit 31 - Bit Timing Format Enable

impl W<u32, Reg<u32, _EMBEDDEDRAM>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _RXIMR>>

pub fn mi(&mut self) -> MI_W

Bits 0:31 - Individual Mask Bits

impl W<u32, Reg<u32, _CTRL1_PN>>

pub fn fcs(&mut self) -> FCS_W

Bits 0:1 - Filtering Combination Selection

pub fn idfs(&mut self) -> IDFS_W

Bits 2:3 - ID Filtering Selection

pub fn plfs(&mut self) -> PLFS_W

Bits 4:5 - Payload Filtering Selection

pub fn nmatch(&mut self) -> NMATCH_W

Bits 8:15 - Number of Messages Matching the Same Filtering Criteria

pub fn wumf_msk(&mut self) -> WUMF_MSK_W

Bit 16 - Wake Up by Match Flag Mask Bit

pub fn wtof_msk(&mut self) -> WTOF_MSK_W

Bit 17 - Wake Up by Timeout Flag Mask Bit

impl W<u32, Reg<u32, _CTRL2_PN>>

pub fn matchto(&mut self) -> MATCHTO_W

Bits 0:15 - Timeout for No Message Matching the Filtering Criteria

impl W<u32, Reg<u32, _WU_MTC>>

pub fn wumf(&mut self) -> WUMF_W

Bit 16 - Wake Up by Match Flag Bit

pub fn wtof(&mut self) -> WTOF_W

Bit 17 - Wake Up by Timeout Flag Bit

impl W<u32, Reg<u32, _FLT_ID1>>

pub fn flt_id1(&mut self) -> FLT_ID1_W

Bits 0:28 - ID Filter 1 for Pretended Networking filtering

pub fn flt_rtr(&mut self) -> FLT_RTR_W

Bit 29 - Remote Transmission Request Filter

pub fn flt_ide(&mut self) -> FLT_IDE_W

Bit 30 - ID Extended Filter

impl W<u32, Reg<u32, _FLT_DLC>>

pub fn flt_dlc_hi(&mut self) -> FLT_DLC_HI_W

Bits 0:3 - Upper Limit for Length of Data Bytes Filter

pub fn flt_dlc_lo(&mut self) -> FLT_DLC_LO_W

Bits 16:19 - Lower Limit for Length of Data Bytes Filter

impl W<u32, Reg<u32, _PL1_LO>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 3.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 2.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 1.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 0.

impl W<u32, Reg<u32, _PL1_HI>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 7.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 6.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 5.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 4.

impl W<u32, Reg<u32, _FLT_ID2_IDMASK>>

pub fn flt_id2_idmask(&mut self) -> FLT_ID2_IDMASK_W

Bits 0:28 - ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering

pub fn rtr_msk(&mut self) -> RTR_MSK_W

Bit 29 - Remote Transmission Request Mask Bit

pub fn ide_msk(&mut self) -> IDE_MSK_W

Bit 30 - ID Extended Mask Bit

impl W<u32, Reg<u32, _PL2_PLMASK_LO>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 3.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 2.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 1.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 0.

impl W<u32, Reg<u32, _PL2_PLMASK_HI>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 7.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 6.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 5.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 4.

impl W<u32, Reg<u32, _FDCTRL>>

pub fn tdcoff(&mut self) -> TDCOFF_W

Bits 8:12 - Transceiver Delay Compensation Offset

pub fn tdcfail(&mut self) -> TDCFAIL_W

Bit 14 - Transceiver Delay Compensation Fail

pub fn tdcen(&mut self) -> TDCEN_W

Bit 15 - Transceiver Delay Compensation Enable

pub fn mbdsr0(&mut self) -> MBDSR0_W

Bits 16:17 - Message Buffer Data Size for Region 0

pub fn fdrate(&mut self) -> FDRATE_W

Bit 31 - Bit Rate Switch Enable

impl W<u32, Reg<u32, _FDCBT>>

pub fn fpseg2(&mut self) -> FPSEG2_W

Bits 0:2 - Fast Phase Segment 2

pub fn fpseg1(&mut self) -> FPSEG1_W

Bits 5:7 - Fast Phase Segment 1

pub fn fpropseg(&mut self) -> FPROPSEG_W

Bits 10:14 - Fast Propagation Segment

pub fn frjw(&mut self) -> FRJW_W

Bits 16:18 - Fast Resync Jump Width

pub fn fpresdiv(&mut self) -> FPRESDIV_W

Bits 20:29 - Fast Prescaler Division Factor

impl W<u32, Reg<u32, _MCR>>

pub fn maxmb(&mut self) -> MAXMB_W

Bits 0:6 - Number Of The Last Message Buffer

pub fn idam(&mut self) -> IDAM_W

Bits 8:9 - ID Acceptance Mode

pub fn fden(&mut self) -> FDEN_W

Bit 11 - CAN FD operation enable

pub fn aen(&mut self) -> AEN_W

Bit 12 - Abort Enable

pub fn lprioen(&mut self) -> LPRIOEN_W

Bit 13 - Local Priority Enable

pub fn pnet_en(&mut self) -> PNET_EN_W

Bit 14 - Pretended Networking Enable

pub fn dma(&mut self) -> DMA_W

Bit 15 - DMA Enable

pub fn irmq(&mut self) -> IRMQ_W

Bit 16 - Individual Rx Masking And Queue Enable

pub fn srxdis(&mut self) -> SRXDIS_W

Bit 17 - Self Reception Disable

pub fn wrnen(&mut self) -> WRNEN_W

Bit 21 - Warning Interrupt Enable

pub fn supv(&mut self) -> SUPV_W

Bit 23 - Supervisor Mode

pub fn softrst(&mut self) -> SOFTRST_W

Bit 25 - Soft Reset

pub fn halt(&mut self) -> HALT_W

Bit 28 - Halt FlexCAN

pub fn rfen(&mut self) -> RFEN_W

Bit 29 - Rx FIFO Enable

pub fn frz(&mut self) -> FRZ_W

Bit 30 - Freeze Enable

pub fn mdis(&mut self) -> MDIS_W

Bit 31 - Module Disable

impl W<u32, Reg<u32, _CTRL1>>

pub fn propseg(&mut self) -> PROPSEG_W

Bits 0:2 - Propagation Segment

pub fn lom(&mut self) -> LOM_W

Bit 3 - Listen-Only Mode

pub fn lbuf(&mut self) -> LBUF_W

Bit 4 - Lowest Buffer Transmitted First

pub fn tsyn(&mut self) -> TSYN_W

Bit 5 - Timer Sync

pub fn boffrec(&mut self) -> BOFFREC_W

Bit 6 - Bus Off Recovery

pub fn smp(&mut self) -> SMP_W

Bit 7 - CAN Bit Sampling

pub fn rwrnmsk(&mut self) -> RWRNMSK_W

Bit 10 - Rx Warning Interrupt Mask

pub fn twrnmsk(&mut self) -> TWRNMSK_W

Bit 11 - Tx Warning Interrupt Mask

pub fn lpb(&mut self) -> LPB_W

Bit 12 - Loop Back Mode

pub fn clksrc(&mut self) -> CLKSRC_W

Bit 13 - CAN Engine Clock Source

pub fn errmsk(&mut self) -> ERRMSK_W

Bit 14 - Error Interrupt Mask

pub fn boffmsk(&mut self) -> BOFFMSK_W

Bit 15 - Bus Off Interrupt Mask

pub fn pseg2(&mut self) -> PSEG2_W

Bits 16:18 - Phase Segment 2

pub fn pseg1(&mut self) -> PSEG1_W

Bits 19:21 - Phase Segment 1

pub fn rjw(&mut self) -> RJW_W

Bits 22:23 - Resync Jump Width

pub fn presdiv(&mut self) -> PRESDIV_W

Bits 24:31 - Prescaler Division Factor

impl W<u32, Reg<u32, _TIMER>>

pub fn timer(&mut self) -> TIMER_W

Bits 0:15 - Timer Value

impl W<u32, Reg<u32, _RXMGMASK>>

pub fn mg(&mut self) -> MG_W

Bits 0:31 - Rx Mailboxes Global Mask Bits

impl W<u32, Reg<u32, _RX14MASK>>

pub fn rx14m(&mut self) -> RX14M_W

Bits 0:31 - Rx Buffer 14 Mask Bits

impl W<u32, Reg<u32, _RX15MASK>>

pub fn rx15m(&mut self) -> RX15M_W

Bits 0:31 - Rx Buffer 15 Mask Bits

impl W<u32, Reg<u32, _ECR>>

pub fn txerrcnt(&mut self) -> TXERRCNT_W

Bits 0:7 - Transmit Error Counter

pub fn rxerrcnt(&mut self) -> RXERRCNT_W

Bits 8:15 - Receive Error Counter

pub fn txerrcnt_fast(&mut self) -> TXERRCNT_FAST_W

Bits 16:23 - Transmit Error Counter for fast bits

pub fn rxerrcnt_fast(&mut self) -> RXERRCNT_FAST_W

Bits 24:31 - Receive Error Counter for fast bits

impl W<u32, Reg<u32, _ESR1>>

pub fn errint(&mut self) -> ERRINT_W

Bit 1 - Error Interrupt

pub fn boffint(&mut self) -> BOFFINT_W

Bit 2 - Bus Off Interrupt

pub fn rwrnint(&mut self) -> RWRNINT_W

Bit 16 - Rx Warning Interrupt Flag

pub fn twrnint(&mut self) -> TWRNINT_W

Bit 17 - Tx Warning Interrupt Flag

pub fn boffdoneint(&mut self) -> BOFFDONEINT_W

Bit 19 - Bus Off Done Interrupt

pub fn errint_fast(&mut self) -> ERRINT_FAST_W

Bit 20 - Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set

pub fn errovr(&mut self) -> ERROVR_W

Bit 21 - Error Overrun bit

impl W<u32, Reg<u32, _IMASK1>>

pub fn buf31to0m(&mut self) -> BUF31TO0M_W

Bits 0:31 - Buffer MB i Mask

impl W<u32, Reg<u32, _IFLAG1>>

pub fn buf0i(&mut self) -> BUF0I_W

Bit 0 - Buffer MB0 Interrupt Or Clear FIFO bit

pub fn buf4to1i(&mut self) -> BUF4TO1I_W

Bits 1:4 - Buffer MB i Interrupt Or "reserved"

pub fn buf5i(&mut self) -> BUF5I_W

Bit 5 - Buffer MB5 Interrupt Or "Frames available in Rx FIFO"

pub fn buf6i(&mut self) -> BUF6I_W

Bit 6 - Buffer MB6 Interrupt Or "Rx FIFO Warning"

pub fn buf7i(&mut self) -> BUF7I_W

Bit 7 - Buffer MB7 Interrupt Or "Rx FIFO Overflow"

pub fn buf31to8i(&mut self) -> BUF31TO8I_W

Bits 8:31 - Buffer MBi Interrupt

impl W<u32, Reg<u32, _CTRL2>>

pub fn edfltdis(&mut self) -> EDFLTDIS_W

Bit 11 - Edge Filter Disable

pub fn isocanfden(&mut self) -> ISOCANFDEN_W

Bit 12 - ISO CAN FD Enable

pub fn prexcen(&mut self) -> PREXCEN_W

Bit 14 - Protocol Exception Enable

pub fn timer_src(&mut self) -> TIMER_SRC_W

Bit 15 - Timer Source

pub fn eacen(&mut self) -> EACEN_W

Bit 16 - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes

pub fn rrs(&mut self) -> RRS_W

Bit 17 - Remote Request Storing

pub fn mrp(&mut self) -> MRP_W

Bit 18 - Mailboxes Reception Priority

pub fn tasd(&mut self) -> TASD_W

Bits 19:23 - Tx Arbitration Start Delay

pub fn rffn(&mut self) -> RFFN_W

Bits 24:27 - Number Of Rx FIFO Filters

pub fn boffdonemsk(&mut self) -> BOFFDONEMSK_W

Bit 30 - Bus Off Done Interrupt Mask

pub fn errmsk_fast(&mut self) -> ERRMSK_FAST_W

Bit 31 - Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames

impl W<u32, Reg<u32, _RXFGMASK>>

pub fn fgm(&mut self) -> FGM_W

Bits 0:31 - Rx FIFO Global Mask Bits

impl W<u32, Reg<u32, _CBT>>

pub fn epseg2(&mut self) -> EPSEG2_W

Bits 0:4 - Extended Phase Segment 2

pub fn epseg1(&mut self) -> EPSEG1_W

Bits 5:9 - Extended Phase Segment 1

pub fn epropseg(&mut self) -> EPROPSEG_W

Bits 10:15 - Extended Propagation Segment

pub fn erjw(&mut self) -> ERJW_W

Bits 16:20 - Extended Resync Jump Width

pub fn epresdiv(&mut self) -> EPRESDIV_W

Bits 21:30 - Extended Prescaler Division Factor

pub fn btf(&mut self) -> BTF_W

Bit 31 - Bit Timing Format Enable

impl W<u32, Reg<u32, _EMBEDDEDRAM>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _RXIMR>>

pub fn mi(&mut self) -> MI_W

Bits 0:31 - Individual Mask Bits

impl W<u32, Reg<u32, _CTRL1_PN>>

pub fn fcs(&mut self) -> FCS_W

Bits 0:1 - Filtering Combination Selection

pub fn idfs(&mut self) -> IDFS_W

Bits 2:3 - ID Filtering Selection

pub fn plfs(&mut self) -> PLFS_W

Bits 4:5 - Payload Filtering Selection

pub fn nmatch(&mut self) -> NMATCH_W

Bits 8:15 - Number of Messages Matching the Same Filtering Criteria

pub fn wumf_msk(&mut self) -> WUMF_MSK_W

Bit 16 - Wake Up by Match Flag Mask Bit

pub fn wtof_msk(&mut self) -> WTOF_MSK_W

Bit 17 - Wake Up by Timeout Flag Mask Bit

impl W<u32, Reg<u32, _CTRL2_PN>>

pub fn matchto(&mut self) -> MATCHTO_W

Bits 0:15 - Timeout for No Message Matching the Filtering Criteria

impl W<u32, Reg<u32, _WU_MTC>>

pub fn wumf(&mut self) -> WUMF_W

Bit 16 - Wake Up by Match Flag Bit

pub fn wtof(&mut self) -> WTOF_W

Bit 17 - Wake Up by Timeout Flag Bit

impl W<u32, Reg<u32, _FLT_ID1>>

pub fn flt_id1(&mut self) -> FLT_ID1_W

Bits 0:28 - ID Filter 1 for Pretended Networking filtering

pub fn flt_rtr(&mut self) -> FLT_RTR_W

Bit 29 - Remote Transmission Request Filter

pub fn flt_ide(&mut self) -> FLT_IDE_W

Bit 30 - ID Extended Filter

impl W<u32, Reg<u32, _FLT_DLC>>

pub fn flt_dlc_hi(&mut self) -> FLT_DLC_HI_W

Bits 0:3 - Upper Limit for Length of Data Bytes Filter

pub fn flt_dlc_lo(&mut self) -> FLT_DLC_LO_W

Bits 16:19 - Lower Limit for Length of Data Bytes Filter

impl W<u32, Reg<u32, _PL1_LO>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 3.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 2.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 1.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 0.

impl W<u32, Reg<u32, _PL1_HI>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 7.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 6.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 5.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 4.

impl W<u32, Reg<u32, _FLT_ID2_IDMASK>>

pub fn flt_id2_idmask(&mut self) -> FLT_ID2_IDMASK_W

Bits 0:28 - ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering

pub fn rtr_msk(&mut self) -> RTR_MSK_W

Bit 29 - Remote Transmission Request Mask Bit

pub fn ide_msk(&mut self) -> IDE_MSK_W

Bit 30 - ID Extended Mask Bit

impl W<u32, Reg<u32, _PL2_PLMASK_LO>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 3.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 2.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 1.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 0.

impl W<u32, Reg<u32, _PL2_PLMASK_HI>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 7.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 6.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 5.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 4.

impl W<u32, Reg<u32, _FDCTRL>>

pub fn tdcoff(&mut self) -> TDCOFF_W

Bits 8:12 - Transceiver Delay Compensation Offset

pub fn tdcfail(&mut self) -> TDCFAIL_W

Bit 14 - Transceiver Delay Compensation Fail

pub fn tdcen(&mut self) -> TDCEN_W

Bit 15 - Transceiver Delay Compensation Enable

pub fn mbdsr0(&mut self) -> MBDSR0_W

Bits 16:17 - Message Buffer Data Size for Region 0

pub fn fdrate(&mut self) -> FDRATE_W

Bit 31 - Bit Rate Switch Enable

impl W<u32, Reg<u32, _FDCBT>>

pub fn fpseg2(&mut self) -> FPSEG2_W

Bits 0:2 - Fast Phase Segment 2

pub fn fpseg1(&mut self) -> FPSEG1_W

Bits 5:7 - Fast Phase Segment 1

pub fn fpropseg(&mut self) -> FPROPSEG_W

Bits 10:14 - Fast Propagation Segment

pub fn frjw(&mut self) -> FRJW_W

Bits 16:18 - Fast Resync Jump Width

pub fn fpresdiv(&mut self) -> FPRESDIV_W

Bits 20:29 - Fast Prescaler Division Factor

impl W<u32, Reg<u32, _MCR>>

pub fn maxmb(&mut self) -> MAXMB_W

Bits 0:6 - Number Of The Last Message Buffer

pub fn idam(&mut self) -> IDAM_W

Bits 8:9 - ID Acceptance Mode

pub fn fden(&mut self) -> FDEN_W

Bit 11 - CAN FD operation enable

pub fn aen(&mut self) -> AEN_W

Bit 12 - Abort Enable

pub fn lprioen(&mut self) -> LPRIOEN_W

Bit 13 - Local Priority Enable

pub fn pnet_en(&mut self) -> PNET_EN_W

Bit 14 - Pretended Networking Enable

pub fn dma(&mut self) -> DMA_W

Bit 15 - DMA Enable

pub fn irmq(&mut self) -> IRMQ_W

Bit 16 - Individual Rx Masking And Queue Enable

pub fn srxdis(&mut self) -> SRXDIS_W

Bit 17 - Self Reception Disable

pub fn wrnen(&mut self) -> WRNEN_W

Bit 21 - Warning Interrupt Enable

pub fn supv(&mut self) -> SUPV_W

Bit 23 - Supervisor Mode

pub fn softrst(&mut self) -> SOFTRST_W

Bit 25 - Soft Reset

pub fn halt(&mut self) -> HALT_W

Bit 28 - Halt FlexCAN

pub fn rfen(&mut self) -> RFEN_W

Bit 29 - Rx FIFO Enable

pub fn frz(&mut self) -> FRZ_W

Bit 30 - Freeze Enable

pub fn mdis(&mut self) -> MDIS_W

Bit 31 - Module Disable

impl W<u32, Reg<u32, _CTRL1>>

pub fn propseg(&mut self) -> PROPSEG_W

Bits 0:2 - Propagation Segment

pub fn lom(&mut self) -> LOM_W

Bit 3 - Listen-Only Mode

pub fn lbuf(&mut self) -> LBUF_W

Bit 4 - Lowest Buffer Transmitted First

pub fn tsyn(&mut self) -> TSYN_W

Bit 5 - Timer Sync

pub fn boffrec(&mut self) -> BOFFREC_W

Bit 6 - Bus Off Recovery

pub fn smp(&mut self) -> SMP_W

Bit 7 - CAN Bit Sampling

pub fn rwrnmsk(&mut self) -> RWRNMSK_W

Bit 10 - Rx Warning Interrupt Mask

pub fn twrnmsk(&mut self) -> TWRNMSK_W

Bit 11 - Tx Warning Interrupt Mask

pub fn lpb(&mut self) -> LPB_W

Bit 12 - Loop Back Mode

pub fn clksrc(&mut self) -> CLKSRC_W

Bit 13 - CAN Engine Clock Source

pub fn errmsk(&mut self) -> ERRMSK_W

Bit 14 - Error Interrupt Mask

pub fn boffmsk(&mut self) -> BOFFMSK_W

Bit 15 - Bus Off Interrupt Mask

pub fn pseg2(&mut self) -> PSEG2_W

Bits 16:18 - Phase Segment 2

pub fn pseg1(&mut self) -> PSEG1_W

Bits 19:21 - Phase Segment 1

pub fn rjw(&mut self) -> RJW_W

Bits 22:23 - Resync Jump Width

pub fn presdiv(&mut self) -> PRESDIV_W

Bits 24:31 - Prescaler Division Factor

impl W<u32, Reg<u32, _TIMER>>

pub fn timer(&mut self) -> TIMER_W

Bits 0:15 - Timer Value

impl W<u32, Reg<u32, _RXMGMASK>>

pub fn mg(&mut self) -> MG_W

Bits 0:31 - Rx Mailboxes Global Mask Bits

impl W<u32, Reg<u32, _RX14MASK>>

pub fn rx14m(&mut self) -> RX14M_W

Bits 0:31 - Rx Buffer 14 Mask Bits

impl W<u32, Reg<u32, _RX15MASK>>

pub fn rx15m(&mut self) -> RX15M_W

Bits 0:31 - Rx Buffer 15 Mask Bits

impl W<u32, Reg<u32, _ECR>>

pub fn txerrcnt(&mut self) -> TXERRCNT_W

Bits 0:7 - Transmit Error Counter

pub fn rxerrcnt(&mut self) -> RXERRCNT_W

Bits 8:15 - Receive Error Counter

pub fn txerrcnt_fast(&mut self) -> TXERRCNT_FAST_W

Bits 16:23 - Transmit Error Counter for fast bits

pub fn rxerrcnt_fast(&mut self) -> RXERRCNT_FAST_W

Bits 24:31 - Receive Error Counter for fast bits

impl W<u32, Reg<u32, _ESR1>>

pub fn errint(&mut self) -> ERRINT_W

Bit 1 - Error Interrupt

pub fn boffint(&mut self) -> BOFFINT_W

Bit 2 - Bus Off Interrupt

pub fn rwrnint(&mut self) -> RWRNINT_W

Bit 16 - Rx Warning Interrupt Flag

pub fn twrnint(&mut self) -> TWRNINT_W

Bit 17 - Tx Warning Interrupt Flag

pub fn boffdoneint(&mut self) -> BOFFDONEINT_W

Bit 19 - Bus Off Done Interrupt

pub fn errint_fast(&mut self) -> ERRINT_FAST_W

Bit 20 - Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set

pub fn errovr(&mut self) -> ERROVR_W

Bit 21 - Error Overrun bit

impl W<u32, Reg<u32, _IMASK1>>

pub fn buf31to0m(&mut self) -> BUF31TO0M_W

Bits 0:31 - Buffer MB i Mask

impl W<u32, Reg<u32, _IFLAG1>>

pub fn buf0i(&mut self) -> BUF0I_W

Bit 0 - Buffer MB0 Interrupt Or Clear FIFO bit

pub fn buf4to1i(&mut self) -> BUF4TO1I_W

Bits 1:4 - Buffer MB i Interrupt Or "reserved"

pub fn buf5i(&mut self) -> BUF5I_W

Bit 5 - Buffer MB5 Interrupt Or "Frames available in Rx FIFO"

pub fn buf6i(&mut self) -> BUF6I_W

Bit 6 - Buffer MB6 Interrupt Or "Rx FIFO Warning"

pub fn buf7i(&mut self) -> BUF7I_W

Bit 7 - Buffer MB7 Interrupt Or "Rx FIFO Overflow"

pub fn buf31to8i(&mut self) -> BUF31TO8I_W

Bits 8:31 - Buffer MBi Interrupt

impl W<u32, Reg<u32, _CTRL2>>

pub fn edfltdis(&mut self) -> EDFLTDIS_W

Bit 11 - Edge Filter Disable

pub fn isocanfden(&mut self) -> ISOCANFDEN_W

Bit 12 - ISO CAN FD Enable

pub fn prexcen(&mut self) -> PREXCEN_W

Bit 14 - Protocol Exception Enable

pub fn timer_src(&mut self) -> TIMER_SRC_W

Bit 15 - Timer Source

pub fn eacen(&mut self) -> EACEN_W

Bit 16 - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes

pub fn rrs(&mut self) -> RRS_W

Bit 17 - Remote Request Storing

pub fn mrp(&mut self) -> MRP_W

Bit 18 - Mailboxes Reception Priority

pub fn tasd(&mut self) -> TASD_W

Bits 19:23 - Tx Arbitration Start Delay

pub fn rffn(&mut self) -> RFFN_W

Bits 24:27 - Number Of Rx FIFO Filters

pub fn boffdonemsk(&mut self) -> BOFFDONEMSK_W

Bit 30 - Bus Off Done Interrupt Mask

pub fn errmsk_fast(&mut self) -> ERRMSK_FAST_W

Bit 31 - Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames

impl W<u32, Reg<u32, _RXFGMASK>>

pub fn fgm(&mut self) -> FGM_W

Bits 0:31 - Rx FIFO Global Mask Bits

impl W<u32, Reg<u32, _CBT>>

pub fn epseg2(&mut self) -> EPSEG2_W

Bits 0:4 - Extended Phase Segment 2

pub fn epseg1(&mut self) -> EPSEG1_W

Bits 5:9 - Extended Phase Segment 1

pub fn epropseg(&mut self) -> EPROPSEG_W

Bits 10:15 - Extended Propagation Segment

pub fn erjw(&mut self) -> ERJW_W

Bits 16:20 - Extended Resync Jump Width

pub fn epresdiv(&mut self) -> EPRESDIV_W

Bits 21:30 - Extended Prescaler Division Factor

pub fn btf(&mut self) -> BTF_W

Bit 31 - Bit Timing Format Enable

impl W<u32, Reg<u32, _EMBEDDEDRAM>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _RXIMR>>

pub fn mi(&mut self) -> MI_W

Bits 0:31 - Individual Mask Bits

impl W<u32, Reg<u32, _CTRL1_PN>>

pub fn fcs(&mut self) -> FCS_W

Bits 0:1 - Filtering Combination Selection

pub fn idfs(&mut self) -> IDFS_W

Bits 2:3 - ID Filtering Selection

pub fn plfs(&mut self) -> PLFS_W

Bits 4:5 - Payload Filtering Selection

pub fn nmatch(&mut self) -> NMATCH_W

Bits 8:15 - Number of Messages Matching the Same Filtering Criteria

pub fn wumf_msk(&mut self) -> WUMF_MSK_W

Bit 16 - Wake Up by Match Flag Mask Bit

pub fn wtof_msk(&mut self) -> WTOF_MSK_W

Bit 17 - Wake Up by Timeout Flag Mask Bit

impl W<u32, Reg<u32, _CTRL2_PN>>

pub fn matchto(&mut self) -> MATCHTO_W

Bits 0:15 - Timeout for No Message Matching the Filtering Criteria

impl W<u32, Reg<u32, _WU_MTC>>

pub fn wumf(&mut self) -> WUMF_W

Bit 16 - Wake Up by Match Flag Bit

pub fn wtof(&mut self) -> WTOF_W

Bit 17 - Wake Up by Timeout Flag Bit

impl W<u32, Reg<u32, _FLT_ID1>>

pub fn flt_id1(&mut self) -> FLT_ID1_W

Bits 0:28 - ID Filter 1 for Pretended Networking filtering

pub fn flt_rtr(&mut self) -> FLT_RTR_W

Bit 29 - Remote Transmission Request Filter

pub fn flt_ide(&mut self) -> FLT_IDE_W

Bit 30 - ID Extended Filter

impl W<u32, Reg<u32, _FLT_DLC>>

pub fn flt_dlc_hi(&mut self) -> FLT_DLC_HI_W

Bits 0:3 - Upper Limit for Length of Data Bytes Filter

pub fn flt_dlc_lo(&mut self) -> FLT_DLC_LO_W

Bits 16:19 - Lower Limit for Length of Data Bytes Filter

impl W<u32, Reg<u32, _PL1_LO>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 3.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 2.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 1.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 0.

impl W<u32, Reg<u32, _PL1_HI>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 7.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 6.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 5.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 4.

impl W<u32, Reg<u32, _FLT_ID2_IDMASK>>

pub fn flt_id2_idmask(&mut self) -> FLT_ID2_IDMASK_W

Bits 0:28 - ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering

pub fn rtr_msk(&mut self) -> RTR_MSK_W

Bit 29 - Remote Transmission Request Mask Bit

pub fn ide_msk(&mut self) -> IDE_MSK_W

Bit 30 - ID Extended Mask Bit

impl W<u32, Reg<u32, _PL2_PLMASK_LO>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 3.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 2.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 1.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 0.

impl W<u32, Reg<u32, _PL2_PLMASK_HI>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 7.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 6.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 5.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 4.

impl W<u32, Reg<u32, _FDCTRL>>

pub fn tdcoff(&mut self) -> TDCOFF_W

Bits 8:12 - Transceiver Delay Compensation Offset

pub fn tdcfail(&mut self) -> TDCFAIL_W

Bit 14 - Transceiver Delay Compensation Fail

pub fn tdcen(&mut self) -> TDCEN_W

Bit 15 - Transceiver Delay Compensation Enable

pub fn mbdsr0(&mut self) -> MBDSR0_W

Bits 16:17 - Message Buffer Data Size for Region 0

pub fn fdrate(&mut self) -> FDRATE_W

Bit 31 - Bit Rate Switch Enable

impl W<u32, Reg<u32, _FDCBT>>

pub fn fpseg2(&mut self) -> FPSEG2_W

Bits 0:2 - Fast Phase Segment 2

pub fn fpseg1(&mut self) -> FPSEG1_W

Bits 5:7 - Fast Phase Segment 1

pub fn fpropseg(&mut self) -> FPROPSEG_W

Bits 10:14 - Fast Propagation Segment

pub fn frjw(&mut self) -> FRJW_W

Bits 16:18 - Fast Resync Jump Width

pub fn fpresdiv(&mut self) -> FPRESDIV_W

Bits 20:29 - Fast Prescaler Division Factor

impl W<u32, Reg<u32, _SC>>

pub fn ps(&mut self) -> PS_W

Bits 0:2 - Prescale Factor Selection

pub fn clks(&mut self) -> CLKS_W

Bits 3:4 - Clock Source Selection

pub fn cpwms(&mut self) -> CPWMS_W

Bit 5 - Center-Aligned PWM Select

pub fn rie(&mut self) -> RIE_W

Bit 6 - Reload Point Interrupt Enable

pub fn toie(&mut self) -> TOIE_W

Bit 8 - Timer Overflow Interrupt Enable

pub fn pwmen0(&mut self) -> PWMEN0_W

Bit 16 - Channel 0 PWM enable bit

pub fn pwmen1(&mut self) -> PWMEN1_W

Bit 17 - Channel 1 PWM enable bit

pub fn pwmen2(&mut self) -> PWMEN2_W

Bit 18 - Channel 2 PWM enable bit

pub fn pwmen3(&mut self) -> PWMEN3_W

Bit 19 - Channel 3 PWM enable bit

pub fn pwmen4(&mut self) -> PWMEN4_W

Bit 20 - Channel 4 PWM enable bit

pub fn pwmen5(&mut self) -> PWMEN5_W

Bit 21 - Channel 5 PWM enable bit

pub fn pwmen6(&mut self) -> PWMEN6_W

Bit 22 - Channel 6 PWM enable bit

pub fn pwmen7(&mut self) -> PWMEN7_W

Bit 23 - Channel 7 PWM enable bit

pub fn fltps(&mut self) -> FLTPS_W

Bits 24:27 - Filter Prescaler

impl W<u32, Reg<u32, _CNT>>

pub fn count(&mut self) -> COUNT_W

Bits 0:15 - Counter Value

impl W<u32, Reg<u32, _MOD>>

pub fn mod_(&mut self) -> MOD_W

Bits 0:15 - MOD

impl W<u32, Reg<u32, _C0SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C0V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C1SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C1V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C2SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C2V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C3SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C3V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C4SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C4V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C5SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C5V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C6SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C6V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C7SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C7V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _CNTIN>>

pub fn init(&mut self) -> INIT_W

Bits 0:15 - INIT

impl W<u32, Reg<u32, _MODE>>

pub fn ftmen(&mut self) -> FTMEN_W

Bit 0 - FTM Enable

pub fn init(&mut self) -> INIT_W

Bit 1 - Initialize The Channels Output

pub fn wpdis(&mut self) -> WPDIS_W

Bit 2 - Write Protection Disable

pub fn pwmsync(&mut self) -> PWMSYNC_W

Bit 3 - PWM Synchronization Mode

pub fn captest(&mut self) -> CAPTEST_W

Bit 4 - Capture Test Mode Enable

pub fn faultm(&mut self) -> FAULTM_W

Bits 5:6 - Fault Control Mode

pub fn faultie(&mut self) -> FAULTIE_W

Bit 7 - Fault Interrupt Enable

impl W<u32, Reg<u32, _SYNC>>

pub fn cntmin(&mut self) -> CNTMIN_W

Bit 0 - Minimum Loading Point Enable

pub fn cntmax(&mut self) -> CNTMAX_W

Bit 1 - Maximum Loading Point Enable

pub fn reinit(&mut self) -> REINIT_W

Bit 2 - FTM Counter Reinitialization by Synchronization

pub fn synchom(&mut self) -> SYNCHOM_W

Bit 3 - Output Mask Synchronization

pub fn trig0(&mut self) -> TRIG0_W

Bit 4 - PWM Synchronization Hardware Trigger 0

pub fn trig1(&mut self) -> TRIG1_W

Bit 5 - PWM Synchronization Hardware Trigger 1

pub fn trig2(&mut self) -> TRIG2_W

Bit 6 - PWM Synchronization Hardware Trigger 2

pub fn swsync(&mut self) -> SWSYNC_W

Bit 7 - PWM Synchronization Software Trigger

impl W<u32, Reg<u32, _OUTINIT>>

pub fn ch0oi(&mut self) -> CH0OI_W

Bit 0 - Channel 0 Output Initialization Value

pub fn ch1oi(&mut self) -> CH1OI_W

Bit 1 - Channel 1 Output Initialization Value

pub fn ch2oi(&mut self) -> CH2OI_W

Bit 2 - Channel 2 Output Initialization Value

pub fn ch3oi(&mut self) -> CH3OI_W

Bit 3 - Channel 3 Output Initialization Value

pub fn ch4oi(&mut self) -> CH4OI_W

Bit 4 - Channel 4 Output Initialization Value

pub fn ch5oi(&mut self) -> CH5OI_W

Bit 5 - Channel 5 Output Initialization Value

pub fn ch6oi(&mut self) -> CH6OI_W

Bit 6 - Channel 6 Output Initialization Value

pub fn ch7oi(&mut self) -> CH7OI_W

Bit 7 - Channel 7 Output Initialization Value

impl W<u32, Reg<u32, _OUTMASK>>

pub fn ch0om(&mut self) -> CH0OM_W

Bit 0 - Channel 0 Output Mask

pub fn ch1om(&mut self) -> CH1OM_W

Bit 1 - Channel 1 Output Mask

pub fn ch2om(&mut self) -> CH2OM_W

Bit 2 - Channel 2 Output Mask

pub fn ch3om(&mut self) -> CH3OM_W

Bit 3 - Channel 3 Output Mask

pub fn ch4om(&mut self) -> CH4OM_W

Bit 4 - Channel 4 Output Mask

pub fn ch5om(&mut self) -> CH5OM_W

Bit 5 - Channel 5 Output Mask

pub fn ch6om(&mut self) -> CH6OM_W

Bit 6 - Channel 6 Output Mask

pub fn ch7om(&mut self) -> CH7OM_W

Bit 7 - Channel 7 Output Mask

impl W<u32, Reg<u32, _COMBINE>>

pub fn combine0(&mut self) -> COMBINE0_W

Bit 0 - Combine Channels For n = 0

pub fn comp0(&mut self) -> COMP0_W

Bit 1 - Complement Of Channel (n) For n = 0

pub fn decapen0(&mut self) -> DECAPEN0_W

Bit 2 - Dual Edge Capture Mode Enable For n = 0

pub fn decap0(&mut self) -> DECAP0_W

Bit 3 - Dual Edge Capture Mode Captures For n = 0

pub fn dten0(&mut self) -> DTEN0_W

Bit 4 - Deadtime Enable For n = 0

pub fn syncen0(&mut self) -> SYNCEN0_W

Bit 5 - Synchronization Enable For n = 0

pub fn faulten0(&mut self) -> FAULTEN0_W

Bit 6 - Fault Control Enable For n = 0

pub fn mcombine0(&mut self) -> MCOMBINE0_W

Bit 7 - Modified Combine Mode For n = 0

pub fn combine1(&mut self) -> COMBINE1_W

Bit 8 - Combine Channels For n = 2

pub fn comp1(&mut self) -> COMP1_W

Bit 9 - Complement Of Channel (n) For n = 2

pub fn decapen1(&mut self) -> DECAPEN1_W

Bit 10 - Dual Edge Capture Mode Enable For n = 2

pub fn decap1(&mut self) -> DECAP1_W

Bit 11 - Dual Edge Capture Mode Captures For n = 2

pub fn dten1(&mut self) -> DTEN1_W

Bit 12 - Deadtime Enable For n = 2

pub fn syncen1(&mut self) -> SYNCEN1_W

Bit 13 - Synchronization Enable For n = 2

pub fn faulten1(&mut self) -> FAULTEN1_W

Bit 14 - Fault Control Enable For n = 2

pub fn mcombine1(&mut self) -> MCOMBINE1_W

Bit 15 - Modified Combine Mode For n = 2

pub fn combine2(&mut self) -> COMBINE2_W

Bit 16 - Combine Channels For n = 4

pub fn comp2(&mut self) -> COMP2_W

Bit 17 - Complement Of Channel (n) For n = 4

pub fn decapen2(&mut self) -> DECAPEN2_W

Bit 18 - Dual Edge Capture Mode Enable For n = 4

pub fn decap2(&mut self) -> DECAP2_W

Bit 19 - Dual Edge Capture Mode Captures For n = 4

pub fn dten2(&mut self) -> DTEN2_W

Bit 20 - Deadtime Enable For n = 4

pub fn syncen2(&mut self) -> SYNCEN2_W

Bit 21 - Synchronization Enable For n = 4

pub fn faulten2(&mut self) -> FAULTEN2_W

Bit 22 - Fault Control Enable For n = 4

pub fn mcombine2(&mut self) -> MCOMBINE2_W

Bit 23 - Modified Combine Mode For n = 4

pub fn combine3(&mut self) -> COMBINE3_W

Bit 24 - Combine Channels For n = 6

pub fn comp3(&mut self) -> COMP3_W

Bit 25 - Complement Of Channel (n) for n = 6

pub fn decapen3(&mut self) -> DECAPEN3_W

Bit 26 - Dual Edge Capture Mode Enable For n = 6

pub fn decap3(&mut self) -> DECAP3_W

Bit 27 - Dual Edge Capture Mode Captures For n = 6

pub fn dten3(&mut self) -> DTEN3_W

Bit 28 - Deadtime Enable For n = 6

pub fn syncen3(&mut self) -> SYNCEN3_W

Bit 29 - Synchronization Enable For n = 6

pub fn faulten3(&mut self) -> FAULTEN3_W

Bit 30 - Fault Control Enable For n = 6

pub fn mcombine3(&mut self) -> MCOMBINE3_W

Bit 31 - Modified Combine Mode For n = 6

impl W<u32, Reg<u32, _DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _EXTTRIG>>

pub fn ch2trig(&mut self) -> CH2TRIG_W

Bit 0 - Channel 2 External Trigger Enable

pub fn ch3trig(&mut self) -> CH3TRIG_W

Bit 1 - Channel 3 External Trigger Enable

pub fn ch4trig(&mut self) -> CH4TRIG_W

Bit 2 - Channel 4 External Trigger Enable

pub fn ch5trig(&mut self) -> CH5TRIG_W

Bit 3 - Channel 5 External Trigger Enable

pub fn ch0trig(&mut self) -> CH0TRIG_W

Bit 4 - Channel 0 External Trigger Enable

pub fn ch1trig(&mut self) -> CH1TRIG_W

Bit 5 - Channel 1 External Trigger Enable

pub fn inittrigen(&mut self) -> INITTRIGEN_W

Bit 6 - Initialization Trigger Enable

pub fn ch6trig(&mut self) -> CH6TRIG_W

Bit 8 - Channel 6 External Trigger Enable

pub fn ch7trig(&mut self) -> CH7TRIG_W

Bit 9 - Channel 7 External Trigger Enable

impl W<u32, Reg<u32, _POL>>

pub fn pol0(&mut self) -> POL0_W

Bit 0 - Channel 0 Polarity

pub fn pol1(&mut self) -> POL1_W

Bit 1 - Channel 1 Polarity

pub fn pol2(&mut self) -> POL2_W

Bit 2 - Channel 2 Polarity

pub fn pol3(&mut self) -> POL3_W

Bit 3 - Channel 3 Polarity

pub fn pol4(&mut self) -> POL4_W

Bit 4 - Channel 4 Polarity

pub fn pol5(&mut self) -> POL5_W

Bit 5 - Channel 5 Polarity

pub fn pol6(&mut self) -> POL6_W

Bit 6 - Channel 6 Polarity

pub fn pol7(&mut self) -> POL7_W

Bit 7 - Channel 7 Polarity

impl W<u32, Reg<u32, _FMS>>

pub fn wpen(&mut self) -> WPEN_W

Bit 6 - Write Protection Enable

impl W<u32, Reg<u32, _FILTER>>

pub fn ch0fval(&mut self) -> CH0FVAL_W

Bits 0:3 - Channel 0 Input Filter

pub fn ch1fval(&mut self) -> CH1FVAL_W

Bits 4:7 - Channel 1 Input Filter

pub fn ch2fval(&mut self) -> CH2FVAL_W

Bits 8:11 - Channel 2 Input Filter

pub fn ch3fval(&mut self) -> CH3FVAL_W

Bits 12:15 - Channel 3 Input Filter

impl W<u32, Reg<u32, _FLTCTRL>>

pub fn fault0en(&mut self) -> FAULT0EN_W

Bit 0 - Fault Input 0 Enable

pub fn fault1en(&mut self) -> FAULT1EN_W

Bit 1 - Fault Input 1 Enable

pub fn fault2en(&mut self) -> FAULT2EN_W

Bit 2 - Fault Input 2 Enable

pub fn fault3en(&mut self) -> FAULT3EN_W

Bit 3 - Fault Input 3 Enable

pub fn ffltr0en(&mut self) -> FFLTR0EN_W

Bit 4 - Fault Input 0 Filter Enable

pub fn ffltr1en(&mut self) -> FFLTR1EN_W

Bit 5 - Fault Input 1 Filter Enable

pub fn ffltr2en(&mut self) -> FFLTR2EN_W

Bit 6 - Fault Input 2 Filter Enable

pub fn ffltr3en(&mut self) -> FFLTR3EN_W

Bit 7 - Fault Input 3 Filter Enable

pub fn ffval(&mut self) -> FFVAL_W

Bits 8:11 - Fault Input Filter

pub fn fstate(&mut self) -> FSTATE_W

Bit 15 - Fault output state

impl W<u32, Reg<u32, _QDCTRL>>

pub fn quaden(&mut self) -> QUADEN_W

Bit 0 - Quadrature Decoder Mode Enable

pub fn quadmode(&mut self) -> QUADMODE_W

Bit 3 - Quadrature Decoder Mode

pub fn phbpol(&mut self) -> PHBPOL_W

Bit 4 - Phase B Input Polarity

pub fn phapol(&mut self) -> PHAPOL_W

Bit 5 - Phase A Input Polarity

pub fn phbfltren(&mut self) -> PHBFLTREN_W

Bit 6 - Phase B Input Filter Enable

pub fn phafltren(&mut self) -> PHAFLTREN_W

Bit 7 - Phase A Input Filter Enable

impl W<u32, Reg<u32, _CONF>>

pub fn ldfq(&mut self) -> LDFQ_W

Bits 0:4 - Frequency of the Reload Opportunities

pub fn bdmmode(&mut self) -> BDMMODE_W

Bits 6:7 - Debug Mode

pub fn gtbeen(&mut self) -> GTBEEN_W

Bit 9 - Global Time Base Enable

pub fn gtbeout(&mut self) -> GTBEOUT_W

Bit 10 - Global Time Base Output

pub fn itrigr(&mut self) -> ITRIGR_W

Bit 11 - Initialization trigger on Reload Point

impl W<u32, Reg<u32, _FLTPOL>>

pub fn flt0pol(&mut self) -> FLT0POL_W

Bit 0 - Fault Input 0 Polarity

pub fn flt1pol(&mut self) -> FLT1POL_W

Bit 1 - Fault Input 1 Polarity

pub fn flt2pol(&mut self) -> FLT2POL_W

Bit 2 - Fault Input 2 Polarity

pub fn flt3pol(&mut self) -> FLT3POL_W

Bit 3 - Fault Input 3 Polarity

impl W<u32, Reg<u32, _SYNCONF>>

pub fn hwtrigmode(&mut self) -> HWTRIGMODE_W

Bit 0 - Hardware Trigger Mode

pub fn cntinc(&mut self) -> CNTINC_W

Bit 2 - CNTIN Register Synchronization

pub fn invc(&mut self) -> INVC_W

Bit 4 - INVCTRL Register Synchronization

pub fn swoc(&mut self) -> SWOC_W

Bit 5 - SWOCTRL Register Synchronization

pub fn syncmode(&mut self) -> SYNCMODE_W

Bit 7 - Synchronization Mode

pub fn swrstcnt(&mut self) -> SWRSTCNT_W

Bit 8 - FTM counter synchronization is activated by the software trigger

pub fn swwrbuf(&mut self) -> SWWRBUF_W

Bit 9 - MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger

pub fn swom(&mut self) -> SWOM_W

Bit 10 - Output mask synchronization is activated by the software trigger

pub fn swinvc(&mut self) -> SWINVC_W

Bit 11 - Inverting control synchronization is activated by the software trigger

pub fn swsoc(&mut self) -> SWSOC_W

Bit 12 - Software output control synchronization is activated by the software trigger

pub fn hwrstcnt(&mut self) -> HWRSTCNT_W

Bit 16 - FTM counter synchronization is activated by a hardware trigger

pub fn hwwrbuf(&mut self) -> HWWRBUF_W

Bit 17 - MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger

pub fn hwom(&mut self) -> HWOM_W

Bit 18 - Output mask synchronization is activated by a hardware trigger

pub fn hwinvc(&mut self) -> HWINVC_W

Bit 19 - Inverting control synchronization is activated by a hardware trigger

pub fn hwsoc(&mut self) -> HWSOC_W

Bit 20 - Software output control synchronization is activated by a hardware trigger

impl W<u32, Reg<u32, _INVCTRL>>

pub fn inv0en(&mut self) -> INV0EN_W

Bit 0 - Pair Channels 0 Inverting Enable

pub fn inv1en(&mut self) -> INV1EN_W

Bit 1 - Pair Channels 1 Inverting Enable

pub fn inv2en(&mut self) -> INV2EN_W

Bit 2 - Pair Channels 2 Inverting Enable

pub fn inv3en(&mut self) -> INV3EN_W

Bit 3 - Pair Channels 3 Inverting Enable

impl W<u32, Reg<u32, _SWOCTRL>>

pub fn ch0oc(&mut self) -> CH0OC_W

Bit 0 - Channel 0 Software Output Control Enable

pub fn ch1oc(&mut self) -> CH1OC_W

Bit 1 - Channel 1 Software Output Control Enable

pub fn ch2oc(&mut self) -> CH2OC_W

Bit 2 - Channel 2 Software Output Control Enable

pub fn ch3oc(&mut self) -> CH3OC_W

Bit 3 - Channel 3 Software Output Control Enable

pub fn ch4oc(&mut self) -> CH4OC_W

Bit 4 - Channel 4 Software Output Control Enable

pub fn ch5oc(&mut self) -> CH5OC_W

Bit 5 - Channel 5 Software Output Control Enable

pub fn ch6oc(&mut self) -> CH6OC_W

Bit 6 - Channel 6 Software Output Control Enable

pub fn ch7oc(&mut self) -> CH7OC_W

Bit 7 - Channel 7 Software Output Control Enable

pub fn ch0ocv(&mut self) -> CH0OCV_W

Bit 8 - Channel 0 Software Output Control Value

pub fn ch1ocv(&mut self) -> CH1OCV_W

Bit 9 - Channel 1 Software Output Control Value

pub fn ch2ocv(&mut self) -> CH2OCV_W

Bit 10 - Channel 2 Software Output Control Value

pub fn ch3ocv(&mut self) -> CH3OCV_W

Bit 11 - Channel 3 Software Output Control Value

pub fn ch4ocv(&mut self) -> CH4OCV_W

Bit 12 - Channel 4 Software Output Control Value

pub fn ch5ocv(&mut self) -> CH5OCV_W

Bit 13 - Channel 5 Software Output Control Value

pub fn ch6ocv(&mut self) -> CH6OCV_W

Bit 14 - Channel 6 Software Output Control Value

pub fn ch7ocv(&mut self) -> CH7OCV_W

Bit 15 - Channel 7 Software Output Control Value

impl W<u32, Reg<u32, _PWMLOAD>>

pub fn ch0sel(&mut self) -> CH0SEL_W

Bit 0 - Channel 0 Select

pub fn ch1sel(&mut self) -> CH1SEL_W

Bit 1 - Channel 1 Select

pub fn ch2sel(&mut self) -> CH2SEL_W

Bit 2 - Channel 2 Select

pub fn ch3sel(&mut self) -> CH3SEL_W

Bit 3 - Channel 3 Select

pub fn ch4sel(&mut self) -> CH4SEL_W

Bit 4 - Channel 4 Select

pub fn ch5sel(&mut self) -> CH5SEL_W

Bit 5 - Channel 5 Select

pub fn ch6sel(&mut self) -> CH6SEL_W

Bit 6 - Channel 6 Select

pub fn ch7sel(&mut self) -> CH7SEL_W

Bit 7 - Channel 7 Select

pub fn hcsel(&mut self) -> HCSEL_W

Bit 8 - Half Cycle Select

pub fn ldok(&mut self) -> LDOK_W

Bit 9 - Load Enable

pub fn glen(&mut self) -> GLEN_W

Bit 10 - Global Load Enable

pub fn gldok(&mut self) -> GLDOK_W

Bit 11 - Global Load OK

impl W<u32, Reg<u32, _HCR>>

pub fn hcval(&mut self) -> HCVAL_W

Bits 0:15 - Half Cycle Value

impl W<u32, Reg<u32, _PAIR0DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _PAIR1DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _PAIR2DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _PAIR3DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _SC>>

pub fn ps(&mut self) -> PS_W

Bits 0:2 - Prescale Factor Selection

pub fn clks(&mut self) -> CLKS_W

Bits 3:4 - Clock Source Selection

pub fn cpwms(&mut self) -> CPWMS_W

Bit 5 - Center-Aligned PWM Select

pub fn rie(&mut self) -> RIE_W

Bit 6 - Reload Point Interrupt Enable

pub fn toie(&mut self) -> TOIE_W

Bit 8 - Timer Overflow Interrupt Enable

pub fn pwmen0(&mut self) -> PWMEN0_W

Bit 16 - Channel 0 PWM enable bit

pub fn pwmen1(&mut self) -> PWMEN1_W

Bit 17 - Channel 1 PWM enable bit

pub fn pwmen2(&mut self) -> PWMEN2_W

Bit 18 - Channel 2 PWM enable bit

pub fn pwmen3(&mut self) -> PWMEN3_W

Bit 19 - Channel 3 PWM enable bit

pub fn pwmen4(&mut self) -> PWMEN4_W

Bit 20 - Channel 4 PWM enable bit

pub fn pwmen5(&mut self) -> PWMEN5_W

Bit 21 - Channel 5 PWM enable bit

pub fn pwmen6(&mut self) -> PWMEN6_W

Bit 22 - Channel 6 PWM enable bit

pub fn pwmen7(&mut self) -> PWMEN7_W

Bit 23 - Channel 7 PWM enable bit

pub fn fltps(&mut self) -> FLTPS_W

Bits 24:27 - Filter Prescaler

impl W<u32, Reg<u32, _CNT>>

pub fn count(&mut self) -> COUNT_W

Bits 0:15 - Counter Value

impl W<u32, Reg<u32, _MOD>>

pub fn mod_(&mut self) -> MOD_W

Bits 0:15 - MOD

impl W<u32, Reg<u32, _C0SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C0V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C1SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C1V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C2SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C2V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C3SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C3V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C4SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C4V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C5SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C5V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C6SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C6V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C7SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C7V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _CNTIN>>

pub fn init(&mut self) -> INIT_W

Bits 0:15 - INIT

impl W<u32, Reg<u32, _MODE>>

pub fn ftmen(&mut self) -> FTMEN_W

Bit 0 - FTM Enable

pub fn init(&mut self) -> INIT_W

Bit 1 - Initialize The Channels Output

pub fn wpdis(&mut self) -> WPDIS_W

Bit 2 - Write Protection Disable

pub fn pwmsync(&mut self) -> PWMSYNC_W

Bit 3 - PWM Synchronization Mode

pub fn captest(&mut self) -> CAPTEST_W

Bit 4 - Capture Test Mode Enable

pub fn faultm(&mut self) -> FAULTM_W

Bits 5:6 - Fault Control Mode

pub fn faultie(&mut self) -> FAULTIE_W

Bit 7 - Fault Interrupt Enable

impl W<u32, Reg<u32, _SYNC>>

pub fn cntmin(&mut self) -> CNTMIN_W

Bit 0 - Minimum Loading Point Enable

pub fn cntmax(&mut self) -> CNTMAX_W

Bit 1 - Maximum Loading Point Enable

pub fn reinit(&mut self) -> REINIT_W

Bit 2 - FTM Counter Reinitialization by Synchronization

pub fn synchom(&mut self) -> SYNCHOM_W

Bit 3 - Output Mask Synchronization

pub fn trig0(&mut self) -> TRIG0_W

Bit 4 - PWM Synchronization Hardware Trigger 0

pub fn trig1(&mut self) -> TRIG1_W

Bit 5 - PWM Synchronization Hardware Trigger 1

pub fn trig2(&mut self) -> TRIG2_W

Bit 6 - PWM Synchronization Hardware Trigger 2

pub fn swsync(&mut self) -> SWSYNC_W

Bit 7 - PWM Synchronization Software Trigger

impl W<u32, Reg<u32, _OUTINIT>>

pub fn ch0oi(&mut self) -> CH0OI_W

Bit 0 - Channel 0 Output Initialization Value

pub fn ch1oi(&mut self) -> CH1OI_W

Bit 1 - Channel 1 Output Initialization Value

pub fn ch2oi(&mut self) -> CH2OI_W

Bit 2 - Channel 2 Output Initialization Value

pub fn ch3oi(&mut self) -> CH3OI_W

Bit 3 - Channel 3 Output Initialization Value

pub fn ch4oi(&mut self) -> CH4OI_W

Bit 4 - Channel 4 Output Initialization Value

pub fn ch5oi(&mut self) -> CH5OI_W

Bit 5 - Channel 5 Output Initialization Value

pub fn ch6oi(&mut self) -> CH6OI_W

Bit 6 - Channel 6 Output Initialization Value

pub fn ch7oi(&mut self) -> CH7OI_W

Bit 7 - Channel 7 Output Initialization Value

impl W<u32, Reg<u32, _OUTMASK>>

pub fn ch0om(&mut self) -> CH0OM_W

Bit 0 - Channel 0 Output Mask

pub fn ch1om(&mut self) -> CH1OM_W

Bit 1 - Channel 1 Output Mask

pub fn ch2om(&mut self) -> CH2OM_W

Bit 2 - Channel 2 Output Mask

pub fn ch3om(&mut self) -> CH3OM_W

Bit 3 - Channel 3 Output Mask

pub fn ch4om(&mut self) -> CH4OM_W

Bit 4 - Channel 4 Output Mask

pub fn ch5om(&mut self) -> CH5OM_W

Bit 5 - Channel 5 Output Mask

pub fn ch6om(&mut self) -> CH6OM_W

Bit 6 - Channel 6 Output Mask

pub fn ch7om(&mut self) -> CH7OM_W

Bit 7 - Channel 7 Output Mask

impl W<u32, Reg<u32, _COMBINE>>

pub fn combine0(&mut self) -> COMBINE0_W

Bit 0 - Combine Channels For n = 0

pub fn comp0(&mut self) -> COMP0_W

Bit 1 - Complement Of Channel (n) For n = 0

pub fn decapen0(&mut self) -> DECAPEN0_W

Bit 2 - Dual Edge Capture Mode Enable For n = 0

pub fn decap0(&mut self) -> DECAP0_W

Bit 3 - Dual Edge Capture Mode Captures For n = 0

pub fn dten0(&mut self) -> DTEN0_W

Bit 4 - Deadtime Enable For n = 0

pub fn syncen0(&mut self) -> SYNCEN0_W

Bit 5 - Synchronization Enable For n = 0

pub fn faulten0(&mut self) -> FAULTEN0_W

Bit 6 - Fault Control Enable For n = 0

pub fn mcombine0(&mut self) -> MCOMBINE0_W

Bit 7 - Modified Combine Mode For n = 0

pub fn combine1(&mut self) -> COMBINE1_W

Bit 8 - Combine Channels For n = 2

pub fn comp1(&mut self) -> COMP1_W

Bit 9 - Complement Of Channel (n) For n = 2

pub fn decapen1(&mut self) -> DECAPEN1_W

Bit 10 - Dual Edge Capture Mode Enable For n = 2

pub fn decap1(&mut self) -> DECAP1_W

Bit 11 - Dual Edge Capture Mode Captures For n = 2

pub fn dten1(&mut self) -> DTEN1_W

Bit 12 - Deadtime Enable For n = 2

pub fn syncen1(&mut self) -> SYNCEN1_W

Bit 13 - Synchronization Enable For n = 2

pub fn faulten1(&mut self) -> FAULTEN1_W

Bit 14 - Fault Control Enable For n = 2

pub fn mcombine1(&mut self) -> MCOMBINE1_W

Bit 15 - Modified Combine Mode For n = 2

pub fn combine2(&mut self) -> COMBINE2_W

Bit 16 - Combine Channels For n = 4

pub fn comp2(&mut self) -> COMP2_W

Bit 17 - Complement Of Channel (n) For n = 4

pub fn decapen2(&mut self) -> DECAPEN2_W

Bit 18 - Dual Edge Capture Mode Enable For n = 4

pub fn decap2(&mut self) -> DECAP2_W

Bit 19 - Dual Edge Capture Mode Captures For n = 4

pub fn dten2(&mut self) -> DTEN2_W

Bit 20 - Deadtime Enable For n = 4

pub fn syncen2(&mut self) -> SYNCEN2_W

Bit 21 - Synchronization Enable For n = 4

pub fn faulten2(&mut self) -> FAULTEN2_W

Bit 22 - Fault Control Enable For n = 4

pub fn mcombine2(&mut self) -> MCOMBINE2_W

Bit 23 - Modified Combine Mode For n = 4

pub fn combine3(&mut self) -> COMBINE3_W

Bit 24 - Combine Channels For n = 6

pub fn comp3(&mut self) -> COMP3_W

Bit 25 - Complement Of Channel (n) for n = 6

pub fn decapen3(&mut self) -> DECAPEN3_W

Bit 26 - Dual Edge Capture Mode Enable For n = 6

pub fn decap3(&mut self) -> DECAP3_W

Bit 27 - Dual Edge Capture Mode Captures For n = 6

pub fn dten3(&mut self) -> DTEN3_W

Bit 28 - Deadtime Enable For n = 6

pub fn syncen3(&mut self) -> SYNCEN3_W

Bit 29 - Synchronization Enable For n = 6

pub fn faulten3(&mut self) -> FAULTEN3_W

Bit 30 - Fault Control Enable For n = 6

pub fn mcombine3(&mut self) -> MCOMBINE3_W

Bit 31 - Modified Combine Mode For n = 6

impl W<u32, Reg<u32, _DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _EXTTRIG>>

pub fn ch2trig(&mut self) -> CH2TRIG_W

Bit 0 - Channel 2 External Trigger Enable

pub fn ch3trig(&mut self) -> CH3TRIG_W

Bit 1 - Channel 3 External Trigger Enable

pub fn ch4trig(&mut self) -> CH4TRIG_W

Bit 2 - Channel 4 External Trigger Enable

pub fn ch5trig(&mut self) -> CH5TRIG_W

Bit 3 - Channel 5 External Trigger Enable

pub fn ch0trig(&mut self) -> CH0TRIG_W

Bit 4 - Channel 0 External Trigger Enable

pub fn ch1trig(&mut self) -> CH1TRIG_W

Bit 5 - Channel 1 External Trigger Enable

pub fn inittrigen(&mut self) -> INITTRIGEN_W

Bit 6 - Initialization Trigger Enable

pub fn ch6trig(&mut self) -> CH6TRIG_W

Bit 8 - Channel 6 External Trigger Enable

pub fn ch7trig(&mut self) -> CH7TRIG_W

Bit 9 - Channel 7 External Trigger Enable

impl W<u32, Reg<u32, _POL>>

pub fn pol0(&mut self) -> POL0_W

Bit 0 - Channel 0 Polarity

pub fn pol1(&mut self) -> POL1_W

Bit 1 - Channel 1 Polarity

pub fn pol2(&mut self) -> POL2_W

Bit 2 - Channel 2 Polarity

pub fn pol3(&mut self) -> POL3_W

Bit 3 - Channel 3 Polarity

pub fn pol4(&mut self) -> POL4_W

Bit 4 - Channel 4 Polarity

pub fn pol5(&mut self) -> POL5_W

Bit 5 - Channel 5 Polarity

pub fn pol6(&mut self) -> POL6_W

Bit 6 - Channel 6 Polarity

pub fn pol7(&mut self) -> POL7_W

Bit 7 - Channel 7 Polarity

impl W<u32, Reg<u32, _FMS>>

pub fn wpen(&mut self) -> WPEN_W

Bit 6 - Write Protection Enable

impl W<u32, Reg<u32, _FILTER>>

pub fn ch0fval(&mut self) -> CH0FVAL_W

Bits 0:3 - Channel 0 Input Filter

pub fn ch1fval(&mut self) -> CH1FVAL_W

Bits 4:7 - Channel 1 Input Filter

pub fn ch2fval(&mut self) -> CH2FVAL_W

Bits 8:11 - Channel 2 Input Filter

pub fn ch3fval(&mut self) -> CH3FVAL_W

Bits 12:15 - Channel 3 Input Filter

impl W<u32, Reg<u32, _FLTCTRL>>

pub fn fault0en(&mut self) -> FAULT0EN_W

Bit 0 - Fault Input 0 Enable

pub fn fault1en(&mut self) -> FAULT1EN_W

Bit 1 - Fault Input 1 Enable

pub fn fault2en(&mut self) -> FAULT2EN_W

Bit 2 - Fault Input 2 Enable

pub fn fault3en(&mut self) -> FAULT3EN_W

Bit 3 - Fault Input 3 Enable

pub fn ffltr0en(&mut self) -> FFLTR0EN_W

Bit 4 - Fault Input 0 Filter Enable

pub fn ffltr1en(&mut self) -> FFLTR1EN_W

Bit 5 - Fault Input 1 Filter Enable

pub fn ffltr2en(&mut self) -> FFLTR2EN_W

Bit 6 - Fault Input 2 Filter Enable

pub fn ffltr3en(&mut self) -> FFLTR3EN_W

Bit 7 - Fault Input 3 Filter Enable

pub fn ffval(&mut self) -> FFVAL_W

Bits 8:11 - Fault Input Filter

pub fn fstate(&mut self) -> FSTATE_W

Bit 15 - Fault output state

impl W<u32, Reg<u32, _QDCTRL>>

pub fn quaden(&mut self) -> QUADEN_W

Bit 0 - Quadrature Decoder Mode Enable

pub fn quadmode(&mut self) -> QUADMODE_W

Bit 3 - Quadrature Decoder Mode

pub fn phbpol(&mut self) -> PHBPOL_W

Bit 4 - Phase B Input Polarity

pub fn phapol(&mut self) -> PHAPOL_W

Bit 5 - Phase A Input Polarity

pub fn phbfltren(&mut self) -> PHBFLTREN_W

Bit 6 - Phase B Input Filter Enable

pub fn phafltren(&mut self) -> PHAFLTREN_W

Bit 7 - Phase A Input Filter Enable

impl W<u32, Reg<u32, _CONF>>

pub fn ldfq(&mut self) -> LDFQ_W

Bits 0:4 - Frequency of the Reload Opportunities

pub fn bdmmode(&mut self) -> BDMMODE_W

Bits 6:7 - Debug Mode

pub fn gtbeen(&mut self) -> GTBEEN_W

Bit 9 - Global Time Base Enable

pub fn gtbeout(&mut self) -> GTBEOUT_W

Bit 10 - Global Time Base Output

pub fn itrigr(&mut self) -> ITRIGR_W

Bit 11 - Initialization trigger on Reload Point

impl W<u32, Reg<u32, _FLTPOL>>

pub fn flt0pol(&mut self) -> FLT0POL_W

Bit 0 - Fault Input 0 Polarity

pub fn flt1pol(&mut self) -> FLT1POL_W

Bit 1 - Fault Input 1 Polarity

pub fn flt2pol(&mut self) -> FLT2POL_W

Bit 2 - Fault Input 2 Polarity

pub fn flt3pol(&mut self) -> FLT3POL_W

Bit 3 - Fault Input 3 Polarity

impl W<u32, Reg<u32, _SYNCONF>>

pub fn hwtrigmode(&mut self) -> HWTRIGMODE_W

Bit 0 - Hardware Trigger Mode

pub fn cntinc(&mut self) -> CNTINC_W

Bit 2 - CNTIN Register Synchronization

pub fn invc(&mut self) -> INVC_W

Bit 4 - INVCTRL Register Synchronization

pub fn swoc(&mut self) -> SWOC_W

Bit 5 - SWOCTRL Register Synchronization

pub fn syncmode(&mut self) -> SYNCMODE_W

Bit 7 - Synchronization Mode

pub fn swrstcnt(&mut self) -> SWRSTCNT_W

Bit 8 - FTM counter synchronization is activated by the software trigger

pub fn swwrbuf(&mut self) -> SWWRBUF_W

Bit 9 - MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger

pub fn swom(&mut self) -> SWOM_W

Bit 10 - Output mask synchronization is activated by the software trigger

pub fn swinvc(&mut self) -> SWINVC_W

Bit 11 - Inverting control synchronization is activated by the software trigger

pub fn swsoc(&mut self) -> SWSOC_W

Bit 12 - Software output control synchronization is activated by the software trigger

pub fn hwrstcnt(&mut self) -> HWRSTCNT_W

Bit 16 - FTM counter synchronization is activated by a hardware trigger

pub fn hwwrbuf(&mut self) -> HWWRBUF_W

Bit 17 - MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger

pub fn hwom(&mut self) -> HWOM_W

Bit 18 - Output mask synchronization is activated by a hardware trigger

pub fn hwinvc(&mut self) -> HWINVC_W

Bit 19 - Inverting control synchronization is activated by a hardware trigger

pub fn hwsoc(&mut self) -> HWSOC_W

Bit 20 - Software output control synchronization is activated by a hardware trigger

impl W<u32, Reg<u32, _INVCTRL>>

pub fn inv0en(&mut self) -> INV0EN_W

Bit 0 - Pair Channels 0 Inverting Enable

pub fn inv1en(&mut self) -> INV1EN_W

Bit 1 - Pair Channels 1 Inverting Enable

pub fn inv2en(&mut self) -> INV2EN_W

Bit 2 - Pair Channels 2 Inverting Enable

pub fn inv3en(&mut self) -> INV3EN_W

Bit 3 - Pair Channels 3 Inverting Enable

impl W<u32, Reg<u32, _SWOCTRL>>

pub fn ch0oc(&mut self) -> CH0OC_W

Bit 0 - Channel 0 Software Output Control Enable

pub fn ch1oc(&mut self) -> CH1OC_W

Bit 1 - Channel 1 Software Output Control Enable

pub fn ch2oc(&mut self) -> CH2OC_W

Bit 2 - Channel 2 Software Output Control Enable

pub fn ch3oc(&mut self) -> CH3OC_W

Bit 3 - Channel 3 Software Output Control Enable

pub fn ch4oc(&mut self) -> CH4OC_W

Bit 4 - Channel 4 Software Output Control Enable

pub fn ch5oc(&mut self) -> CH5OC_W

Bit 5 - Channel 5 Software Output Control Enable

pub fn ch6oc(&mut self) -> CH6OC_W

Bit 6 - Channel 6 Software Output Control Enable

pub fn ch7oc(&mut self) -> CH7OC_W

Bit 7 - Channel 7 Software Output Control Enable

pub fn ch0ocv(&mut self) -> CH0OCV_W

Bit 8 - Channel 0 Software Output Control Value

pub fn ch1ocv(&mut self) -> CH1OCV_W

Bit 9 - Channel 1 Software Output Control Value

pub fn ch2ocv(&mut self) -> CH2OCV_W

Bit 10 - Channel 2 Software Output Control Value

pub fn ch3ocv(&mut self) -> CH3OCV_W

Bit 11 - Channel 3 Software Output Control Value

pub fn ch4ocv(&mut self) -> CH4OCV_W

Bit 12 - Channel 4 Software Output Control Value

pub fn ch5ocv(&mut self) -> CH5OCV_W

Bit 13 - Channel 5 Software Output Control Value

pub fn ch6ocv(&mut self) -> CH6OCV_W

Bit 14 - Channel 6 Software Output Control Value

pub fn ch7ocv(&mut self) -> CH7OCV_W

Bit 15 - Channel 7 Software Output Control Value

impl W<u32, Reg<u32, _PWMLOAD>>

pub fn ch0sel(&mut self) -> CH0SEL_W

Bit 0 - Channel 0 Select

pub fn ch1sel(&mut self) -> CH1SEL_W

Bit 1 - Channel 1 Select

pub fn ch2sel(&mut self) -> CH2SEL_W

Bit 2 - Channel 2 Select

pub fn ch3sel(&mut self) -> CH3SEL_W

Bit 3 - Channel 3 Select

pub fn ch4sel(&mut self) -> CH4SEL_W

Bit 4 - Channel 4 Select

pub fn ch5sel(&mut self) -> CH5SEL_W

Bit 5 - Channel 5 Select

pub fn ch6sel(&mut self) -> CH6SEL_W

Bit 6 - Channel 6 Select

pub fn ch7sel(&mut self) -> CH7SEL_W

Bit 7 - Channel 7 Select

pub fn hcsel(&mut self) -> HCSEL_W

Bit 8 - Half Cycle Select

pub fn ldok(&mut self) -> LDOK_W

Bit 9 - Load Enable

pub fn glen(&mut self) -> GLEN_W

Bit 10 - Global Load Enable

pub fn gldok(&mut self) -> GLDOK_W

Bit 11 - Global Load OK

impl W<u32, Reg<u32, _HCR>>

pub fn hcval(&mut self) -> HCVAL_W

Bits 0:15 - Half Cycle Value

impl W<u32, Reg<u32, _PAIR0DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _PAIR1DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _PAIR2DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _PAIR3DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _SC>>

pub fn ps(&mut self) -> PS_W

Bits 0:2 - Prescale Factor Selection

pub fn clks(&mut self) -> CLKS_W

Bits 3:4 - Clock Source Selection

pub fn cpwms(&mut self) -> CPWMS_W

Bit 5 - Center-Aligned PWM Select

pub fn rie(&mut self) -> RIE_W

Bit 6 - Reload Point Interrupt Enable

pub fn toie(&mut self) -> TOIE_W

Bit 8 - Timer Overflow Interrupt Enable

pub fn pwmen0(&mut self) -> PWMEN0_W

Bit 16 - Channel 0 PWM enable bit

pub fn pwmen1(&mut self) -> PWMEN1_W

Bit 17 - Channel 1 PWM enable bit

pub fn pwmen2(&mut self) -> PWMEN2_W

Bit 18 - Channel 2 PWM enable bit

pub fn pwmen3(&mut self) -> PWMEN3_W

Bit 19 - Channel 3 PWM enable bit

pub fn pwmen4(&mut self) -> PWMEN4_W

Bit 20 - Channel 4 PWM enable bit

pub fn pwmen5(&mut self) -> PWMEN5_W

Bit 21 - Channel 5 PWM enable bit

pub fn pwmen6(&mut self) -> PWMEN6_W

Bit 22 - Channel 6 PWM enable bit

pub fn pwmen7(&mut self) -> PWMEN7_W

Bit 23 - Channel 7 PWM enable bit

pub fn fltps(&mut self) -> FLTPS_W

Bits 24:27 - Filter Prescaler

impl W<u32, Reg<u32, _CNT>>

pub fn count(&mut self) -> COUNT_W

Bits 0:15 - Counter Value

impl W<u32, Reg<u32, _MOD>>

pub fn mod_(&mut self) -> MOD_W

Bits 0:15 - MOD

impl W<u32, Reg<u32, _C0SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C0V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C1SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C1V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C2SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C2V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C3SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C3V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C4SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C4V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C5SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C5V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C6SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C6V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C7SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C7V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _CNTIN>>

pub fn init(&mut self) -> INIT_W

Bits 0:15 - INIT

impl W<u32, Reg<u32, _MODE>>

pub fn ftmen(&mut self) -> FTMEN_W

Bit 0 - FTM Enable

pub fn init(&mut self) -> INIT_W

Bit 1 - Initialize The Channels Output

pub fn wpdis(&mut self) -> WPDIS_W

Bit 2 - Write Protection Disable

pub fn pwmsync(&mut self) -> PWMSYNC_W

Bit 3 - PWM Synchronization Mode

pub fn captest(&mut self) -> CAPTEST_W

Bit 4 - Capture Test Mode Enable

pub fn faultm(&mut self) -> FAULTM_W

Bits 5:6 - Fault Control Mode

pub fn faultie(&mut self) -> FAULTIE_W

Bit 7 - Fault Interrupt Enable

impl W<u32, Reg<u32, _SYNC>>

pub fn cntmin(&mut self) -> CNTMIN_W

Bit 0 - Minimum Loading Point Enable

pub fn cntmax(&mut self) -> CNTMAX_W

Bit 1 - Maximum Loading Point Enable

pub fn reinit(&mut self) -> REINIT_W

Bit 2 - FTM Counter Reinitialization by Synchronization

pub fn synchom(&mut self) -> SYNCHOM_W

Bit 3 - Output Mask Synchronization

pub fn trig0(&mut self) -> TRIG0_W

Bit 4 - PWM Synchronization Hardware Trigger 0

pub fn trig1(&mut self) -> TRIG1_W

Bit 5 - PWM Synchronization Hardware Trigger 1

pub fn trig2(&mut self) -> TRIG2_W

Bit 6 - PWM Synchronization Hardware Trigger 2

pub fn swsync(&mut self) -> SWSYNC_W

Bit 7 - PWM Synchronization Software Trigger

impl W<u32, Reg<u32, _OUTINIT>>

pub fn ch0oi(&mut self) -> CH0OI_W

Bit 0 - Channel 0 Output Initialization Value

pub fn ch1oi(&mut self) -> CH1OI_W

Bit 1 - Channel 1 Output Initialization Value

pub fn ch2oi(&mut self) -> CH2OI_W

Bit 2 - Channel 2 Output Initialization Value

pub fn ch3oi(&mut self) -> CH3OI_W

Bit 3 - Channel 3 Output Initialization Value

pub fn ch4oi(&mut self) -> CH4OI_W

Bit 4 - Channel 4 Output Initialization Value

pub fn ch5oi(&mut self) -> CH5OI_W

Bit 5 - Channel 5 Output Initialization Value

pub fn ch6oi(&mut self) -> CH6OI_W

Bit 6 - Channel 6 Output Initialization Value

pub fn ch7oi(&mut self) -> CH7OI_W

Bit 7 - Channel 7 Output Initialization Value

impl W<u32, Reg<u32, _OUTMASK>>

pub fn ch0om(&mut self) -> CH0OM_W

Bit 0 - Channel 0 Output Mask

pub fn ch1om(&mut self) -> CH1OM_W

Bit 1 - Channel 1 Output Mask

pub fn ch2om(&mut self) -> CH2OM_W

Bit 2 - Channel 2 Output Mask

pub fn ch3om(&mut self) -> CH3OM_W

Bit 3 - Channel 3 Output Mask

pub fn ch4om(&mut self) -> CH4OM_W

Bit 4 - Channel 4 Output Mask

pub fn ch5om(&mut self) -> CH5OM_W

Bit 5 - Channel 5 Output Mask

pub fn ch6om(&mut self) -> CH6OM_W

Bit 6 - Channel 6 Output Mask

pub fn ch7om(&mut self) -> CH7OM_W

Bit 7 - Channel 7 Output Mask

impl W<u32, Reg<u32, _COMBINE>>

pub fn combine0(&mut self) -> COMBINE0_W

Bit 0 - Combine Channels For n = 0

pub fn comp0(&mut self) -> COMP0_W

Bit 1 - Complement Of Channel (n) For n = 0

pub fn decapen0(&mut self) -> DECAPEN0_W

Bit 2 - Dual Edge Capture Mode Enable For n = 0

pub fn decap0(&mut self) -> DECAP0_W

Bit 3 - Dual Edge Capture Mode Captures For n = 0

pub fn dten0(&mut self) -> DTEN0_W

Bit 4 - Deadtime Enable For n = 0

pub fn syncen0(&mut self) -> SYNCEN0_W

Bit 5 - Synchronization Enable For n = 0

pub fn faulten0(&mut self) -> FAULTEN0_W

Bit 6 - Fault Control Enable For n = 0

pub fn mcombine0(&mut self) -> MCOMBINE0_W

Bit 7 - Modified Combine Mode For n = 0

pub fn combine1(&mut self) -> COMBINE1_W

Bit 8 - Combine Channels For n = 2

pub fn comp1(&mut self) -> COMP1_W

Bit 9 - Complement Of Channel (n) For n = 2

pub fn decapen1(&mut self) -> DECAPEN1_W

Bit 10 - Dual Edge Capture Mode Enable For n = 2

pub fn decap1(&mut self) -> DECAP1_W

Bit 11 - Dual Edge Capture Mode Captures For n = 2

pub fn dten1(&mut self) -> DTEN1_W

Bit 12 - Deadtime Enable For n = 2

pub fn syncen1(&mut self) -> SYNCEN1_W

Bit 13 - Synchronization Enable For n = 2

pub fn faulten1(&mut self) -> FAULTEN1_W

Bit 14 - Fault Control Enable For n = 2

pub fn mcombine1(&mut self) -> MCOMBINE1_W

Bit 15 - Modified Combine Mode For n = 2

pub fn combine2(&mut self) -> COMBINE2_W

Bit 16 - Combine Channels For n = 4

pub fn comp2(&mut self) -> COMP2_W

Bit 17 - Complement Of Channel (n) For n = 4

pub fn decapen2(&mut self) -> DECAPEN2_W

Bit 18 - Dual Edge Capture Mode Enable For n = 4

pub fn decap2(&mut self) -> DECAP2_W

Bit 19 - Dual Edge Capture Mode Captures For n = 4

pub fn dten2(&mut self) -> DTEN2_W

Bit 20 - Deadtime Enable For n = 4

pub fn syncen2(&mut self) -> SYNCEN2_W

Bit 21 - Synchronization Enable For n = 4

pub fn faulten2(&mut self) -> FAULTEN2_W

Bit 22 - Fault Control Enable For n = 4

pub fn mcombine2(&mut self) -> MCOMBINE2_W

Bit 23 - Modified Combine Mode For n = 4

pub fn combine3(&mut self) -> COMBINE3_W

Bit 24 - Combine Channels For n = 6

pub fn comp3(&mut self) -> COMP3_W

Bit 25 - Complement Of Channel (n) for n = 6

pub fn decapen3(&mut self) -> DECAPEN3_W

Bit 26 - Dual Edge Capture Mode Enable For n = 6

pub fn decap3(&mut self) -> DECAP3_W

Bit 27 - Dual Edge Capture Mode Captures For n = 6

pub fn dten3(&mut self) -> DTEN3_W

Bit 28 - Deadtime Enable For n = 6

pub fn syncen3(&mut self) -> SYNCEN3_W

Bit 29 - Synchronization Enable For n = 6

pub fn faulten3(&mut self) -> FAULTEN3_W

Bit 30 - Fault Control Enable For n = 6

pub fn mcombine3(&mut self) -> MCOMBINE3_W

Bit 31 - Modified Combine Mode For n = 6

impl W<u32, Reg<u32, _DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _EXTTRIG>>

pub fn ch2trig(&mut self) -> CH2TRIG_W

Bit 0 - Channel 2 External Trigger Enable

pub fn ch3trig(&mut self) -> CH3TRIG_W

Bit 1 - Channel 3 External Trigger Enable

pub fn ch4trig(&mut self) -> CH4TRIG_W

Bit 2 - Channel 4 External Trigger Enable

pub fn ch5trig(&mut self) -> CH5TRIG_W

Bit 3 - Channel 5 External Trigger Enable

pub fn ch0trig(&mut self) -> CH0TRIG_W

Bit 4 - Channel 0 External Trigger Enable

pub fn ch1trig(&mut self) -> CH1TRIG_W

Bit 5 - Channel 1 External Trigger Enable

pub fn inittrigen(&mut self) -> INITTRIGEN_W

Bit 6 - Initialization Trigger Enable

pub fn ch6trig(&mut self) -> CH6TRIG_W

Bit 8 - Channel 6 External Trigger Enable

pub fn ch7trig(&mut self) -> CH7TRIG_W

Bit 9 - Channel 7 External Trigger Enable

impl W<u32, Reg<u32, _POL>>

pub fn pol0(&mut self) -> POL0_W

Bit 0 - Channel 0 Polarity

pub fn pol1(&mut self) -> POL1_W

Bit 1 - Channel 1 Polarity

pub fn pol2(&mut self) -> POL2_W

Bit 2 - Channel 2 Polarity

pub fn pol3(&mut self) -> POL3_W

Bit 3 - Channel 3 Polarity

pub fn pol4(&mut self) -> POL4_W

Bit 4 - Channel 4 Polarity

pub fn pol5(&mut self) -> POL5_W

Bit 5 - Channel 5 Polarity

pub fn pol6(&mut self) -> POL6_W

Bit 6 - Channel 6 Polarity

pub fn pol7(&mut self) -> POL7_W

Bit 7 - Channel 7 Polarity

impl W<u32, Reg<u32, _FMS>>

pub fn wpen(&mut self) -> WPEN_W

Bit 6 - Write Protection Enable

impl W<u32, Reg<u32, _FILTER>>

pub fn ch0fval(&mut self) -> CH0FVAL_W

Bits 0:3 - Channel 0 Input Filter

pub fn ch1fval(&mut self) -> CH1FVAL_W

Bits 4:7 - Channel 1 Input Filter

pub fn ch2fval(&mut self) -> CH2FVAL_W

Bits 8:11 - Channel 2 Input Filter

pub fn ch3fval(&mut self) -> CH3FVAL_W

Bits 12:15 - Channel 3 Input Filter

impl W<u32, Reg<u32, _FLTCTRL>>

pub fn fault0en(&mut self) -> FAULT0EN_W

Bit 0 - Fault Input 0 Enable

pub fn fault1en(&mut self) -> FAULT1EN_W

Bit 1 - Fault Input 1 Enable

pub fn fault2en(&mut self) -> FAULT2EN_W

Bit 2 - Fault Input 2 Enable

pub fn fault3en(&mut self) -> FAULT3EN_W

Bit 3 - Fault Input 3 Enable

pub fn ffltr0en(&mut self) -> FFLTR0EN_W

Bit 4 - Fault Input 0 Filter Enable

pub fn ffltr1en(&mut self) -> FFLTR1EN_W

Bit 5 - Fault Input 1 Filter Enable

pub fn ffltr2en(&mut self) -> FFLTR2EN_W

Bit 6 - Fault Input 2 Filter Enable

pub fn ffltr3en(&mut self) -> FFLTR3EN_W

Bit 7 - Fault Input 3 Filter Enable

pub fn ffval(&mut self) -> FFVAL_W

Bits 8:11 - Fault Input Filter

pub fn fstate(&mut self) -> FSTATE_W

Bit 15 - Fault output state

impl W<u32, Reg<u32, _QDCTRL>>

pub fn quaden(&mut self) -> QUADEN_W

Bit 0 - Quadrature Decoder Mode Enable

pub fn quadmode(&mut self) -> QUADMODE_W

Bit 3 - Quadrature Decoder Mode

pub fn phbpol(&mut self) -> PHBPOL_W

Bit 4 - Phase B Input Polarity

pub fn phapol(&mut self) -> PHAPOL_W

Bit 5 - Phase A Input Polarity

pub fn phbfltren(&mut self) -> PHBFLTREN_W

Bit 6 - Phase B Input Filter Enable

pub fn phafltren(&mut self) -> PHAFLTREN_W

Bit 7 - Phase A Input Filter Enable

impl W<u32, Reg<u32, _CONF>>

pub fn ldfq(&mut self) -> LDFQ_W

Bits 0:4 - Frequency of the Reload Opportunities

pub fn bdmmode(&mut self) -> BDMMODE_W

Bits 6:7 - Debug Mode

pub fn gtbeen(&mut self) -> GTBEEN_W

Bit 9 - Global Time Base Enable

pub fn gtbeout(&mut self) -> GTBEOUT_W

Bit 10 - Global Time Base Output

pub fn itrigr(&mut self) -> ITRIGR_W

Bit 11 - Initialization trigger on Reload Point

impl W<u32, Reg<u32, _FLTPOL>>

pub fn flt0pol(&mut self) -> FLT0POL_W

Bit 0 - Fault Input 0 Polarity

pub fn flt1pol(&mut self) -> FLT1POL_W

Bit 1 - Fault Input 1 Polarity

pub fn flt2pol(&mut self) -> FLT2POL_W

Bit 2 - Fault Input 2 Polarity

pub fn flt3pol(&mut self) -> FLT3POL_W

Bit 3 - Fault Input 3 Polarity

impl W<u32, Reg<u32, _SYNCONF>>

pub fn hwtrigmode(&mut self) -> HWTRIGMODE_W

Bit 0 - Hardware Trigger Mode

pub fn cntinc(&mut self) -> CNTINC_W

Bit 2 - CNTIN Register Synchronization

pub fn invc(&mut self) -> INVC_W

Bit 4 - INVCTRL Register Synchronization

pub fn swoc(&mut self) -> SWOC_W

Bit 5 - SWOCTRL Register Synchronization

pub fn syncmode(&mut self) -> SYNCMODE_W

Bit 7 - Synchronization Mode

pub fn swrstcnt(&mut self) -> SWRSTCNT_W

Bit 8 - FTM counter synchronization is activated by the software trigger

pub fn swwrbuf(&mut self) -> SWWRBUF_W

Bit 9 - MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger

pub fn swom(&mut self) -> SWOM_W

Bit 10 - Output mask synchronization is activated by the software trigger

pub fn swinvc(&mut self) -> SWINVC_W

Bit 11 - Inverting control synchronization is activated by the software trigger

pub fn swsoc(&mut self) -> SWSOC_W

Bit 12 - Software output control synchronization is activated by the software trigger

pub fn hwrstcnt(&mut self) -> HWRSTCNT_W

Bit 16 - FTM counter synchronization is activated by a hardware trigger

pub fn hwwrbuf(&mut self) -> HWWRBUF_W

Bit 17 - MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger

pub fn hwom(&mut self) -> HWOM_W

Bit 18 - Output mask synchronization is activated by a hardware trigger

pub fn hwinvc(&mut self) -> HWINVC_W

Bit 19 - Inverting control synchronization is activated by a hardware trigger

pub fn hwsoc(&mut self) -> HWSOC_W

Bit 20 - Software output control synchronization is activated by a hardware trigger

impl W<u32, Reg<u32, _INVCTRL>>

pub fn inv0en(&mut self) -> INV0EN_W

Bit 0 - Pair Channels 0 Inverting Enable

pub fn inv1en(&mut self) -> INV1EN_W

Bit 1 - Pair Channels 1 Inverting Enable

pub fn inv2en(&mut self) -> INV2EN_W

Bit 2 - Pair Channels 2 Inverting Enable

pub fn inv3en(&mut self) -> INV3EN_W

Bit 3 - Pair Channels 3 Inverting Enable

impl W<u32, Reg<u32, _SWOCTRL>>

pub fn ch0oc(&mut self) -> CH0OC_W

Bit 0 - Channel 0 Software Output Control Enable

pub fn ch1oc(&mut self) -> CH1OC_W

Bit 1 - Channel 1 Software Output Control Enable

pub fn ch2oc(&mut self) -> CH2OC_W

Bit 2 - Channel 2 Software Output Control Enable

pub fn ch3oc(&mut self) -> CH3OC_W

Bit 3 - Channel 3 Software Output Control Enable

pub fn ch4oc(&mut self) -> CH4OC_W

Bit 4 - Channel 4 Software Output Control Enable

pub fn ch5oc(&mut self) -> CH5OC_W

Bit 5 - Channel 5 Software Output Control Enable

pub fn ch6oc(&mut self) -> CH6OC_W

Bit 6 - Channel 6 Software Output Control Enable

pub fn ch7oc(&mut self) -> CH7OC_W

Bit 7 - Channel 7 Software Output Control Enable

pub fn ch0ocv(&mut self) -> CH0OCV_W

Bit 8 - Channel 0 Software Output Control Value

pub fn ch1ocv(&mut self) -> CH1OCV_W

Bit 9 - Channel 1 Software Output Control Value

pub fn ch2ocv(&mut self) -> CH2OCV_W

Bit 10 - Channel 2 Software Output Control Value

pub fn ch3ocv(&mut self) -> CH3OCV_W

Bit 11 - Channel 3 Software Output Control Value

pub fn ch4ocv(&mut self) -> CH4OCV_W

Bit 12 - Channel 4 Software Output Control Value

pub fn ch5ocv(&mut self) -> CH5OCV_W

Bit 13 - Channel 5 Software Output Control Value

pub fn ch6ocv(&mut self) -> CH6OCV_W

Bit 14 - Channel 6 Software Output Control Value

pub fn ch7ocv(&mut self) -> CH7OCV_W

Bit 15 - Channel 7 Software Output Control Value

impl W<u32, Reg<u32, _PWMLOAD>>

pub fn ch0sel(&mut self) -> CH0SEL_W

Bit 0 - Channel 0 Select

pub fn ch1sel(&mut self) -> CH1SEL_W

Bit 1 - Channel 1 Select

pub fn ch2sel(&mut self) -> CH2SEL_W

Bit 2 - Channel 2 Select

pub fn ch3sel(&mut self) -> CH3SEL_W

Bit 3 - Channel 3 Select

pub fn ch4sel(&mut self) -> CH4SEL_W

Bit 4 - Channel 4 Select

pub fn ch5sel(&mut self) -> CH5SEL_W

Bit 5 - Channel 5 Select

pub fn ch6sel(&mut self) -> CH6SEL_W

Bit 6 - Channel 6 Select

pub fn ch7sel(&mut self) -> CH7SEL_W

Bit 7 - Channel 7 Select

pub fn hcsel(&mut self) -> HCSEL_W

Bit 8 - Half Cycle Select

pub fn ldok(&mut self) -> LDOK_W

Bit 9 - Load Enable

pub fn glen(&mut self) -> GLEN_W

Bit 10 - Global Load Enable

pub fn gldok(&mut self) -> GLDOK_W

Bit 11 - Global Load OK

impl W<u32, Reg<u32, _HCR>>

pub fn hcval(&mut self) -> HCVAL_W

Bits 0:15 - Half Cycle Value

impl W<u32, Reg<u32, _PAIR0DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _PAIR1DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _PAIR2DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _PAIR3DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _SC>>

pub fn ps(&mut self) -> PS_W

Bits 0:2 - Prescale Factor Selection

pub fn clks(&mut self) -> CLKS_W

Bits 3:4 - Clock Source Selection

pub fn cpwms(&mut self) -> CPWMS_W

Bit 5 - Center-Aligned PWM Select

pub fn rie(&mut self) -> RIE_W

Bit 6 - Reload Point Interrupt Enable

pub fn toie(&mut self) -> TOIE_W

Bit 8 - Timer Overflow Interrupt Enable

pub fn pwmen0(&mut self) -> PWMEN0_W

Bit 16 - Channel 0 PWM enable bit

pub fn pwmen1(&mut self) -> PWMEN1_W

Bit 17 - Channel 1 PWM enable bit

pub fn pwmen2(&mut self) -> PWMEN2_W

Bit 18 - Channel 2 PWM enable bit

pub fn pwmen3(&mut self) -> PWMEN3_W

Bit 19 - Channel 3 PWM enable bit

pub fn pwmen4(&mut self) -> PWMEN4_W

Bit 20 - Channel 4 PWM enable bit

pub fn pwmen5(&mut self) -> PWMEN5_W

Bit 21 - Channel 5 PWM enable bit

pub fn pwmen6(&mut self) -> PWMEN6_W

Bit 22 - Channel 6 PWM enable bit

pub fn pwmen7(&mut self) -> PWMEN7_W

Bit 23 - Channel 7 PWM enable bit

pub fn fltps(&mut self) -> FLTPS_W

Bits 24:27 - Filter Prescaler

impl W<u32, Reg<u32, _CNT>>

pub fn count(&mut self) -> COUNT_W

Bits 0:15 - Counter Value

impl W<u32, Reg<u32, _MOD>>

pub fn mod_(&mut self) -> MOD_W

Bits 0:15 - MOD

impl W<u32, Reg<u32, _C0SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C0V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C1SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C1V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C2SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C2V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C3SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C3V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C4SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C4V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C5SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C5V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C6SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C6V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _C7SC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn icrst(&mut self) -> ICRST_W

Bit 1 - FTM counter reset by the selected input capture event.

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Channel (n) Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Channel (n) Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel (n) Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel (n) Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel (n) Interrupt Enable

pub fn trigmode(&mut self) -> TRIGMODE_W

Bit 8 - Trigger mode control

impl W<u32, Reg<u32, _C7V>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _CNTIN>>

pub fn init(&mut self) -> INIT_W

Bits 0:15 - INIT

impl W<u32, Reg<u32, _MODE>>

pub fn ftmen(&mut self) -> FTMEN_W

Bit 0 - FTM Enable

pub fn init(&mut self) -> INIT_W

Bit 1 - Initialize The Channels Output

pub fn wpdis(&mut self) -> WPDIS_W

Bit 2 - Write Protection Disable

pub fn pwmsync(&mut self) -> PWMSYNC_W

Bit 3 - PWM Synchronization Mode

pub fn captest(&mut self) -> CAPTEST_W

Bit 4 - Capture Test Mode Enable

pub fn faultm(&mut self) -> FAULTM_W

Bits 5:6 - Fault Control Mode

pub fn faultie(&mut self) -> FAULTIE_W

Bit 7 - Fault Interrupt Enable

impl W<u32, Reg<u32, _SYNC>>

pub fn cntmin(&mut self) -> CNTMIN_W

Bit 0 - Minimum Loading Point Enable

pub fn cntmax(&mut self) -> CNTMAX_W

Bit 1 - Maximum Loading Point Enable

pub fn reinit(&mut self) -> REINIT_W

Bit 2 - FTM Counter Reinitialization by Synchronization

pub fn synchom(&mut self) -> SYNCHOM_W

Bit 3 - Output Mask Synchronization

pub fn trig0(&mut self) -> TRIG0_W

Bit 4 - PWM Synchronization Hardware Trigger 0

pub fn trig1(&mut self) -> TRIG1_W

Bit 5 - PWM Synchronization Hardware Trigger 1

pub fn trig2(&mut self) -> TRIG2_W

Bit 6 - PWM Synchronization Hardware Trigger 2

pub fn swsync(&mut self) -> SWSYNC_W

Bit 7 - PWM Synchronization Software Trigger

impl W<u32, Reg<u32, _OUTINIT>>

pub fn ch0oi(&mut self) -> CH0OI_W

Bit 0 - Channel 0 Output Initialization Value

pub fn ch1oi(&mut self) -> CH1OI_W

Bit 1 - Channel 1 Output Initialization Value

pub fn ch2oi(&mut self) -> CH2OI_W

Bit 2 - Channel 2 Output Initialization Value

pub fn ch3oi(&mut self) -> CH3OI_W

Bit 3 - Channel 3 Output Initialization Value

pub fn ch4oi(&mut self) -> CH4OI_W

Bit 4 - Channel 4 Output Initialization Value

pub fn ch5oi(&mut self) -> CH5OI_W

Bit 5 - Channel 5 Output Initialization Value

pub fn ch6oi(&mut self) -> CH6OI_W

Bit 6 - Channel 6 Output Initialization Value

pub fn ch7oi(&mut self) -> CH7OI_W

Bit 7 - Channel 7 Output Initialization Value

impl W<u32, Reg<u32, _OUTMASK>>

pub fn ch0om(&mut self) -> CH0OM_W

Bit 0 - Channel 0 Output Mask

pub fn ch1om(&mut self) -> CH1OM_W

Bit 1 - Channel 1 Output Mask

pub fn ch2om(&mut self) -> CH2OM_W

Bit 2 - Channel 2 Output Mask

pub fn ch3om(&mut self) -> CH3OM_W

Bit 3 - Channel 3 Output Mask

pub fn ch4om(&mut self) -> CH4OM_W

Bit 4 - Channel 4 Output Mask

pub fn ch5om(&mut self) -> CH5OM_W

Bit 5 - Channel 5 Output Mask

pub fn ch6om(&mut self) -> CH6OM_W

Bit 6 - Channel 6 Output Mask

pub fn ch7om(&mut self) -> CH7OM_W

Bit 7 - Channel 7 Output Mask

impl W<u32, Reg<u32, _COMBINE>>

pub fn combine0(&mut self) -> COMBINE0_W

Bit 0 - Combine Channels For n = 0

pub fn comp0(&mut self) -> COMP0_W

Bit 1 - Complement Of Channel (n) For n = 0

pub fn decapen0(&mut self) -> DECAPEN0_W

Bit 2 - Dual Edge Capture Mode Enable For n = 0

pub fn decap0(&mut self) -> DECAP0_W

Bit 3 - Dual Edge Capture Mode Captures For n = 0

pub fn dten0(&mut self) -> DTEN0_W

Bit 4 - Deadtime Enable For n = 0

pub fn syncen0(&mut self) -> SYNCEN0_W

Bit 5 - Synchronization Enable For n = 0

pub fn faulten0(&mut self) -> FAULTEN0_W

Bit 6 - Fault Control Enable For n = 0

pub fn mcombine0(&mut self) -> MCOMBINE0_W

Bit 7 - Modified Combine Mode For n = 0

pub fn combine1(&mut self) -> COMBINE1_W

Bit 8 - Combine Channels For n = 2

pub fn comp1(&mut self) -> COMP1_W

Bit 9 - Complement Of Channel (n) For n = 2

pub fn decapen1(&mut self) -> DECAPEN1_W

Bit 10 - Dual Edge Capture Mode Enable For n = 2

pub fn decap1(&mut self) -> DECAP1_W

Bit 11 - Dual Edge Capture Mode Captures For n = 2

pub fn dten1(&mut self) -> DTEN1_W

Bit 12 - Deadtime Enable For n = 2

pub fn syncen1(&mut self) -> SYNCEN1_W

Bit 13 - Synchronization Enable For n = 2

pub fn faulten1(&mut self) -> FAULTEN1_W

Bit 14 - Fault Control Enable For n = 2

pub fn mcombine1(&mut self) -> MCOMBINE1_W

Bit 15 - Modified Combine Mode For n = 2

pub fn combine2(&mut self) -> COMBINE2_W

Bit 16 - Combine Channels For n = 4

pub fn comp2(&mut self) -> COMP2_W

Bit 17 - Complement Of Channel (n) For n = 4

pub fn decapen2(&mut self) -> DECAPEN2_W

Bit 18 - Dual Edge Capture Mode Enable For n = 4

pub fn decap2(&mut self) -> DECAP2_W

Bit 19 - Dual Edge Capture Mode Captures For n = 4

pub fn dten2(&mut self) -> DTEN2_W

Bit 20 - Deadtime Enable For n = 4

pub fn syncen2(&mut self) -> SYNCEN2_W

Bit 21 - Synchronization Enable For n = 4

pub fn faulten2(&mut self) -> FAULTEN2_W

Bit 22 - Fault Control Enable For n = 4

pub fn mcombine2(&mut self) -> MCOMBINE2_W

Bit 23 - Modified Combine Mode For n = 4

pub fn combine3(&mut self) -> COMBINE3_W

Bit 24 - Combine Channels For n = 6

pub fn comp3(&mut self) -> COMP3_W

Bit 25 - Complement Of Channel (n) for n = 6

pub fn decapen3(&mut self) -> DECAPEN3_W

Bit 26 - Dual Edge Capture Mode Enable For n = 6

pub fn decap3(&mut self) -> DECAP3_W

Bit 27 - Dual Edge Capture Mode Captures For n = 6

pub fn dten3(&mut self) -> DTEN3_W

Bit 28 - Deadtime Enable For n = 6

pub fn syncen3(&mut self) -> SYNCEN3_W

Bit 29 - Synchronization Enable For n = 6

pub fn faulten3(&mut self) -> FAULTEN3_W

Bit 30 - Fault Control Enable For n = 6

pub fn mcombine3(&mut self) -> MCOMBINE3_W

Bit 31 - Modified Combine Mode For n = 6

impl W<u32, Reg<u32, _DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _EXTTRIG>>

pub fn ch2trig(&mut self) -> CH2TRIG_W

Bit 0 - Channel 2 External Trigger Enable

pub fn ch3trig(&mut self) -> CH3TRIG_W

Bit 1 - Channel 3 External Trigger Enable

pub fn ch4trig(&mut self) -> CH4TRIG_W

Bit 2 - Channel 4 External Trigger Enable

pub fn ch5trig(&mut self) -> CH5TRIG_W

Bit 3 - Channel 5 External Trigger Enable

pub fn ch0trig(&mut self) -> CH0TRIG_W

Bit 4 - Channel 0 External Trigger Enable

pub fn ch1trig(&mut self) -> CH1TRIG_W

Bit 5 - Channel 1 External Trigger Enable

pub fn inittrigen(&mut self) -> INITTRIGEN_W

Bit 6 - Initialization Trigger Enable

pub fn ch6trig(&mut self) -> CH6TRIG_W

Bit 8 - Channel 6 External Trigger Enable

pub fn ch7trig(&mut self) -> CH7TRIG_W

Bit 9 - Channel 7 External Trigger Enable

impl W<u32, Reg<u32, _POL>>

pub fn pol0(&mut self) -> POL0_W

Bit 0 - Channel 0 Polarity

pub fn pol1(&mut self) -> POL1_W

Bit 1 - Channel 1 Polarity

pub fn pol2(&mut self) -> POL2_W

Bit 2 - Channel 2 Polarity

pub fn pol3(&mut self) -> POL3_W

Bit 3 - Channel 3 Polarity

pub fn pol4(&mut self) -> POL4_W

Bit 4 - Channel 4 Polarity

pub fn pol5(&mut self) -> POL5_W

Bit 5 - Channel 5 Polarity

pub fn pol6(&mut self) -> POL6_W

Bit 6 - Channel 6 Polarity

pub fn pol7(&mut self) -> POL7_W

Bit 7 - Channel 7 Polarity

impl W<u32, Reg<u32, _FMS>>

pub fn wpen(&mut self) -> WPEN_W

Bit 6 - Write Protection Enable

impl W<u32, Reg<u32, _FILTER>>

pub fn ch0fval(&mut self) -> CH0FVAL_W

Bits 0:3 - Channel 0 Input Filter

pub fn ch1fval(&mut self) -> CH1FVAL_W

Bits 4:7 - Channel 1 Input Filter

pub fn ch2fval(&mut self) -> CH2FVAL_W

Bits 8:11 - Channel 2 Input Filter

pub fn ch3fval(&mut self) -> CH3FVAL_W

Bits 12:15 - Channel 3 Input Filter

impl W<u32, Reg<u32, _FLTCTRL>>

pub fn fault0en(&mut self) -> FAULT0EN_W

Bit 0 - Fault Input 0 Enable

pub fn fault1en(&mut self) -> FAULT1EN_W

Bit 1 - Fault Input 1 Enable

pub fn fault2en(&mut self) -> FAULT2EN_W

Bit 2 - Fault Input 2 Enable

pub fn fault3en(&mut self) -> FAULT3EN_W

Bit 3 - Fault Input 3 Enable

pub fn ffltr0en(&mut self) -> FFLTR0EN_W

Bit 4 - Fault Input 0 Filter Enable

pub fn ffltr1en(&mut self) -> FFLTR1EN_W

Bit 5 - Fault Input 1 Filter Enable

pub fn ffltr2en(&mut self) -> FFLTR2EN_W

Bit 6 - Fault Input 2 Filter Enable

pub fn ffltr3en(&mut self) -> FFLTR3EN_W

Bit 7 - Fault Input 3 Filter Enable

pub fn ffval(&mut self) -> FFVAL_W

Bits 8:11 - Fault Input Filter

pub fn fstate(&mut self) -> FSTATE_W

Bit 15 - Fault output state

impl W<u32, Reg<u32, _QDCTRL>>

pub fn quaden(&mut self) -> QUADEN_W

Bit 0 - Quadrature Decoder Mode Enable

pub fn quadmode(&mut self) -> QUADMODE_W

Bit 3 - Quadrature Decoder Mode

pub fn phbpol(&mut self) -> PHBPOL_W

Bit 4 - Phase B Input Polarity

pub fn phapol(&mut self) -> PHAPOL_W

Bit 5 - Phase A Input Polarity

pub fn phbfltren(&mut self) -> PHBFLTREN_W

Bit 6 - Phase B Input Filter Enable

pub fn phafltren(&mut self) -> PHAFLTREN_W

Bit 7 - Phase A Input Filter Enable

impl W<u32, Reg<u32, _CONF>>

pub fn ldfq(&mut self) -> LDFQ_W

Bits 0:4 - Frequency of the Reload Opportunities

pub fn bdmmode(&mut self) -> BDMMODE_W

Bits 6:7 - Debug Mode

pub fn gtbeen(&mut self) -> GTBEEN_W

Bit 9 - Global Time Base Enable

pub fn gtbeout(&mut self) -> GTBEOUT_W

Bit 10 - Global Time Base Output

pub fn itrigr(&mut self) -> ITRIGR_W

Bit 11 - Initialization trigger on Reload Point

impl W<u32, Reg<u32, _FLTPOL>>

pub fn flt0pol(&mut self) -> FLT0POL_W

Bit 0 - Fault Input 0 Polarity

pub fn flt1pol(&mut self) -> FLT1POL_W

Bit 1 - Fault Input 1 Polarity

pub fn flt2pol(&mut self) -> FLT2POL_W

Bit 2 - Fault Input 2 Polarity

pub fn flt3pol(&mut self) -> FLT3POL_W

Bit 3 - Fault Input 3 Polarity

impl W<u32, Reg<u32, _SYNCONF>>

pub fn hwtrigmode(&mut self) -> HWTRIGMODE_W

Bit 0 - Hardware Trigger Mode

pub fn cntinc(&mut self) -> CNTINC_W

Bit 2 - CNTIN Register Synchronization

pub fn invc(&mut self) -> INVC_W

Bit 4 - INVCTRL Register Synchronization

pub fn swoc(&mut self) -> SWOC_W

Bit 5 - SWOCTRL Register Synchronization

pub fn syncmode(&mut self) -> SYNCMODE_W

Bit 7 - Synchronization Mode

pub fn swrstcnt(&mut self) -> SWRSTCNT_W

Bit 8 - FTM counter synchronization is activated by the software trigger

pub fn swwrbuf(&mut self) -> SWWRBUF_W

Bit 9 - MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger

pub fn swom(&mut self) -> SWOM_W

Bit 10 - Output mask synchronization is activated by the software trigger

pub fn swinvc(&mut self) -> SWINVC_W

Bit 11 - Inverting control synchronization is activated by the software trigger

pub fn swsoc(&mut self) -> SWSOC_W

Bit 12 - Software output control synchronization is activated by the software trigger

pub fn hwrstcnt(&mut self) -> HWRSTCNT_W

Bit 16 - FTM counter synchronization is activated by a hardware trigger

pub fn hwwrbuf(&mut self) -> HWWRBUF_W

Bit 17 - MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger

pub fn hwom(&mut self) -> HWOM_W

Bit 18 - Output mask synchronization is activated by a hardware trigger

pub fn hwinvc(&mut self) -> HWINVC_W

Bit 19 - Inverting control synchronization is activated by a hardware trigger

pub fn hwsoc(&mut self) -> HWSOC_W

Bit 20 - Software output control synchronization is activated by a hardware trigger

impl W<u32, Reg<u32, _INVCTRL>>

pub fn inv0en(&mut self) -> INV0EN_W

Bit 0 - Pair Channels 0 Inverting Enable

pub fn inv1en(&mut self) -> INV1EN_W

Bit 1 - Pair Channels 1 Inverting Enable

pub fn inv2en(&mut self) -> INV2EN_W

Bit 2 - Pair Channels 2 Inverting Enable

pub fn inv3en(&mut self) -> INV3EN_W

Bit 3 - Pair Channels 3 Inverting Enable

impl W<u32, Reg<u32, _SWOCTRL>>

pub fn ch0oc(&mut self) -> CH0OC_W

Bit 0 - Channel 0 Software Output Control Enable

pub fn ch1oc(&mut self) -> CH1OC_W

Bit 1 - Channel 1 Software Output Control Enable

pub fn ch2oc(&mut self) -> CH2OC_W

Bit 2 - Channel 2 Software Output Control Enable

pub fn ch3oc(&mut self) -> CH3OC_W

Bit 3 - Channel 3 Software Output Control Enable

pub fn ch4oc(&mut self) -> CH4OC_W

Bit 4 - Channel 4 Software Output Control Enable

pub fn ch5oc(&mut self) -> CH5OC_W

Bit 5 - Channel 5 Software Output Control Enable

pub fn ch6oc(&mut self) -> CH6OC_W

Bit 6 - Channel 6 Software Output Control Enable

pub fn ch7oc(&mut self) -> CH7OC_W

Bit 7 - Channel 7 Software Output Control Enable

pub fn ch0ocv(&mut self) -> CH0OCV_W

Bit 8 - Channel 0 Software Output Control Value

pub fn ch1ocv(&mut self) -> CH1OCV_W

Bit 9 - Channel 1 Software Output Control Value

pub fn ch2ocv(&mut self) -> CH2OCV_W

Bit 10 - Channel 2 Software Output Control Value

pub fn ch3ocv(&mut self) -> CH3OCV_W

Bit 11 - Channel 3 Software Output Control Value

pub fn ch4ocv(&mut self) -> CH4OCV_W

Bit 12 - Channel 4 Software Output Control Value

pub fn ch5ocv(&mut self) -> CH5OCV_W

Bit 13 - Channel 5 Software Output Control Value

pub fn ch6ocv(&mut self) -> CH6OCV_W

Bit 14 - Channel 6 Software Output Control Value

pub fn ch7ocv(&mut self) -> CH7OCV_W

Bit 15 - Channel 7 Software Output Control Value

impl W<u32, Reg<u32, _PWMLOAD>>

pub fn ch0sel(&mut self) -> CH0SEL_W

Bit 0 - Channel 0 Select

pub fn ch1sel(&mut self) -> CH1SEL_W

Bit 1 - Channel 1 Select

pub fn ch2sel(&mut self) -> CH2SEL_W

Bit 2 - Channel 2 Select

pub fn ch3sel(&mut self) -> CH3SEL_W

Bit 3 - Channel 3 Select

pub fn ch4sel(&mut self) -> CH4SEL_W

Bit 4 - Channel 4 Select

pub fn ch5sel(&mut self) -> CH5SEL_W

Bit 5 - Channel 5 Select

pub fn ch6sel(&mut self) -> CH6SEL_W

Bit 6 - Channel 6 Select

pub fn ch7sel(&mut self) -> CH7SEL_W

Bit 7 - Channel 7 Select

pub fn hcsel(&mut self) -> HCSEL_W

Bit 8 - Half Cycle Select

pub fn ldok(&mut self) -> LDOK_W

Bit 9 - Load Enable

pub fn glen(&mut self) -> GLEN_W

Bit 10 - Global Load Enable

pub fn gldok(&mut self) -> GLDOK_W

Bit 11 - Global Load OK

impl W<u32, Reg<u32, _HCR>>

pub fn hcval(&mut self) -> HCVAL_W

Bits 0:15 - Half Cycle Value

impl W<u32, Reg<u32, _PAIR0DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _PAIR1DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _PAIR2DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _PAIR3DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

pub fn dtvalex(&mut self) -> DTVALEX_W

Bits 16:19 - Extended Deadtime Value

impl W<u32, Reg<u32, _SC1>>

pub fn adch(&mut self) -> ADCH_W

Bits 0:4 - Input channel select

pub fn aien(&mut self) -> AIEN_W

Bit 6 - Interrupt Enable

impl W<u32, Reg<u32, _CFG1>>

pub fn adiclk(&mut self) -> ADICLK_W

Bits 0:1 - Input Clock Select

pub fn mode(&mut self) -> MODE_W

Bits 2:3 - Conversion mode selection

pub fn adiv(&mut self) -> ADIV_W

Bits 5:6 - Clock Divide Select

pub fn clrltrg(&mut self) -> CLRLTRG_W

Bit 8 - Clear Latch Trigger in Trigger Handler Block

impl W<u32, Reg<u32, _CFG2>>

pub fn smplts(&mut self) -> SMPLTS_W

Bits 0:7 - Sample Time Select

impl W<u32, Reg<u32, _CV>>

pub fn cv(&mut self) -> CV_W

Bits 0:15 - Compare Value.

impl W<u32, Reg<u32, _SC2>>

pub fn refsel(&mut self) -> REFSEL_W

Bits 0:1 - Voltage Reference Selection

pub fn dmaen(&mut self) -> DMAEN_W

Bit 2 - DMA Enable

pub fn acren(&mut self) -> ACREN_W

Bit 3 - Compare Function Range Enable

pub fn acfgt(&mut self) -> ACFGT_W

Bit 4 - Compare Function Greater Than Enable

pub fn acfe(&mut self) -> ACFE_W

Bit 5 - Compare Function Enable

pub fn adtrg(&mut self) -> ADTRG_W

Bit 6 - Conversion Trigger Select

impl W<u32, Reg<u32, _SC3>>

pub fn avgs(&mut self) -> AVGS_W

Bits 0:1 - Hardware Average Select

pub fn avge(&mut self) -> AVGE_W

Bit 2 - Hardware Average Enable

pub fn adco(&mut self) -> ADCO_W

Bit 3 - Continuous Conversion Enable

pub fn cal(&mut self) -> CAL_W

Bit 7 - Calibration

impl W<u32, Reg<u32, _BASE_OFS>>

pub fn ba_ofs(&mut self) -> BA_OFS_W

Bits 0:7 - Base Offset Error Correction Value

impl W<u32, Reg<u32, _OFS>>

pub fn ofs(&mut self) -> OFS_W

Bits 0:15 - Offset Error Correction Value

impl W<u32, Reg<u32, _USR_OFS>>

pub fn usr_ofs(&mut self) -> USR_OFS_W

Bits 0:7 - USER Offset Error Correction Value

impl W<u32, Reg<u32, _XOFS>>

pub fn xofs(&mut self) -> XOFS_W

Bits 0:5 - X offset error correction value

impl W<u32, Reg<u32, _YOFS>>

pub fn yofs(&mut self) -> YOFS_W

Bits 0:7 - Y offset error correction value

impl W<u32, Reg<u32, _G>>

pub fn g(&mut self) -> G_W

Bits 0:10 - Gain error adjustment factor for the overall conversion

impl W<u32, Reg<u32, _UG>>

pub fn ug(&mut self) -> UG_W

Bits 0:9 - User gain error correction value

impl W<u32, Reg<u32, _CLPS>>

pub fn clps(&mut self) -> CLPS_W

Bits 0:6 - Calibration Value

impl W<u32, Reg<u32, _CLP3>>

pub fn clp3(&mut self) -> CLP3_W

Bits 0:9 - Calibration Value

impl W<u32, Reg<u32, _CLP2>>

pub fn clp2(&mut self) -> CLP2_W

Bits 0:9 - Calibration Value

impl W<u32, Reg<u32, _CLP1>>

pub fn clp1(&mut self) -> CLP1_W

Bits 0:8 - Calibration Value

impl W<u32, Reg<u32, _CLP0>>

pub fn clp0(&mut self) -> CLP0_W

Bits 0:7 - Calibration Value

impl W<u32, Reg<u32, _CLPX>>

pub fn clpx(&mut self) -> CLPX_W

Bits 0:6 - Calibration Value

impl W<u32, Reg<u32, _CLP9>>

pub fn clp9(&mut self) -> CLP9_W

Bits 0:6 - Calibration Value

impl W<u32, Reg<u32, _CLPS_OFS>>

pub fn clps_ofs(&mut self) -> CLPS_OFS_W

Bits 0:3 - CLPS Offset

impl W<u32, Reg<u32, _CLP3_OFS>>

pub fn clp3_ofs(&mut self) -> CLP3_OFS_W

Bits 0:3 - CLP3 Offset

impl W<u32, Reg<u32, _CLP2_OFS>>

pub fn clp2_ofs(&mut self) -> CLP2_OFS_W

Bits 0:3 - CLP2 Offset

impl W<u32, Reg<u32, _CLP1_OFS>>

pub fn clp1_ofs(&mut self) -> CLP1_OFS_W

Bits 0:3 - CLP1 Offset

impl W<u32, Reg<u32, _CLP0_OFS>>

pub fn clp0_ofs(&mut self) -> CLP0_OFS_W

Bits 0:3 - CLP0 Offset

impl W<u32, Reg<u32, _CLPX_OFS>>

pub fn clpx_ofs(&mut self) -> CLPX_OFS_W

Bits 0:11 - CLPX Offset

impl W<u32, Reg<u32, _CLP9_OFS>>

pub fn clp9_ofs(&mut self) -> CLP9_OFS_W

Bits 0:11 - CLP9 Offset

impl W<u32, Reg<u32, _SC1>>

pub fn adch(&mut self) -> ADCH_W

Bits 0:4 - Input channel select

pub fn aien(&mut self) -> AIEN_W

Bit 6 - Interrupt Enable

impl W<u32, Reg<u32, _CFG1>>

pub fn adiclk(&mut self) -> ADICLK_W

Bits 0:1 - Input Clock Select

pub fn mode(&mut self) -> MODE_W

Bits 2:3 - Conversion mode selection

pub fn adiv(&mut self) -> ADIV_W

Bits 5:6 - Clock Divide Select

pub fn clrltrg(&mut self) -> CLRLTRG_W

Bit 8 - Clear Latch Trigger in Trigger Handler Block

impl W<u32, Reg<u32, _CFG2>>

pub fn smplts(&mut self) -> SMPLTS_W

Bits 0:7 - Sample Time Select

impl W<u32, Reg<u32, _CV>>

pub fn cv(&mut self) -> CV_W

Bits 0:15 - Compare Value.

impl W<u32, Reg<u32, _SC2>>

pub fn refsel(&mut self) -> REFSEL_W

Bits 0:1 - Voltage Reference Selection

pub fn dmaen(&mut self) -> DMAEN_W

Bit 2 - DMA Enable

pub fn acren(&mut self) -> ACREN_W

Bit 3 - Compare Function Range Enable

pub fn acfgt(&mut self) -> ACFGT_W

Bit 4 - Compare Function Greater Than Enable

pub fn acfe(&mut self) -> ACFE_W

Bit 5 - Compare Function Enable

pub fn adtrg(&mut self) -> ADTRG_W

Bit 6 - Conversion Trigger Select

impl W<u32, Reg<u32, _SC3>>

pub fn avgs(&mut self) -> AVGS_W

Bits 0:1 - Hardware Average Select

pub fn avge(&mut self) -> AVGE_W

Bit 2 - Hardware Average Enable

pub fn adco(&mut self) -> ADCO_W

Bit 3 - Continuous Conversion Enable

pub fn cal(&mut self) -> CAL_W

Bit 7 - Calibration

impl W<u32, Reg<u32, _BASE_OFS>>

pub fn ba_ofs(&mut self) -> BA_OFS_W

Bits 0:7 - Base Offset Error Correction Value

impl W<u32, Reg<u32, _OFS>>

pub fn ofs(&mut self) -> OFS_W

Bits 0:15 - Offset Error Correction Value

impl W<u32, Reg<u32, _USR_OFS>>

pub fn usr_ofs(&mut self) -> USR_OFS_W

Bits 0:7 - USER Offset Error Correction Value

impl W<u32, Reg<u32, _XOFS>>

pub fn xofs(&mut self) -> XOFS_W

Bits 0:5 - X offset error correction value

impl W<u32, Reg<u32, _YOFS>>

pub fn yofs(&mut self) -> YOFS_W

Bits 0:7 - Y offset error correction value

impl W<u32, Reg<u32, _G>>

pub fn g(&mut self) -> G_W

Bits 0:10 - Gain error adjustment factor for the overall conversion

impl W<u32, Reg<u32, _UG>>

pub fn ug(&mut self) -> UG_W

Bits 0:9 - User gain error correction value

impl W<u32, Reg<u32, _CLPS>>

pub fn clps(&mut self) -> CLPS_W

Bits 0:6 - Calibration Value

impl W<u32, Reg<u32, _CLP3>>

pub fn clp3(&mut self) -> CLP3_W

Bits 0:9 - Calibration Value

impl W<u32, Reg<u32, _CLP2>>

pub fn clp2(&mut self) -> CLP2_W

Bits 0:9 - Calibration Value

impl W<u32, Reg<u32, _CLP1>>

pub fn clp1(&mut self) -> CLP1_W

Bits 0:8 - Calibration Value

impl W<u32, Reg<u32, _CLP0>>

pub fn clp0(&mut self) -> CLP0_W

Bits 0:7 - Calibration Value

impl W<u32, Reg<u32, _CLPX>>

pub fn clpx(&mut self) -> CLPX_W

Bits 0:6 - Calibration Value

impl W<u32, Reg<u32, _CLP9>>

pub fn clp9(&mut self) -> CLP9_W

Bits 0:6 - Calibration Value

impl W<u32, Reg<u32, _CLPS_OFS>>

pub fn clps_ofs(&mut self) -> CLPS_OFS_W

Bits 0:3 - CLPS Offset

impl W<u32, Reg<u32, _CLP3_OFS>>

pub fn clp3_ofs(&mut self) -> CLP3_OFS_W

Bits 0:3 - CLP3 Offset

impl W<u32, Reg<u32, _CLP2_OFS>>

pub fn clp2_ofs(&mut self) -> CLP2_OFS_W

Bits 0:3 - CLP2 Offset

impl W<u32, Reg<u32, _CLP1_OFS>>

pub fn clp1_ofs(&mut self) -> CLP1_OFS_W

Bits 0:3 - CLP1 Offset

impl W<u32, Reg<u32, _CLP0_OFS>>

pub fn clp0_ofs(&mut self) -> CLP0_OFS_W

Bits 0:3 - CLP0 Offset

impl W<u32, Reg<u32, _CLPX_OFS>>

pub fn clpx_ofs(&mut self) -> CLPX_OFS_W

Bits 0:11 - CLPX Offset

impl W<u32, Reg<u32, _CLP9_OFS>>

pub fn clp9_ofs(&mut self) -> CLP9_OFS_W

Bits 0:11 - CLP9 Offset

impl W<u32, Reg<u32, _CR>>

pub fn men(&mut self) -> MEN_W

Bit 0 - Module Enable

pub fn rst(&mut self) -> RST_W

Bit 1 - Software Reset

pub fn dozen(&mut self) -> DOZEN_W

Bit 2 - Doze mode enable

pub fn dbgen(&mut self) -> DBGEN_W

Bit 3 - Debug Enable

pub fn rtf(&mut self) -> RTF_W

Bit 8 - Reset Transmit FIFO

pub fn rrf(&mut self) -> RRF_W

Bit 9 - Reset Receive FIFO

impl W<u32, Reg<u32, _SR>>

pub fn wcf(&mut self) -> WCF_W

Bit 8 - Word Complete Flag

pub fn fcf(&mut self) -> FCF_W

Bit 9 - Frame Complete Flag

pub fn tcf(&mut self) -> TCF_W

Bit 10 - Transfer Complete Flag

pub fn tef(&mut self) -> TEF_W

Bit 11 - Transmit Error Flag

pub fn ref_(&mut self) -> REF_W

Bit 12 - Receive Error Flag

pub fn dmf(&mut self) -> DMF_W

Bit 13 - Data Match Flag

impl W<u32, Reg<u32, _IER>>

pub fn tdie(&mut self) -> TDIE_W

Bit 0 - Transmit Data Interrupt Enable

pub fn rdie(&mut self) -> RDIE_W

Bit 1 - Receive Data Interrupt Enable

pub fn wcie(&mut self) -> WCIE_W

Bit 8 - Word Complete Interrupt Enable

pub fn fcie(&mut self) -> FCIE_W

Bit 9 - Frame Complete Interrupt Enable

pub fn tcie(&mut self) -> TCIE_W

Bit 10 - Transfer Complete Interrupt Enable

pub fn teie(&mut self) -> TEIE_W

Bit 11 - Transmit Error Interrupt Enable

pub fn reie(&mut self) -> REIE_W

Bit 12 - Receive Error Interrupt Enable

pub fn dmie(&mut self) -> DMIE_W

Bit 13 - Data Match Interrupt Enable

impl W<u32, Reg<u32, _DER>>

pub fn tdde(&mut self) -> TDDE_W

Bit 0 - Transmit Data DMA Enable

pub fn rdde(&mut self) -> RDDE_W

Bit 1 - Receive Data DMA Enable

impl W<u32, Reg<u32, _CFGR0>>

pub fn hren(&mut self) -> HREN_W

Bit 0 - Host Request Enable

pub fn hrpol(&mut self) -> HRPOL_W

Bit 1 - Host Request Polarity

pub fn hrsel(&mut self) -> HRSEL_W

Bit 2 - Host Request Select

pub fn cirfifo(&mut self) -> CIRFIFO_W

Bit 8 - Circular FIFO Enable

pub fn rdmo(&mut self) -> RDMO_W

Bit 9 - Receive Data Match Only

impl W<u32, Reg<u32, _CFGR1>>

pub fn master(&mut self) -> MASTER_W

Bit 0 - Master Mode

pub fn sample(&mut self) -> SAMPLE_W

Bit 1 - Sample Point

pub fn autopcs(&mut self) -> AUTOPCS_W

Bit 2 - Automatic PCS

pub fn nostall(&mut self) -> NOSTALL_W

Bit 3 - No Stall

pub fn pcspol(&mut self) -> PCSPOL_W

Bits 8:11 - Peripheral Chip Select Polarity

pub fn matcfg(&mut self) -> MATCFG_W

Bits 16:18 - Match Configuration

pub fn pincfg(&mut self) -> PINCFG_W

Bits 24:25 - Pin Configuration

pub fn outcfg(&mut self) -> OUTCFG_W

Bit 26 - Output Config

pub fn pcscfg(&mut self) -> PCSCFG_W

Bit 27 - Peripheral Chip Select Configuration

impl W<u32, Reg<u32, _DMR0>>

pub fn match0(&mut self) -> MATCH0_W

Bits 0:31 - Match 0 Value

impl W<u32, Reg<u32, _DMR1>>

pub fn match1(&mut self) -> MATCH1_W

Bits 0:31 - Match 1 Value

impl W<u32, Reg<u32, _CCR>>

pub fn sckdiv(&mut self) -> SCKDIV_W

Bits 0:7 - SCK Divider

pub fn dbt(&mut self) -> DBT_W

Bits 8:15 - Delay Between Transfers

pub fn pcssck(&mut self) -> PCSSCK_W

Bits 16:23 - PCS to SCK Delay

pub fn sckpcs(&mut self) -> SCKPCS_W

Bits 24:31 - SCK to PCS Delay

impl W<u32, Reg<u32, _FCR>>

pub fn txwater(&mut self) -> TXWATER_W

Bits 0:1 - Transmit FIFO Watermark

pub fn rxwater(&mut self) -> RXWATER_W

Bits 16:17 - Receive FIFO Watermark

impl W<u32, Reg<u32, _TCR>>

pub fn framesz(&mut self) -> FRAMESZ_W

Bits 0:11 - Frame Size

pub fn width(&mut self) -> WIDTH_W

Bits 16:17 - Transfer Width

pub fn txmsk(&mut self) -> TXMSK_W

Bit 18 - Transmit Data Mask

pub fn rxmsk(&mut self) -> RXMSK_W

Bit 19 - Receive Data Mask

pub fn contc(&mut self) -> CONTC_W

Bit 20 - Continuing Command

pub fn cont(&mut self) -> CONT_W

Bit 21 - Continuous Transfer

pub fn bysw(&mut self) -> BYSW_W

Bit 22 - Byte Swap

pub fn lsbf(&mut self) -> LSBF_W

Bit 23 - LSB First

pub fn pcs(&mut self) -> PCS_W

Bits 24:25 - Peripheral Chip Select

pub fn prescale(&mut self) -> PRESCALE_W

Bits 27:29 - Prescaler Value

pub fn cpha(&mut self) -> CPHA_W

Bit 30 - Clock Phase

pub fn cpol(&mut self) -> CPOL_W

Bit 31 - Clock Polarity

impl W<u32, Reg<u32, _TDR>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Transmit Data

impl W<u32, Reg<u32, _CR>>

pub fn men(&mut self) -> MEN_W

Bit 0 - Module Enable

pub fn rst(&mut self) -> RST_W

Bit 1 - Software Reset

pub fn dozen(&mut self) -> DOZEN_W

Bit 2 - Doze mode enable

pub fn dbgen(&mut self) -> DBGEN_W

Bit 3 - Debug Enable

pub fn rtf(&mut self) -> RTF_W

Bit 8 - Reset Transmit FIFO

pub fn rrf(&mut self) -> RRF_W

Bit 9 - Reset Receive FIFO

impl W<u32, Reg<u32, _SR>>

pub fn wcf(&mut self) -> WCF_W

Bit 8 - Word Complete Flag

pub fn fcf(&mut self) -> FCF_W

Bit 9 - Frame Complete Flag

pub fn tcf(&mut self) -> TCF_W

Bit 10 - Transfer Complete Flag

pub fn tef(&mut self) -> TEF_W

Bit 11 - Transmit Error Flag

pub fn ref_(&mut self) -> REF_W

Bit 12 - Receive Error Flag

pub fn dmf(&mut self) -> DMF_W

Bit 13 - Data Match Flag

impl W<u32, Reg<u32, _IER>>

pub fn tdie(&mut self) -> TDIE_W

Bit 0 - Transmit Data Interrupt Enable

pub fn rdie(&mut self) -> RDIE_W

Bit 1 - Receive Data Interrupt Enable

pub fn wcie(&mut self) -> WCIE_W

Bit 8 - Word Complete Interrupt Enable

pub fn fcie(&mut self) -> FCIE_W

Bit 9 - Frame Complete Interrupt Enable

pub fn tcie(&mut self) -> TCIE_W

Bit 10 - Transfer Complete Interrupt Enable

pub fn teie(&mut self) -> TEIE_W

Bit 11 - Transmit Error Interrupt Enable

pub fn reie(&mut self) -> REIE_W

Bit 12 - Receive Error Interrupt Enable

pub fn dmie(&mut self) -> DMIE_W

Bit 13 - Data Match Interrupt Enable

impl W<u32, Reg<u32, _DER>>

pub fn tdde(&mut self) -> TDDE_W

Bit 0 - Transmit Data DMA Enable

pub fn rdde(&mut self) -> RDDE_W

Bit 1 - Receive Data DMA Enable

impl W<u32, Reg<u32, _CFGR0>>

pub fn hren(&mut self) -> HREN_W

Bit 0 - Host Request Enable

pub fn hrpol(&mut self) -> HRPOL_W

Bit 1 - Host Request Polarity

pub fn hrsel(&mut self) -> HRSEL_W

Bit 2 - Host Request Select

pub fn cirfifo(&mut self) -> CIRFIFO_W

Bit 8 - Circular FIFO Enable

pub fn rdmo(&mut self) -> RDMO_W

Bit 9 - Receive Data Match Only

impl W<u32, Reg<u32, _CFGR1>>

pub fn master(&mut self) -> MASTER_W

Bit 0 - Master Mode

pub fn sample(&mut self) -> SAMPLE_W

Bit 1 - Sample Point

pub fn autopcs(&mut self) -> AUTOPCS_W

Bit 2 - Automatic PCS

pub fn nostall(&mut self) -> NOSTALL_W

Bit 3 - No Stall

pub fn pcspol(&mut self) -> PCSPOL_W

Bits 8:11 - Peripheral Chip Select Polarity

pub fn matcfg(&mut self) -> MATCFG_W

Bits 16:18 - Match Configuration

pub fn pincfg(&mut self) -> PINCFG_W

Bits 24:25 - Pin Configuration

pub fn outcfg(&mut self) -> OUTCFG_W

Bit 26 - Output Config

pub fn pcscfg(&mut self) -> PCSCFG_W

Bit 27 - Peripheral Chip Select Configuration

impl W<u32, Reg<u32, _DMR0>>

pub fn match0(&mut self) -> MATCH0_W

Bits 0:31 - Match 0 Value

impl W<u32, Reg<u32, _DMR1>>

pub fn match1(&mut self) -> MATCH1_W

Bits 0:31 - Match 1 Value

impl W<u32, Reg<u32, _CCR>>

pub fn sckdiv(&mut self) -> SCKDIV_W

Bits 0:7 - SCK Divider

pub fn dbt(&mut self) -> DBT_W

Bits 8:15 - Delay Between Transfers

pub fn pcssck(&mut self) -> PCSSCK_W

Bits 16:23 - PCS to SCK Delay

pub fn sckpcs(&mut self) -> SCKPCS_W

Bits 24:31 - SCK to PCS Delay

impl W<u32, Reg<u32, _FCR>>

pub fn txwater(&mut self) -> TXWATER_W

Bits 0:1 - Transmit FIFO Watermark

pub fn rxwater(&mut self) -> RXWATER_W

Bits 16:17 - Receive FIFO Watermark

impl W<u32, Reg<u32, _TCR>>

pub fn framesz(&mut self) -> FRAMESZ_W

Bits 0:11 - Frame Size

pub fn width(&mut self) -> WIDTH_W

Bits 16:17 - Transfer Width

pub fn txmsk(&mut self) -> TXMSK_W

Bit 18 - Transmit Data Mask

pub fn rxmsk(&mut self) -> RXMSK_W

Bit 19 - Receive Data Mask

pub fn contc(&mut self) -> CONTC_W

Bit 20 - Continuing Command

pub fn cont(&mut self) -> CONT_W

Bit 21 - Continuous Transfer

pub fn bysw(&mut self) -> BYSW_W

Bit 22 - Byte Swap

pub fn lsbf(&mut self) -> LSBF_W

Bit 23 - LSB First

pub fn pcs(&mut self) -> PCS_W

Bits 24:25 - Peripheral Chip Select

pub fn prescale(&mut self) -> PRESCALE_W

Bits 27:29 - Prescaler Value

pub fn cpha(&mut self) -> CPHA_W

Bit 30 - Clock Phase

pub fn cpol(&mut self) -> CPOL_W

Bit 31 - Clock Polarity

impl W<u32, Reg<u32, _TDR>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Transmit Data

impl W<u32, Reg<u32, _CR>>

pub fn men(&mut self) -> MEN_W

Bit 0 - Module Enable

pub fn rst(&mut self) -> RST_W

Bit 1 - Software Reset

pub fn dozen(&mut self) -> DOZEN_W

Bit 2 - Doze mode enable

pub fn dbgen(&mut self) -> DBGEN_W

Bit 3 - Debug Enable

pub fn rtf(&mut self) -> RTF_W

Bit 8 - Reset Transmit FIFO

pub fn rrf(&mut self) -> RRF_W

Bit 9 - Reset Receive FIFO

impl W<u32, Reg<u32, _SR>>

pub fn wcf(&mut self) -> WCF_W

Bit 8 - Word Complete Flag

pub fn fcf(&mut self) -> FCF_W

Bit 9 - Frame Complete Flag

pub fn tcf(&mut self) -> TCF_W

Bit 10 - Transfer Complete Flag

pub fn tef(&mut self) -> TEF_W

Bit 11 - Transmit Error Flag

pub fn ref_(&mut self) -> REF_W

Bit 12 - Receive Error Flag

pub fn dmf(&mut self) -> DMF_W

Bit 13 - Data Match Flag

impl W<u32, Reg<u32, _IER>>

pub fn tdie(&mut self) -> TDIE_W

Bit 0 - Transmit Data Interrupt Enable

pub fn rdie(&mut self) -> RDIE_W

Bit 1 - Receive Data Interrupt Enable

pub fn wcie(&mut self) -> WCIE_W

Bit 8 - Word Complete Interrupt Enable

pub fn fcie(&mut self) -> FCIE_W

Bit 9 - Frame Complete Interrupt Enable

pub fn tcie(&mut self) -> TCIE_W

Bit 10 - Transfer Complete Interrupt Enable

pub fn teie(&mut self) -> TEIE_W

Bit 11 - Transmit Error Interrupt Enable

pub fn reie(&mut self) -> REIE_W

Bit 12 - Receive Error Interrupt Enable

pub fn dmie(&mut self) -> DMIE_W

Bit 13 - Data Match Interrupt Enable

impl W<u32, Reg<u32, _DER>>

pub fn tdde(&mut self) -> TDDE_W

Bit 0 - Transmit Data DMA Enable

pub fn rdde(&mut self) -> RDDE_W

Bit 1 - Receive Data DMA Enable

impl W<u32, Reg<u32, _CFGR0>>

pub fn hren(&mut self) -> HREN_W

Bit 0 - Host Request Enable

pub fn hrpol(&mut self) -> HRPOL_W

Bit 1 - Host Request Polarity

pub fn hrsel(&mut self) -> HRSEL_W

Bit 2 - Host Request Select

pub fn cirfifo(&mut self) -> CIRFIFO_W

Bit 8 - Circular FIFO Enable

pub fn rdmo(&mut self) -> RDMO_W

Bit 9 - Receive Data Match Only

impl W<u32, Reg<u32, _CFGR1>>

pub fn master(&mut self) -> MASTER_W

Bit 0 - Master Mode

pub fn sample(&mut self) -> SAMPLE_W

Bit 1 - Sample Point

pub fn autopcs(&mut self) -> AUTOPCS_W

Bit 2 - Automatic PCS

pub fn nostall(&mut self) -> NOSTALL_W

Bit 3 - No Stall

pub fn pcspol(&mut self) -> PCSPOL_W

Bits 8:11 - Peripheral Chip Select Polarity

pub fn matcfg(&mut self) -> MATCFG_W

Bits 16:18 - Match Configuration

pub fn pincfg(&mut self) -> PINCFG_W

Bits 24:25 - Pin Configuration

pub fn outcfg(&mut self) -> OUTCFG_W

Bit 26 - Output Config

pub fn pcscfg(&mut self) -> PCSCFG_W

Bit 27 - Peripheral Chip Select Configuration

impl W<u32, Reg<u32, _DMR0>>

pub fn match0(&mut self) -> MATCH0_W

Bits 0:31 - Match 0 Value

impl W<u32, Reg<u32, _DMR1>>

pub fn match1(&mut self) -> MATCH1_W

Bits 0:31 - Match 1 Value

impl W<u32, Reg<u32, _CCR>>

pub fn sckdiv(&mut self) -> SCKDIV_W

Bits 0:7 - SCK Divider

pub fn dbt(&mut self) -> DBT_W

Bits 8:15 - Delay Between Transfers

pub fn pcssck(&mut self) -> PCSSCK_W

Bits 16:23 - PCS to SCK Delay

pub fn sckpcs(&mut self) -> SCKPCS_W

Bits 24:31 - SCK to PCS Delay

impl W<u32, Reg<u32, _FCR>>

pub fn txwater(&mut self) -> TXWATER_W

Bits 0:1 - Transmit FIFO Watermark

pub fn rxwater(&mut self) -> RXWATER_W

Bits 16:17 - Receive FIFO Watermark

impl W<u32, Reg<u32, _TCR>>

pub fn framesz(&mut self) -> FRAMESZ_W

Bits 0:11 - Frame Size

pub fn width(&mut self) -> WIDTH_W

Bits 16:17 - Transfer Width

pub fn txmsk(&mut self) -> TXMSK_W

Bit 18 - Transmit Data Mask

pub fn rxmsk(&mut self) -> RXMSK_W

Bit 19 - Receive Data Mask

pub fn contc(&mut self) -> CONTC_W

Bit 20 - Continuing Command

pub fn cont(&mut self) -> CONT_W

Bit 21 - Continuous Transfer

pub fn bysw(&mut self) -> BYSW_W

Bit 22 - Byte Swap

pub fn lsbf(&mut self) -> LSBF_W

Bit 23 - LSB First

pub fn pcs(&mut self) -> PCS_W

Bits 24:25 - Peripheral Chip Select

pub fn prescale(&mut self) -> PRESCALE_W

Bits 27:29 - Prescaler Value

pub fn cpha(&mut self) -> CPHA_W

Bit 30 - Clock Phase

pub fn cpol(&mut self) -> CPOL_W

Bit 31 - Clock Polarity

impl W<u32, Reg<u32, _TDR>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Transmit Data

impl W<u32, Reg<u32, _SC>>

pub fn ldok(&mut self) -> LDOK_W

Bit 0 - Load OK

pub fn cont(&mut self) -> CONT_W

Bit 1 - Continuous Mode Enable

pub fn mult(&mut self) -> MULT_W

Bits 2:3 - Multiplication Factor Select for Prescaler

pub fn pdbie(&mut self) -> PDBIE_W

Bit 5 - PDB Interrupt Enable

pub fn pdbif(&mut self) -> PDBIF_W

Bit 6 - PDB Interrupt Flag

pub fn pdben(&mut self) -> PDBEN_W

Bit 7 - PDB Enable

pub fn trgsel(&mut self) -> TRGSEL_W

Bits 8:11 - Trigger Input Source Select

pub fn prescaler(&mut self) -> PRESCALER_W

Bits 12:14 - Prescaler Divider Select

pub fn dmaen(&mut self) -> DMAEN_W

Bit 15 - DMA Enable

pub fn swtrig(&mut self) -> SWTRIG_W

Bit 16 - Software Trigger

pub fn pdbeie(&mut self) -> PDBEIE_W

Bit 17 - PDB Sequence Error Interrupt Enable

pub fn ldmod(&mut self) -> LDMOD_W

Bits 18:19 - Load Mode Select

impl W<u32, Reg<u32, _MOD>>

pub fn mod_(&mut self) -> MOD_W

Bits 0:15 - PDB Modulus

impl W<u32, Reg<u32, _IDLY>>

pub fn idly(&mut self) -> IDLY_W

Bits 0:15 - PDB Interrupt Delay

impl W<u32, Reg<u32, _CHC1>>

pub fn en(&mut self) -> EN_W

Bits 0:7 - PDB Channel Pre-Trigger Enable

pub fn tos(&mut self) -> TOS_W

Bits 8:15 - PDB Channel Pre-Trigger Output Select

pub fn bb(&mut self) -> BB_W

Bits 16:23 - PDB Channel Pre-Trigger Back-to-Back Operation Enable

impl W<u32, Reg<u32, _CHS>>

pub fn err(&mut self) -> ERR_W

Bits 0:7 - PDB Channel Sequence Error Flags

pub fn cf(&mut self) -> CF_W

Bits 16:23 - PDB Channel Flags

impl W<u32, Reg<u32, _CHDLY0>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _CHDLY1>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _CHDLY2>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _CHDLY3>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _CHDLY4>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _CHDLY5>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _CHDLY6>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _CHDLY7>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _POEN>>

pub fn poen(&mut self) -> POEN_W

Bits 0:7 - PDB Pulse-Out Enable

impl W<u32, Reg<u32, _PODLY>>

pub fn dly2(&mut self) -> DLY2_W

Bits 0:15 - PDB Pulse-Out Delay 2

pub fn dly1(&mut self) -> DLY1_W

Bits 16:31 - PDB Pulse-Out Delay 1

impl W<u16, Reg<u16, _DLY2>>

pub fn dly2(&mut self) -> DLY2_W

Bits 0:15 - DLY2

impl W<u16, Reg<u16, _DLY1>>

pub fn dly1(&mut self) -> DLY1_W

Bits 0:15 - DLY1

impl W<u32, Reg<u32, _SC>>

pub fn ldok(&mut self) -> LDOK_W

Bit 0 - Load OK

pub fn cont(&mut self) -> CONT_W

Bit 1 - Continuous Mode Enable

pub fn mult(&mut self) -> MULT_W

Bits 2:3 - Multiplication Factor Select for Prescaler

pub fn pdbie(&mut self) -> PDBIE_W

Bit 5 - PDB Interrupt Enable

pub fn pdbif(&mut self) -> PDBIF_W

Bit 6 - PDB Interrupt Flag

pub fn pdben(&mut self) -> PDBEN_W

Bit 7 - PDB Enable

pub fn trgsel(&mut self) -> TRGSEL_W

Bits 8:11 - Trigger Input Source Select

pub fn prescaler(&mut self) -> PRESCALER_W

Bits 12:14 - Prescaler Divider Select

pub fn dmaen(&mut self) -> DMAEN_W

Bit 15 - DMA Enable

pub fn swtrig(&mut self) -> SWTRIG_W

Bit 16 - Software Trigger

pub fn pdbeie(&mut self) -> PDBEIE_W

Bit 17 - PDB Sequence Error Interrupt Enable

pub fn ldmod(&mut self) -> LDMOD_W

Bits 18:19 - Load Mode Select

impl W<u32, Reg<u32, _MOD>>

pub fn mod_(&mut self) -> MOD_W

Bits 0:15 - PDB Modulus

impl W<u32, Reg<u32, _IDLY>>

pub fn idly(&mut self) -> IDLY_W

Bits 0:15 - PDB Interrupt Delay

impl W<u32, Reg<u32, _CHC1>>

pub fn en(&mut self) -> EN_W

Bits 0:7 - PDB Channel Pre-Trigger Enable

pub fn tos(&mut self) -> TOS_W

Bits 8:15 - PDB Channel Pre-Trigger Output Select

pub fn bb(&mut self) -> BB_W

Bits 16:23 - PDB Channel Pre-Trigger Back-to-Back Operation Enable

impl W<u32, Reg<u32, _CHS>>

pub fn err(&mut self) -> ERR_W

Bits 0:7 - PDB Channel Sequence Error Flags

pub fn cf(&mut self) -> CF_W

Bits 16:23 - PDB Channel Flags

impl W<u32, Reg<u32, _CHDLY0>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _CHDLY1>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _CHDLY2>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _CHDLY3>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _CHDLY4>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _CHDLY5>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _CHDLY6>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _CHDLY7>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _POEN>>

pub fn poen(&mut self) -> POEN_W

Bits 0:7 - PDB Pulse-Out Enable

impl W<u32, Reg<u32, _PODLY>>

pub fn dly2(&mut self) -> DLY2_W

Bits 0:15 - PDB Pulse-Out Delay 2

pub fn dly1(&mut self) -> DLY1_W

Bits 16:31 - PDB Pulse-Out Delay 1

impl W<u16, Reg<u16, _DLY2>>

pub fn dly2(&mut self) -> DLY2_W

Bits 0:15 - DLY2

impl W<u16, Reg<u16, _DLY1>>

pub fn dly1(&mut self) -> DLY1_W

Bits 0:15 - DLY1

impl W<u32, Reg<u32, _DATA>>

pub fn ll(&mut self) -> LL_W

Bits 0:7 - CRC Low Lower Byte

pub fn lu(&mut self) -> LU_W

Bits 8:15 - CRC Low Upper Byte

pub fn hl(&mut self) -> HL_W

Bits 16:23 - CRC High Lower Byte

pub fn hu(&mut self) -> HU_W

Bits 24:31 - CRC High Upper Byte

impl W<u16, Reg<u16, _DATAL>>

pub fn datal(&mut self) -> DATAL_W

Bits 0:15 - DATAL stores the lower 16 bits of the 16/32 bit CRC

impl W<u8, Reg<u8, _DATALL>>

pub fn datall(&mut self) -> DATALL_W

Bits 0:7 - CRCLL stores the first 8 bits of the 32 bit DATA

impl W<u8, Reg<u8, _DATALU>>

pub fn datalu(&mut self) -> DATALU_W

Bits 0:7 - DATALL stores the second 8 bits of the 32 bit CRC

impl W<u16, Reg<u16, _DATAH>>

pub fn datah(&mut self) -> DATAH_W

Bits 0:15 - DATAH stores the high 16 bits of the 16/32 bit CRC

impl W<u8, Reg<u8, _DATAHL>>

pub fn datahl(&mut self) -> DATAHL_W

Bits 0:7 - DATAHL stores the third 8 bits of the 32 bit CRC

impl W<u8, Reg<u8, _DATAHU>>

pub fn datahu(&mut self) -> DATAHU_W

Bits 0:7 - DATAHU stores the fourth 8 bits of the 32 bit CRC

impl W<u32, Reg<u32, _GPOLY>>

pub fn low(&mut self) -> LOW_W

Bits 0:15 - Low Polynominal Half-word

pub fn high(&mut self) -> HIGH_W

Bits 16:31 - High Polynominal Half-word

impl W<u32, Reg<u32, _CTRL>>

pub fn tcrc(&mut self) -> TCRC_W

Bit 24 - TCRC

pub fn was(&mut self) -> WAS_W

Bit 25 - Write CRC Data Register As Seed

pub fn fxor(&mut self) -> FXOR_W

Bit 26 - Complement Read Of CRC Data Register

pub fn totr(&mut self) -> TOTR_W

Bits 28:29 - Type Of Transpose For Read

pub fn tot(&mut self) -> TOT_W

Bits 30:31 - Type Of Transpose For Writes

impl W<u32, Reg<u32, _MCR>>

pub fn m_cen(&mut self) -> M_CEN_W

Bit 0 - Module Clock Enable

pub fn sw_rst(&mut self) -> SW_RST_W

Bit 1 - Software Reset Bit

pub fn doze_en(&mut self) -> DOZE_EN_W

Bit 2 - DOZE Mode Enable Bit

pub fn dbg_en(&mut self) -> DBG_EN_W

Bit 3 - Debug Enable Bit

impl W<u32, Reg<u32, _MSR>>

pub fn tif0(&mut self) -> TIF0_W

Bit 0 - Channel 0 Timer Interrupt Flag

pub fn tif1(&mut self) -> TIF1_W

Bit 1 - Channel 1 Timer Interrupt Flag

pub fn tif2(&mut self) -> TIF2_W

Bit 2 - Channel 2 Timer Interrupt Flag

pub fn tif3(&mut self) -> TIF3_W

Bit 3 - Channel 3 Timer Interrupt Flag

impl W<u32, Reg<u32, _MIER>>

pub fn tie0(&mut self) -> TIE0_W

Bit 0 - Channel 0 Timer Interrupt Enable

pub fn tie1(&mut self) -> TIE1_W

Bit 1 - Channel 1 Timer Interrupt Enable

pub fn tie2(&mut self) -> TIE2_W

Bit 2 - Channel 2 Timer Interrupt Enable

pub fn tie3(&mut self) -> TIE3_W

Bit 3 - Channel 3 Timer Interrupt Enable

impl W<u32, Reg<u32, _SETTEN>>

pub fn set_t_en_0(&mut self) -> SET_T_EN_0_W

Bit 0 - Set Timer 0 Enable

pub fn set_t_en_1(&mut self) -> SET_T_EN_1_W

Bit 1 - Set Timer 1 Enable

pub fn set_t_en_2(&mut self) -> SET_T_EN_2_W

Bit 2 - Set Timer 2 Enable

pub fn set_t_en_3(&mut self) -> SET_T_EN_3_W

Bit 3 - Set Timer 3 Enable

impl W<u32, Reg<u32, _CLRTEN>>

pub fn clr_t_en_0(&mut self) -> CLR_T_EN_0_W

Bit 0 - Clear Timer 0 Enable

pub fn clr_t_en_1(&mut self) -> CLR_T_EN_1_W

Bit 1 - Clear Timer 1 Enable

pub fn clr_t_en_2(&mut self) -> CLR_T_EN_2_W

Bit 2 - Clear Timer 2 Enable

pub fn clr_t_en_3(&mut self) -> CLR_T_EN_3_W

Bit 3 - Clear Timer 3 Enable

impl W<u32, Reg<u32, _TVAL0>>

pub fn tmr_val(&mut self) -> TMR_VAL_W

Bits 0:31 - Timer Value

impl W<u32, Reg<u32, _TCTRL0>>

pub fn t_en(&mut self) -> T_EN_W

Bit 0 - Timer Enable

pub fn chain(&mut self) -> CHAIN_W

Bit 1 - Chain Channel

pub fn mode(&mut self) -> MODE_W

Bits 2:3 - Timer Operation Mode

pub fn tsot(&mut self) -> TSOT_W

Bit 16 - Timer Start On Trigger

pub fn tsoi(&mut self) -> TSOI_W

Bit 17 - Timer Stop On Interrupt

pub fn trot(&mut self) -> TROT_W

Bit 18 - Timer Reload On Trigger

pub fn trg_src(&mut self) -> TRG_SRC_W

Bit 23 - Trigger Source

pub fn trg_sel(&mut self) -> TRG_SEL_W

Bits 24:27 - Trigger Select

impl W<u32, Reg<u32, _TVAL1>>

pub fn tmr_val(&mut self) -> TMR_VAL_W

Bits 0:31 - Timer Value

impl W<u32, Reg<u32, _TCTRL1>>

pub fn t_en(&mut self) -> T_EN_W

Bit 0 - Timer Enable

pub fn chain(&mut self) -> CHAIN_W

Bit 1 - Chain Channel

pub fn mode(&mut self) -> MODE_W

Bits 2:3 - Timer Operation Mode

pub fn tsot(&mut self) -> TSOT_W

Bit 16 - Timer Start On Trigger

pub fn tsoi(&mut self) -> TSOI_W

Bit 17 - Timer Stop On Interrupt

pub fn trot(&mut self) -> TROT_W

Bit 18 - Timer Reload On Trigger

pub fn trg_src(&mut self) -> TRG_SRC_W

Bit 23 - Trigger Source

pub fn trg_sel(&mut self) -> TRG_SEL_W

Bits 24:27 - Trigger Select

impl W<u32, Reg<u32, _TVAL2>>

pub fn tmr_val(&mut self) -> TMR_VAL_W

Bits 0:31 - Timer Value

impl W<u32, Reg<u32, _TCTRL2>>

pub fn t_en(&mut self) -> T_EN_W

Bit 0 - Timer Enable

pub fn chain(&mut self) -> CHAIN_W

Bit 1 - Chain Channel

pub fn mode(&mut self) -> MODE_W

Bits 2:3 - Timer Operation Mode

pub fn tsot(&mut self) -> TSOT_W

Bit 16 - Timer Start On Trigger

pub fn tsoi(&mut self) -> TSOI_W

Bit 17 - Timer Stop On Interrupt

pub fn trot(&mut self) -> TROT_W

Bit 18 - Timer Reload On Trigger

pub fn trg_src(&mut self) -> TRG_SRC_W

Bit 23 - Trigger Source

pub fn trg_sel(&mut self) -> TRG_SEL_W

Bits 24:27 - Trigger Select

impl W<u32, Reg<u32, _TVAL3>>

pub fn tmr_val(&mut self) -> TMR_VAL_W

Bits 0:31 - Timer Value

impl W<u32, Reg<u32, _TCTRL3>>

pub fn t_en(&mut self) -> T_EN_W

Bit 0 - Timer Enable

pub fn chain(&mut self) -> CHAIN_W

Bit 1 - Chain Channel

pub fn mode(&mut self) -> MODE_W

Bits 2:3 - Timer Operation Mode

pub fn tsot(&mut self) -> TSOT_W

Bit 16 - Timer Start On Trigger

pub fn tsoi(&mut self) -> TSOI_W

Bit 17 - Timer Stop On Interrupt

pub fn trot(&mut self) -> TROT_W

Bit 18 - Timer Reload On Trigger

pub fn trg_src(&mut self) -> TRG_SRC_W

Bit 23 - Trigger Source

pub fn trg_sel(&mut self) -> TRG_SEL_W

Bits 24:27 - Trigger Select

impl W<u32, Reg<u32, _TSR>>

pub fn tsr(&mut self) -> TSR_W

Bits 0:31 - Time Seconds Register

impl W<u32, Reg<u32, _TPR>>

pub fn tpr(&mut self) -> TPR_W

Bits 0:15 - Time Prescaler Register

impl W<u32, Reg<u32, _TAR>>

pub fn tar(&mut self) -> TAR_W

Bits 0:31 - Time Alarm Register

impl W<u32, Reg<u32, _TCR>>

pub fn tcr(&mut self) -> TCR_W

Bits 0:7 - Time Compensation Register

pub fn cir(&mut self) -> CIR_W

Bits 8:15 - Compensation Interval Register

impl W<u32, Reg<u32, _CR>>

pub fn swr(&mut self) -> SWR_W

Bit 0 - Software Reset

pub fn sup(&mut self) -> SUP_W

Bit 2 - Supervisor Access

pub fn um(&mut self) -> UM_W

Bit 3 - Update Mode

pub fn cps(&mut self) -> CPS_W

Bit 5 - Clock Pin Select

pub fn lpos(&mut self) -> LPOS_W

Bit 7 - LPO Select

pub fn cpe(&mut self) -> CPE_W

Bit 24 - Clock Pin Enable

impl W<u32, Reg<u32, _SR>>

pub fn tce(&mut self) -> TCE_W

Bit 4 - Time Counter Enable

impl W<u32, Reg<u32, _LR>>

pub fn tcl(&mut self) -> TCL_W

Bit 3 - Time Compensation Lock

pub fn crl(&mut self) -> CRL_W

Bit 4 - Control Register Lock

pub fn srl(&mut self) -> SRL_W

Bit 5 - Status Register Lock

pub fn lrl(&mut self) -> LRL_W

Bit 6 - Lock Register Lock

impl W<u32, Reg<u32, _IER>>

pub fn tiie(&mut self) -> TIIE_W

Bit 0 - Time Invalid Interrupt Enable

pub fn toie(&mut self) -> TOIE_W

Bit 1 - Time Overflow Interrupt Enable

pub fn taie(&mut self) -> TAIE_W

Bit 2 - Time Alarm Interrupt Enable

pub fn tsie(&mut self) -> TSIE_W

Bit 4 - Time Seconds Interrupt Enable

pub fn tsic(&mut self) -> TSIC_W

Bits 16:18 - Timer Seconds Interrupt Configuration

impl W<u32, Reg<u32, _CSR>>

pub fn ten(&mut self) -> TEN_W

Bit 0 - Timer Enable

pub fn tms(&mut self) -> TMS_W

Bit 1 - Timer Mode Select

pub fn tfc(&mut self) -> TFC_W

Bit 2 - Timer Free-Running Counter

pub fn tpp(&mut self) -> TPP_W

Bit 3 - Timer Pin Polarity

pub fn tps(&mut self) -> TPS_W

Bits 4:5 - Timer Pin Select

pub fn tie(&mut self) -> TIE_W

Bit 6 - Timer Interrupt Enable

pub fn tcf(&mut self) -> TCF_W

Bit 7 - Timer Compare Flag

pub fn tdre(&mut self) -> TDRE_W

Bit 8 - Timer DMA Request Enable

impl W<u32, Reg<u32, _PSR>>

pub fn pcs(&mut self) -> PCS_W

Bits 0:1 - Prescaler Clock Select

pub fn pbyp(&mut self) -> PBYP_W

Bit 2 - Prescaler Bypass

pub fn prescale(&mut self) -> PRESCALE_W

Bits 3:6 - Prescale Value

impl W<u32, Reg<u32, _CMR>>

pub fn compare(&mut self) -> COMPARE_W

Bits 0:15 - Compare Value

impl W<u32, Reg<u32, _CNR>>

pub fn counter(&mut self) -> COUNTER_W

Bits 0:15 - Counter Value

impl W<u32, Reg<u32, _CHIPCTL>>

pub fn adc_interleave_en(&mut self) -> ADC_INTERLEAVE_EN_W

Bits 0:3 - ADC interleave channel enable

pub fn clkoutsel(&mut self) -> CLKOUTSEL_W

Bits 4:7 - CLKOUT Select

pub fn clkoutdiv(&mut self) -> CLKOUTDIV_W

Bits 8:10 - CLKOUT Divide Ratio

pub fn clkouten(&mut self) -> CLKOUTEN_W

Bit 11 - CLKOUT enable

pub fn traceclk_sel(&mut self) -> TRACECLK_SEL_W

Bit 12 - Debug trace clock select

pub fn pdb_bb_sel(&mut self) -> PDB_BB_SEL_W

Bit 13 - PDB back-to-back select

pub fn adc_supply(&mut self) -> ADC_SUPPLY_W

Bits 16:18 - ADC_SUPPLY

pub fn adc_supplyen(&mut self) -> ADC_SUPPLYEN_W

Bit 19 - ADC_SUPPLYEN

pub fn sramu_reten(&mut self) -> SRAMU_RETEN_W

Bit 20 - SRAMU_RETEN

pub fn sraml_reten(&mut self) -> SRAML_RETEN_W

Bit 21 - SRAML_RETEN

impl W<u32, Reg<u32, _FTMOPT0>>

pub fn ftm0fltx_sel(&mut self) -> FTM0FLTXSEL_W

Bits 0:2 - FTM0 Fault X Select

pub fn ftm1fltx_sel(&mut self) -> FTM1FLTXSEL_W

Bits 4:6 - FTM1 Fault X Select

pub fn ftm2fltx_sel(&mut self) -> FTM2FLTXSEL_W

Bits 8:10 - FTM2 Fault X Select

pub fn ftm3fltx_sel(&mut self) -> FTM3FLTXSEL_W

Bits 12:14 - FTM3 Fault X Select

pub fn ftm0clksel(&mut self) -> FTM0CLKSEL_W

Bits 24:25 - FTM0 External Clock Pin Select

pub fn ftm1clksel(&mut self) -> FTM1CLKSEL_W

Bits 26:27 - FTM1 External Clock Pin Select

pub fn ftm2clksel(&mut self) -> FTM2CLKSEL_W

Bits 28:29 - FTM2 External Clock Pin Select

pub fn ftm3clksel(&mut self) -> FTM3CLKSEL_W

Bits 30:31 - FTM3 External Clock Pin Select

impl W<u32, Reg<u32, _LPOCLKS>>

pub fn lpo1kclken(&mut self) -> LPO1KCLKEN_W

Bit 0 - 1 kHz LPO_CLK enable

pub fn lpo32kclken(&mut self) -> LPO32KCLKEN_W

Bit 1 - 32 kHz LPO_CLK enable

pub fn lpoclksel(&mut self) -> LPOCLKSEL_W

Bits 2:3 - LPO clock source select

pub fn rtcclksel(&mut self) -> RTCCLKSEL_W

Bits 4:5 - 32 kHz clock source select

impl W<u32, Reg<u32, _ADCOPT>>

pub fn adc0trgsel(&mut self) -> ADC0TRGSEL_W

Bit 0 - ADC0 trigger source select

pub fn adc0swpretrg(&mut self) -> ADC0SWPRETRG_W

Bits 1:3 - ADC0 software pretrigger sources

pub fn adc0pretrgsel(&mut self) -> ADC0PRETRGSEL_W

Bits 4:5 - ADC0 pretrigger source select

pub fn adc1trgsel(&mut self) -> ADC1TRGSEL_W

Bit 8 - ADC1 trigger source select

pub fn adc1swpretrg(&mut self) -> ADC1SWPRETRG_W

Bits 9:11 - ADC1 software pretrigger sources

pub fn adc1pretrgsel(&mut self) -> ADC1PRETRGSEL_W

Bits 12:13 - ADC1 pretrigger source select

impl W<u32, Reg<u32, _FTMOPT1>>

pub fn ftm0syncbit(&mut self) -> FTM0SYNCBIT_W

Bit 0 - FTM0 Sync Bit

pub fn ftm1syncbit(&mut self) -> FTM1SYNCBIT_W

Bit 1 - FTM1 Sync Bit

pub fn ftm2syncbit(&mut self) -> FTM2SYNCBIT_W

Bit 2 - FTM2 Sync Bit

pub fn ftm3syncbit(&mut self) -> FTM3SYNCBIT_W

Bit 3 - FTM3 Sync Bit

pub fn ftm1ch0sel(&mut self) -> FTM1CH0SEL_W

Bits 4:5 - FTM1 CH0 Select

pub fn ftm2ch0sel(&mut self) -> FTM2CH0SEL_W

Bits 6:7 - FTM2 CH0 Select

pub fn ftm2ch1sel(&mut self) -> FTM2CH1SEL_W

Bit 8 - FTM2 CH1 Select

pub fn ftmgldok(&mut self) -> FTMGLDOK_W

Bit 15 - FTM global load enable

pub fn ftm0_outsel(&mut self) -> FTM0_OUTSEL_W

Bits 16:23 - FTM0 channel modulation select with FTM1_CH1

pub fn ftm3_outsel(&mut self) -> FTM3_OUTSEL_W

Bits 24:31 - FTM3 channel modulation select with FTM2_CH1

impl W<u32, Reg<u32, _MISCTRL0>>

pub fn ftm0_obe_ctrl(&mut self) -> FTM0_OBE_CTRL_W

Bit 16 - FTM0 OBE CTRL bit

pub fn ftm1_obe_ctrl(&mut self) -> FTM1_OBE_CTRL_W

Bit 17 - FTM1 OBE CTRL bit

pub fn ftm2_obe_ctrl(&mut self) -> FTM2_OBE_CTRL_W

Bit 18 - FTM2 OBE CTRL bit

pub fn ftm3_obe_ctrl(&mut self) -> FTM3_OBE_CTRL_W

Bit 19 - FTM3 OBE CTRL bit

impl W<u32, Reg<u32, _PLATCGC>>

pub fn cgcmscm(&mut self) -> CGCMSCM_W

Bit 0 - MSCM Clock Gating Control

pub fn cgcmpu(&mut self) -> CGCMPU_W

Bit 1 - MPU Clock Gating Control

pub fn cgcdma(&mut self) -> CGCDMA_W

Bit 2 - DMA Clock Gating Control

pub fn cgcerm(&mut self) -> CGCERM_W

Bit 3 - ERM Clock Gating Control

pub fn cgceim(&mut self) -> CGCEIM_W

Bit 4 - EIM Clock Gating Control

impl W<u32, Reg<u32, _CLKDIV4>>

pub fn tracefrac(&mut self) -> TRACEFRAC_W

Bit 0 - Trace Clock Divider fraction To configure TRACEDIV and TRACEFRAC, you must first clear TRACEDIVEN to disable the trace clock divide function.

pub fn tracediv(&mut self) -> TRACEDIV_W

Bits 1:3 - Trace Clock Divider value To configure TRACEDIV, you must first disable TRACEDIVEN, then enable it after setting TRACEDIV.

pub fn tracediven(&mut self) -> TRACEDIVEN_W

Bit 28 - Debug Trace Divider control

impl W<u32, Reg<u32, _MISCTRL1>>

pub fn sw_trg(&mut self) -> SW_TRG_W

Bit 0 - Software trigger to TRGMUX. Writing to this bit generates software trigger to peripherals through TRGMUX (Refer to Figure: Trigger interconnectivity).

impl W<u32, Reg<u32, _PCR0>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR1>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR2>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR3>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR4>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR5>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR6>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR7>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR8>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR9>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR10>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR11>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR12>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR13>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR14>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR15>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR16>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR17>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR18>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR19>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR20>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR21>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR22>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR23>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR24>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR25>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR26>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR27>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR28>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR29>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR30>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR31>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _GPCLR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _GPCHR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _ISFR>>

pub fn isf(&mut self) -> ISF_W

Bits 0:31 - Interrupt Status Flag

impl W<u32, Reg<u32, _DFER>>

pub fn dfe(&mut self) -> DFE_W

Bits 0:31 - Digital Filter Enable

impl W<u32, Reg<u32, _DFCR>>

pub fn cs(&mut self) -> CS_W

Bit 0 - Clock Source

impl W<u32, Reg<u32, _DFWR>>

pub fn filt(&mut self) -> FILT_W

Bits 0:4 - Filter Length

impl W<u32, Reg<u32, _PCR0>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR1>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR2>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR3>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR4>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR5>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR6>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR7>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR8>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR9>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR10>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR11>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR12>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR13>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR14>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR15>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR16>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR17>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR18>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR19>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR20>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR21>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR22>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR23>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR24>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR25>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR26>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR27>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR28>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR29>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR30>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR31>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _GPCLR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _GPCHR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _ISFR>>

pub fn isf(&mut self) -> ISF_W

Bits 0:31 - Interrupt Status Flag

impl W<u32, Reg<u32, _DFER>>

pub fn dfe(&mut self) -> DFE_W

Bits 0:31 - Digital Filter Enable

impl W<u32, Reg<u32, _DFCR>>

pub fn cs(&mut self) -> CS_W

Bit 0 - Clock Source

impl W<u32, Reg<u32, _DFWR>>

pub fn filt(&mut self) -> FILT_W

Bits 0:4 - Filter Length

impl W<u32, Reg<u32, _PCR0>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR1>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR2>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR3>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR4>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR5>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR6>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR7>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR8>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR9>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR10>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR11>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR12>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR13>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR14>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR15>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR16>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR17>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR18>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR19>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR20>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR21>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR22>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR23>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR24>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR25>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR26>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR27>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR28>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR29>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR30>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR31>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _GPCLR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _GPCHR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _ISFR>>

pub fn isf(&mut self) -> ISF_W

Bits 0:31 - Interrupt Status Flag

impl W<u32, Reg<u32, _DFER>>

pub fn dfe(&mut self) -> DFE_W

Bits 0:31 - Digital Filter Enable

impl W<u32, Reg<u32, _DFCR>>

pub fn cs(&mut self) -> CS_W

Bit 0 - Clock Source

impl W<u32, Reg<u32, _DFWR>>

pub fn filt(&mut self) -> FILT_W

Bits 0:4 - Filter Length

impl W<u32, Reg<u32, _PCR0>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR1>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR2>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR3>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR4>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR5>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR6>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR7>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR8>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR9>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR10>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR11>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR12>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR13>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR14>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR15>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR16>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR17>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR18>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR19>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR20>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR21>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR22>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR23>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR24>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR25>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR26>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR27>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR28>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR29>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR30>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR31>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _GPCLR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _GPCHR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _ISFR>>

pub fn isf(&mut self) -> ISF_W

Bits 0:31 - Interrupt Status Flag

impl W<u32, Reg<u32, _DFER>>

pub fn dfe(&mut self) -> DFE_W

Bits 0:31 - Digital Filter Enable

impl W<u32, Reg<u32, _DFCR>>

pub fn cs(&mut self) -> CS_W

Bit 0 - Clock Source

impl W<u32, Reg<u32, _DFWR>>

pub fn filt(&mut self) -> FILT_W

Bits 0:4 - Filter Length

impl W<u32, Reg<u32, _PCR0>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR1>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR2>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR3>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR4>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR5>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR6>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR7>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR8>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR9>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR10>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR11>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR12>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR13>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR14>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR15>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR16>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR17>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR18>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR19>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR20>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR21>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR22>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR23>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR24>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR25>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR26>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR27>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR28>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR29>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR30>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR31>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _GPCLR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _GPCHR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _ISFR>>

pub fn isf(&mut self) -> ISF_W

Bits 0:31 - Interrupt Status Flag

impl W<u32, Reg<u32, _DFER>>

pub fn dfe(&mut self) -> DFE_W

Bits 0:31 - Digital Filter Enable

impl W<u32, Reg<u32, _DFCR>>

pub fn cs(&mut self) -> CS_W

Bit 0 - Clock Source

impl W<u32, Reg<u32, _DFWR>>

pub fn filt(&mut self) -> FILT_W

Bits 0:4 - Filter Length

impl W<u32, Reg<u32, _CS>>

pub fn stop(&mut self) -> STOP_W

Bit 0 - Stop Enable

pub fn wait(&mut self) -> WAIT_W

Bit 1 - Wait Enable

pub fn dbg(&mut self) -> DBG_W

Bit 2 - Debug Enable

pub fn tst(&mut self) -> TST_W

Bits 3:4 - Watchdog Test

pub fn update(&mut self) -> UPDATE_W

Bit 5 - Allow updates

pub fn int(&mut self) -> INT_W

Bit 6 - Watchdog Interrupt

pub fn en(&mut self) -> EN_W

Bit 7 - Watchdog Enable

pub fn clk(&mut self) -> CLK_W

Bits 8:9 - Watchdog Clock

pub fn pres(&mut self) -> PRES_W

Bit 12 - Watchdog prescaler

pub fn cmd32en(&mut self) -> CMD32EN_W

Bit 13 - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words

pub fn flg(&mut self) -> FLG_W

Bit 14 - Watchdog Interrupt Flag

pub fn win(&mut self) -> WIN_W

Bit 15 - Watchdog Window

impl W<u32, Reg<u32, _CNT>>

pub fn cntlow(&mut self) -> CNTLOW_W

Bits 0:7 - Low byte of the Watchdog Counter

pub fn cnthigh(&mut self) -> CNTHIGH_W

Bits 8:15 - High byte of the Watchdog Counter

impl W<u32, Reg<u32, _TOVAL>>

pub fn tovallow(&mut self) -> TOVALLOW_W

Bits 0:7 - Low byte of the timeout value

pub fn tovalhigh(&mut self) -> TOVALHIGH_W

Bits 8:15 - High byte of the timeout value

impl W<u32, Reg<u32, _WIN>>

pub fn winlow(&mut self) -> WINLOW_W

Bits 0:7 - Low byte of Watchdog Window

pub fn winhigh(&mut self) -> WINHIGH_W

Bits 8:15 - High byte of Watchdog Window

impl W<u32, Reg<u32, _CTRL>>

pub fn flexen(&mut self) -> FLEXEN_W

Bit 0 - FlexIO Enable

pub fn swrst(&mut self) -> SWRST_W

Bit 1 - Software Reset

pub fn fastacc(&mut self) -> FASTACC_W

Bit 2 - Fast Access

pub fn dbge(&mut self) -> DBGE_W

Bit 30 - Debug Enable

pub fn dozen(&mut self) -> DOZEN_W

Bit 31 - Doze Enable

impl W<u32, Reg<u32, _SHIFTSTAT>>

pub fn ssf(&mut self) -> SSF_W

Bits 0:3 - Shifter Status Flag

impl W<u32, Reg<u32, _SHIFTERR>>

pub fn sef(&mut self) -> SEF_W

Bits 0:3 - Shifter Error Flags

impl W<u32, Reg<u32, _TIMSTAT>>

pub fn tsf(&mut self) -> TSF_W

Bits 0:3 - Timer Status Flags

impl W<u32, Reg<u32, _SHIFTSIEN>>

pub fn ssie(&mut self) -> SSIE_W

Bits 0:3 - Shifter Status Interrupt Enable

impl W<u32, Reg<u32, _SHIFTEIEN>>

pub fn seie(&mut self) -> SEIE_W

Bits 0:3 - Shifter Error Interrupt Enable

impl W<u32, Reg<u32, _TIMIEN>>

pub fn teie(&mut self) -> TEIE_W

Bits 0:3 - Timer Status Interrupt Enable

impl W<u32, Reg<u32, _SHIFTSDEN>>

pub fn ssde(&mut self) -> SSDE_W

Bits 0:3 - Shifter Status DMA Enable

impl W<u32, Reg<u32, _SHIFTCTL0>>

pub fn smod(&mut self) -> SMOD_W

Bits 0:2 - Shifter Mode

pub fn pinpol(&mut self) -> PINPOL_W

Bit 7 - Shifter Pin Polarity

pub fn pinsel(&mut self) -> PINSEL_W

Bits 8:10 - Shifter Pin Select

pub fn pincfg(&mut self) -> PINCFG_W

Bits 16:17 - Shifter Pin Configuration

pub fn timpol(&mut self) -> TIMPOL_W

Bit 23 - Timer Polarity

pub fn timsel(&mut self) -> TIMSEL_W

Bits 24:25 - Timer Select

impl W<u32, Reg<u32, _SHIFTCTL1>>

pub fn smod(&mut self) -> SMOD_W

Bits 0:2 - Shifter Mode

pub fn pinpol(&mut self) -> PINPOL_W

Bit 7 - Shifter Pin Polarity

pub fn pinsel(&mut self) -> PINSEL_W

Bits 8:10 - Shifter Pin Select

pub fn pincfg(&mut self) -> PINCFG_W

Bits 16:17 - Shifter Pin Configuration

pub fn timpol(&mut self) -> TIMPOL_W

Bit 23 - Timer Polarity

pub fn timsel(&mut self) -> TIMSEL_W

Bits 24:25 - Timer Select

impl W<u32, Reg<u32, _SHIFTCTL2>>

pub fn smod(&mut self) -> SMOD_W

Bits 0:2 - Shifter Mode

pub fn pinpol(&mut self) -> PINPOL_W

Bit 7 - Shifter Pin Polarity

pub fn pinsel(&mut self) -> PINSEL_W

Bits 8:10 - Shifter Pin Select

pub fn pincfg(&mut self) -> PINCFG_W

Bits 16:17 - Shifter Pin Configuration

pub fn timpol(&mut self) -> TIMPOL_W

Bit 23 - Timer Polarity

pub fn timsel(&mut self) -> TIMSEL_W

Bits 24:25 - Timer Select

impl W<u32, Reg<u32, _SHIFTCTL3>>

pub fn smod(&mut self) -> SMOD_W

Bits 0:2 - Shifter Mode

pub fn pinpol(&mut self) -> PINPOL_W

Bit 7 - Shifter Pin Polarity

pub fn pinsel(&mut self) -> PINSEL_W

Bits 8:10 - Shifter Pin Select

pub fn pincfg(&mut self) -> PINCFG_W

Bits 16:17 - Shifter Pin Configuration

pub fn timpol(&mut self) -> TIMPOL_W

Bit 23 - Timer Polarity

pub fn timsel(&mut self) -> TIMSEL_W

Bits 24:25 - Timer Select

impl W<u32, Reg<u32, _SHIFTCFG0>>

pub fn sstart(&mut self) -> SSTART_W

Bits 0:1 - Shifter Start bit

pub fn sstop(&mut self) -> SSTOP_W

Bits 4:5 - Shifter Stop bit

pub fn insrc(&mut self) -> INSRC_W

Bit 8 - Input Source

impl W<u32, Reg<u32, _SHIFTCFG1>>

pub fn sstart(&mut self) -> SSTART_W

Bits 0:1 - Shifter Start bit

pub fn sstop(&mut self) -> SSTOP_W

Bits 4:5 - Shifter Stop bit

pub fn insrc(&mut self) -> INSRC_W

Bit 8 - Input Source

impl W<u32, Reg<u32, _SHIFTCFG2>>

pub fn sstart(&mut self) -> SSTART_W

Bits 0:1 - Shifter Start bit

pub fn sstop(&mut self) -> SSTOP_W

Bits 4:5 - Shifter Stop bit

pub fn insrc(&mut self) -> INSRC_W

Bit 8 - Input Source

impl W<u32, Reg<u32, _SHIFTCFG3>>

pub fn sstart(&mut self) -> SSTART_W

Bits 0:1 - Shifter Start bit

pub fn sstop(&mut self) -> SSTOP_W

Bits 4:5 - Shifter Stop bit

pub fn insrc(&mut self) -> INSRC_W

Bit 8 - Input Source

impl W<u32, Reg<u32, _SHIFTBUF0>>

pub fn shiftbuf(&mut self) -> SHIFTBUF_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _SHIFTBUF1>>

pub fn shiftbuf(&mut self) -> SHIFTBUF_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _SHIFTBUF2>>

pub fn shiftbuf(&mut self) -> SHIFTBUF_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _SHIFTBUF3>>

pub fn shiftbuf(&mut self) -> SHIFTBUF_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _SHIFTBUFBIS0>>

pub fn shiftbufbis(&mut self) -> SHIFTBUFBIS_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _SHIFTBUFBIS1>>

pub fn shiftbufbis(&mut self) -> SHIFTBUFBIS_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _SHIFTBUFBIS2>>

pub fn shiftbufbis(&mut self) -> SHIFTBUFBIS_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _SHIFTBUFBIS3>>

pub fn shiftbufbis(&mut self) -> SHIFTBUFBIS_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _SHIFTBUFBYS0>>

pub fn shiftbufbys(&mut self) -> SHIFTBUFBYS_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _SHIFTBUFBYS1>>

pub fn shiftbufbys(&mut self) -> SHIFTBUFBYS_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _SHIFTBUFBYS2>>

pub fn shiftbufbys(&mut self) -> SHIFTBUFBYS_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _SHIFTBUFBYS3>>

pub fn shiftbufbys(&mut self) -> SHIFTBUFBYS_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _SHIFTBUFBBS0>>

pub fn shiftbufbbs(&mut self) -> SHIFTBUFBBS_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _SHIFTBUFBBS1>>

pub fn shiftbufbbs(&mut self) -> SHIFTBUFBBS_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _SHIFTBUFBBS2>>

pub fn shiftbufbbs(&mut self) -> SHIFTBUFBBS_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _SHIFTBUFBBS3>>

pub fn shiftbufbbs(&mut self) -> SHIFTBUFBBS_W

Bits 0:31 - Shift Buffer

impl W<u32, Reg<u32, _TIMCTL0>>

pub fn timod(&mut self) -> TIMOD_W

Bits 0:1 - Timer Mode

pub fn pinpol(&mut self) -> PINPOL_W

Bit 7 - Timer Pin Polarity

pub fn pinsel(&mut self) -> PINSEL_W

Bits 8:10 - Timer Pin Select

pub fn pincfg(&mut self) -> PINCFG_W

Bits 16:17 - Timer Pin Configuration

pub fn trgsrc(&mut self) -> TRGSRC_W

Bit 22 - Trigger Source

pub fn trgpol(&mut self) -> TRGPOL_W

Bit 23 - Trigger Polarity

pub fn trgsel(&mut self) -> TRGSEL_W

Bits 24:27 - Trigger Select

impl W<u32, Reg<u32, _TIMCTL1>>

pub fn timod(&mut self) -> TIMOD_W

Bits 0:1 - Timer Mode

pub fn pinpol(&mut self) -> PINPOL_W

Bit 7 - Timer Pin Polarity

pub fn pinsel(&mut self) -> PINSEL_W

Bits 8:10 - Timer Pin Select

pub fn pincfg(&mut self) -> PINCFG_W

Bits 16:17 - Timer Pin Configuration

pub fn trgsrc(&mut self) -> TRGSRC_W

Bit 22 - Trigger Source

pub fn trgpol(&mut self) -> TRGPOL_W

Bit 23 - Trigger Polarity

pub fn trgsel(&mut self) -> TRGSEL_W

Bits 24:27 - Trigger Select

impl W<u32, Reg<u32, _TIMCTL2>>

pub fn timod(&mut self) -> TIMOD_W

Bits 0:1 - Timer Mode

pub fn pinpol(&mut self) -> PINPOL_W

Bit 7 - Timer Pin Polarity

pub fn pinsel(&mut self) -> PINSEL_W

Bits 8:10 - Timer Pin Select

pub fn pincfg(&mut self) -> PINCFG_W

Bits 16:17 - Timer Pin Configuration

pub fn trgsrc(&mut self) -> TRGSRC_W

Bit 22 - Trigger Source

pub fn trgpol(&mut self) -> TRGPOL_W

Bit 23 - Trigger Polarity

pub fn trgsel(&mut self) -> TRGSEL_W

Bits 24:27 - Trigger Select

impl W<u32, Reg<u32, _TIMCTL3>>

pub fn timod(&mut self) -> TIMOD_W

Bits 0:1 - Timer Mode

pub fn pinpol(&mut self) -> PINPOL_W

Bit 7 - Timer Pin Polarity

pub fn pinsel(&mut self) -> PINSEL_W

Bits 8:10 - Timer Pin Select

pub fn pincfg(&mut self) -> PINCFG_W

Bits 16:17 - Timer Pin Configuration

pub fn trgsrc(&mut self) -> TRGSRC_W

Bit 22 - Trigger Source

pub fn trgpol(&mut self) -> TRGPOL_W

Bit 23 - Trigger Polarity

pub fn trgsel(&mut self) -> TRGSEL_W

Bits 24:27 - Trigger Select

impl W<u32, Reg<u32, _TIMCFG0>>

pub fn tstart(&mut self) -> TSTART_W

Bit 1 - Timer Start Bit

pub fn tstop(&mut self) -> TSTOP_W

Bits 4:5 - Timer Stop Bit

pub fn timena(&mut self) -> TIMENA_W

Bits 8:10 - Timer Enable

pub fn timdis(&mut self) -> TIMDIS_W

Bits 12:14 - Timer Disable

pub fn timrst(&mut self) -> TIMRST_W

Bits 16:18 - Timer Reset

pub fn timdec(&mut self) -> TIMDEC_W

Bits 20:21 - Timer Decrement

pub fn timout(&mut self) -> TIMOUT_W

Bits 24:25 - Timer Output

impl W<u32, Reg<u32, _TIMCFG1>>

pub fn tstart(&mut self) -> TSTART_W

Bit 1 - Timer Start Bit

pub fn tstop(&mut self) -> TSTOP_W

Bits 4:5 - Timer Stop Bit

pub fn timena(&mut self) -> TIMENA_W

Bits 8:10 - Timer Enable

pub fn timdis(&mut self) -> TIMDIS_W

Bits 12:14 - Timer Disable

pub fn timrst(&mut self) -> TIMRST_W

Bits 16:18 - Timer Reset

pub fn timdec(&mut self) -> TIMDEC_W

Bits 20:21 - Timer Decrement

pub fn timout(&mut self) -> TIMOUT_W

Bits 24:25 - Timer Output

impl W<u32, Reg<u32, _TIMCFG2>>

pub fn tstart(&mut self) -> TSTART_W

Bit 1 - Timer Start Bit

pub fn tstop(&mut self) -> TSTOP_W

Bits 4:5 - Timer Stop Bit

pub fn timena(&mut self) -> TIMENA_W

Bits 8:10 - Timer Enable

pub fn timdis(&mut self) -> TIMDIS_W

Bits 12:14 - Timer Disable

pub fn timrst(&mut self) -> TIMRST_W

Bits 16:18 - Timer Reset

pub fn timdec(&mut self) -> TIMDEC_W

Bits 20:21 - Timer Decrement

pub fn timout(&mut self) -> TIMOUT_W

Bits 24:25 - Timer Output

impl W<u32, Reg<u32, _TIMCFG3>>

pub fn tstart(&mut self) -> TSTART_W

Bit 1 - Timer Start Bit

pub fn tstop(&mut self) -> TSTOP_W

Bits 4:5 - Timer Stop Bit

pub fn timena(&mut self) -> TIMENA_W

Bits 8:10 - Timer Enable

pub fn timdis(&mut self) -> TIMDIS_W

Bits 12:14 - Timer Disable

pub fn timrst(&mut self) -> TIMRST_W

Bits 16:18 - Timer Reset

pub fn timdec(&mut self) -> TIMDEC_W

Bits 20:21 - Timer Decrement

pub fn timout(&mut self) -> TIMOUT_W

Bits 24:25 - Timer Output

impl W<u32, Reg<u32, _TIMCMP0>>

pub fn cmp(&mut self) -> CMP_W

Bits 0:15 - Timer Compare Value

impl W<u32, Reg<u32, _TIMCMP1>>

pub fn cmp(&mut self) -> CMP_W

Bits 0:15 - Timer Compare Value

impl W<u32, Reg<u32, _TIMCMP2>>

pub fn cmp(&mut self) -> CMP_W

Bits 0:15 - Timer Compare Value

impl W<u32, Reg<u32, _TIMCMP3>>

pub fn cmp(&mut self) -> CMP_W

Bits 0:15 - Timer Compare Value

impl W<u8, Reg<u8, _CTRL>>

pub fn ewmen(&mut self) -> EWMEN_W

Bit 0 - EWM enable.

pub fn assin(&mut self) -> ASSIN_W

Bit 1 - EWM_in's Assertion State Select.

pub fn inen(&mut self) -> INEN_W

Bit 2 - Input Enable.

pub fn inten(&mut self) -> INTEN_W

Bit 3 - Interrupt Enable.

impl W<u8, Reg<u8, _SERV>>

pub fn service(&mut self) -> SERVICE_W

Bits 0:7 - SERVICE

impl W<u8, Reg<u8, _CMPL>>

pub fn comparel(&mut self) -> COMPAREL_W

Bits 0:7 - COMPAREL

impl W<u8, Reg<u8, _CMPH>>

pub fn compareh(&mut self) -> COMPAREH_W

Bits 0:7 - COMPAREH

impl W<u8, Reg<u8, _CLKPRESCALER>>

pub fn clk_div(&mut self) -> CLK_DIV_W

Bits 0:7 - CLK_DIV

impl W<u32, Reg<u32, _TRGMUX_DMAMUX0>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn sel1(&mut self) -> SEL1_W

Bits 8:13 - Trigger MUX Input 1 Source Select

pub fn sel2(&mut self) -> SEL2_W

Bits 16:21 - Trigger MUX Input 2 Source Select

pub fn sel3(&mut self) -> SEL3_W

Bits 24:29 - Trigger MUX Input 3 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_EXTOUT0>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn sel1(&mut self) -> SEL1_W

Bits 8:13 - Trigger MUX Input 1 Source Select

pub fn sel2(&mut self) -> SEL2_W

Bits 16:21 - Trigger MUX Input 2 Source Select

pub fn sel3(&mut self) -> SEL3_W

Bits 24:29 - Trigger MUX Input 3 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_EXTOUT1>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn sel1(&mut self) -> SEL1_W

Bits 8:13 - Trigger MUX Input 1 Source Select

pub fn sel2(&mut self) -> SEL2_W

Bits 16:21 - Trigger MUX Input 2 Source Select

pub fn sel3(&mut self) -> SEL3_W

Bits 24:29 - Trigger MUX Input 3 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_ADC0>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn sel1(&mut self) -> SEL1_W

Bits 8:13 - Trigger MUX Input 1 Source Select

pub fn sel2(&mut self) -> SEL2_W

Bits 16:21 - Trigger MUX Input 2 Source Select

pub fn sel3(&mut self) -> SEL3_W

Bits 24:29 - Trigger MUX Input 3 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_ADC1>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn sel1(&mut self) -> SEL1_W

Bits 8:13 - Trigger MUX Input 1 Source Select

pub fn sel2(&mut self) -> SEL2_W

Bits 16:21 - Trigger MUX Input 2 Source Select

pub fn sel3(&mut self) -> SEL3_W

Bits 24:29 - Trigger MUX Input 3 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_CMP0>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_FTM0>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn sel1(&mut self) -> SEL1_W

Bits 8:13 - Trigger MUX Input 1 Source Select

pub fn sel2(&mut self) -> SEL2_W

Bits 16:21 - Trigger MUX Input 2 Source Select

pub fn sel3(&mut self) -> SEL3_W

Bits 24:29 - Trigger MUX Input 3 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_FTM1>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn sel1(&mut self) -> SEL1_W

Bits 8:13 - Trigger MUX Input 1 Source Select

pub fn sel2(&mut self) -> SEL2_W

Bits 16:21 - Trigger MUX Input 2 Source Select

pub fn sel3(&mut self) -> SEL3_W

Bits 24:29 - Trigger MUX Input 3 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_FTM2>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn sel1(&mut self) -> SEL1_W

Bits 8:13 - Trigger MUX Input 1 Source Select

pub fn sel2(&mut self) -> SEL2_W

Bits 16:21 - Trigger MUX Input 2 Source Select

pub fn sel3(&mut self) -> SEL3_W

Bits 24:29 - Trigger MUX Input 3 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_FTM3>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn sel1(&mut self) -> SEL1_W

Bits 8:13 - Trigger MUX Input 1 Source Select

pub fn sel2(&mut self) -> SEL2_W

Bits 16:21 - Trigger MUX Input 2 Source Select

pub fn sel3(&mut self) -> SEL3_W

Bits 24:29 - Trigger MUX Input 3 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_PDB0>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_PDB1>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_FLEXIO>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn sel1(&mut self) -> SEL1_W

Bits 8:13 - Trigger MUX Input 1 Source Select

pub fn sel2(&mut self) -> SEL2_W

Bits 16:21 - Trigger MUX Input 2 Source Select

pub fn sel3(&mut self) -> SEL3_W

Bits 24:29 - Trigger MUX Input 3 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_LPIT0>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn sel1(&mut self) -> SEL1_W

Bits 8:13 - Trigger MUX Input 1 Source Select

pub fn sel2(&mut self) -> SEL2_W

Bits 16:21 - Trigger MUX Input 2 Source Select

pub fn sel3(&mut self) -> SEL3_W

Bits 24:29 - Trigger MUX Input 3 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_LPUART0>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_LPUART1>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_LPI2C0>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_LPSPI0>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_LPSPI1>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _TRGMUX_LPTMR0>>

pub fn sel0(&mut self) -> SEL0_W

Bits 0:5 - Trigger MUX Input 0 Source Select

pub fn lk(&mut self) -> LK_W

Bit 31 - TRGMUX register lock.

impl W<u32, Reg<u32, _RCCR>>

pub fn divslow(&mut self) -> DIVSLOW_W

Bits 0:3 - Slow Clock Divide Ratio

pub fn divbus(&mut self) -> DIVBUS_W

Bits 4:7 - Bus Clock Divide Ratio

pub fn divcore(&mut self) -> DIVCORE_W

Bits 16:19 - Core Clock Divide Ratio

pub fn scs(&mut self) -> SCS_W

Bits 24:27 - System Clock Source

impl W<u32, Reg<u32, _VCCR>>

pub fn divslow(&mut self) -> DIVSLOW_W

Bits 0:3 - Slow Clock Divide Ratio

pub fn divbus(&mut self) -> DIVBUS_W

Bits 4:7 - Bus Clock Divide Ratio

pub fn divcore(&mut self) -> DIVCORE_W

Bits 16:19 - Core Clock Divide Ratio

pub fn scs(&mut self) -> SCS_W

Bits 24:27 - System Clock Source

impl W<u32, Reg<u32, _HCCR>>

pub fn divslow(&mut self) -> DIVSLOW_W

Bits 0:3 - Slow Clock Divide Ratio

pub fn divbus(&mut self) -> DIVBUS_W

Bits 4:7 - Bus Clock Divide Ratio

pub fn divcore(&mut self) -> DIVCORE_W

Bits 16:19 - Core Clock Divide Ratio

pub fn scs(&mut self) -> SCS_W

Bits 24:27 - System Clock Source

impl W<u32, Reg<u32, _CLKOUTCNFG>>

pub fn clkoutsel(&mut self) -> CLKOUTSEL_W

Bits 24:27 - SCG Clkout Select

impl W<u32, Reg<u32, _SOSCCSR>>

pub fn soscen(&mut self) -> SOSCEN_W

Bit 0 - System OSC Enable

pub fn sosccm(&mut self) -> SOSCCM_W

Bit 16 - System OSC Clock Monitor

pub fn sosccmre(&mut self) -> SOSCCMRE_W

Bit 17 - System OSC Clock Monitor Reset Enable

pub fn lk(&mut self) -> LK_W

Bit 23 - Lock Register

pub fn soscerr(&mut self) -> SOSCERR_W

Bit 26 - System OSC Clock Error

impl W<u32, Reg<u32, _SOSCDIV>>

pub fn soscdiv1(&mut self) -> SOSCDIV1_W

Bits 0:2 - System OSC Clock Divide 1

pub fn soscdiv2(&mut self) -> SOSCDIV2_W

Bits 8:10 - System OSC Clock Divide 2

impl W<u32, Reg<u32, _SOSCCFG>>

pub fn erefs(&mut self) -> EREFS_W

Bit 2 - External Reference Select

pub fn hgo(&mut self) -> HGO_W

Bit 3 - High Gain Oscillator Select

pub fn range(&mut self) -> RANGE_W

Bits 4:5 - System OSC Range Select

impl W<u32, Reg<u32, _SIRCCSR>>

pub fn sircen(&mut self) -> SIRCEN_W

Bit 0 - Slow IRC Enable

pub fn sircsten(&mut self) -> SIRCSTEN_W

Bit 1 - Slow IRC Stop Enable

pub fn sirclpen(&mut self) -> SIRCLPEN_W

Bit 2 - Slow IRC Low Power Enable

pub fn lk(&mut self) -> LK_W

Bit 23 - Lock Register

impl W<u32, Reg<u32, _SIRCDIV>>

pub fn sircdiv1(&mut self) -> SIRCDIV1_W

Bits 0:2 - Slow IRC Clock Divide 1

pub fn sircdiv2(&mut self) -> SIRCDIV2_W

Bits 8:10 - Slow IRC Clock Divide 2

impl W<u32, Reg<u32, _SIRCCFG>>

pub fn range(&mut self) -> RANGE_W

Bit 0 - Frequency Range

impl W<u32, Reg<u32, _FIRCCSR>>

pub fn fircen(&mut self) -> FIRCEN_W

Bit 0 - Fast IRC Enable

pub fn fircregoff(&mut self) -> FIRCREGOFF_W

Bit 3 - Fast IRC Regulator Enable

pub fn lk(&mut self) -> LK_W

Bit 23 - Lock Register

pub fn fircerr(&mut self) -> FIRCERR_W

Bit 26 - Fast IRC Clock Error

impl W<u32, Reg<u32, _FIRCDIV>>

pub fn fircdiv1(&mut self) -> FIRCDIV1_W

Bits 0:2 - Fast IRC Clock Divide 1

pub fn fircdiv2(&mut self) -> FIRCDIV2_W

Bits 8:10 - Fast IRC Clock Divide 2

impl W<u32, Reg<u32, _FIRCCFG>>

pub fn range(&mut self) -> RANGE_W

Bits 0:1 - Frequency Range

impl W<u32, Reg<u32, _SPLLCSR>>

pub fn spllen(&mut self) -> SPLLEN_W

Bit 0 - System PLL Enable

pub fn spllcm(&mut self) -> SPLLCM_W

Bit 16 - System PLL Clock Monitor

pub fn spllcmre(&mut self) -> SPLLCMRE_W

Bit 17 - System PLL Clock Monitor Reset Enable

pub fn lk(&mut self) -> LK_W

Bit 23 - Lock Register

pub fn spllerr(&mut self) -> SPLLERR_W

Bit 26 - System PLL Clock Error

impl W<u32, Reg<u32, _SPLLDIV>>

pub fn splldiv1(&mut self) -> SPLLDIV1_W

Bits 0:2 - System PLL Clock Divide 1

pub fn splldiv2(&mut self) -> SPLLDIV2_W

Bits 8:10 - System PLL Clock Divide 2

impl W<u32, Reg<u32, _SPLLCFG>>

pub fn prediv(&mut self) -> PREDIV_W

Bits 8:10 - PLL Reference Clock Divider

pub fn mult(&mut self) -> MULT_W

Bits 16:20 - System PLL Multiplier

impl W<u32, Reg<u32, _PCC_FTFC>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_DMAMUX>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_FLEXCAN0>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_FLEXCAN1>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_FTM3>>

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_ADC1>>

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_FLEXCAN2>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_LPSPI0>>

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_LPSPI1>>

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_LPSPI2>>

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_PDB1>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_CRC>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_PDB0>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_LPIT>>

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_FTM0>>

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_FTM1>>

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_FTM2>>

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_ADC0>>

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_RTC>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_LPTMR0>>

pub fn pcd(&mut self) -> PCD_W

Bits 0:2 - Peripheral Clock Divider Select

pub fn frac(&mut self) -> FRAC_W

Bit 3 - Peripheral Clock Divider Fraction

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_PORTA>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_PORTB>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_PORTC>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_PORTD>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_PORTE>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_FLEXIO>>

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_EWM>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_LPI2C0>>

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_LPUART0>>

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_LPUART1>>

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_LPUART2>>

pub fn pcs(&mut self) -> PCS_W

Bits 24:26 - Peripheral Clock Source Select

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _PCC_CMP0>>

pub fn cgc(&mut self) -> CGC_W

Bit 30 - Clock Gate Control

impl W<u32, Reg<u32, _MCR>>

pub fn men(&mut self) -> MEN_W

Bit 0 - Master Enable

pub fn rst(&mut self) -> RST_W

Bit 1 - Software Reset

pub fn dozen(&mut self) -> DOZEN_W

Bit 2 - Doze mode enable

pub fn dbgen(&mut self) -> DBGEN_W

Bit 3 - Debug Enable

pub fn rtf(&mut self) -> RTF_W

Bit 8 - Reset Transmit FIFO

pub fn rrf(&mut self) -> RRF_W

Bit 9 - Reset Receive FIFO

impl W<u32, Reg<u32, _MSR>>

pub fn epf(&mut self) -> EPF_W

Bit 8 - End Packet Flag

pub fn sdf(&mut self) -> SDF_W

Bit 9 - STOP Detect Flag

pub fn ndf(&mut self) -> NDF_W

Bit 10 - NACK Detect Flag

pub fn alf(&mut self) -> ALF_W

Bit 11 - Arbitration Lost Flag

pub fn fef(&mut self) -> FEF_W

Bit 12 - FIFO Error Flag

pub fn pltf(&mut self) -> PLTF_W

Bit 13 - Pin Low Timeout Flag

pub fn dmf(&mut self) -> DMF_W

Bit 14 - Data Match Flag

impl W<u32, Reg<u32, _MIER>>

pub fn tdie(&mut self) -> TDIE_W

Bit 0 - Transmit Data Interrupt Enable

pub fn rdie(&mut self) -> RDIE_W

Bit 1 - Receive Data Interrupt Enable

pub fn epie(&mut self) -> EPIE_W

Bit 8 - End Packet Interrupt Enable

pub fn sdie(&mut self) -> SDIE_W

Bit 9 - STOP Detect Interrupt Enable

pub fn ndie(&mut self) -> NDIE_W

Bit 10 - NACK Detect Interrupt Enable

pub fn alie(&mut self) -> ALIE_W

Bit 11 - Arbitration Lost Interrupt Enable

pub fn feie(&mut self) -> FEIE_W

Bit 12 - FIFO Error Interrupt Enable

pub fn pltie(&mut self) -> PLTIE_W

Bit 13 - Pin Low Timeout Interrupt Enable

pub fn dmie(&mut self) -> DMIE_W

Bit 14 - Data Match Interrupt Enable

impl W<u32, Reg<u32, _MDER>>

pub fn tdde(&mut self) -> TDDE_W

Bit 0 - Transmit Data DMA Enable

pub fn rdde(&mut self) -> RDDE_W

Bit 1 - Receive Data DMA Enable

impl W<u32, Reg<u32, _MCFGR0>>

pub fn hren(&mut self) -> HREN_W

Bit 0 - Host Request Enable

pub fn hrpol(&mut self) -> HRPOL_W

Bit 1 - Host Request Polarity

pub fn hrsel(&mut self) -> HRSEL_W

Bit 2 - Host Request Select

pub fn cirfifo(&mut self) -> CIRFIFO_W

Bit 8 - Circular FIFO Enable

pub fn rdmo(&mut self) -> RDMO_W

Bit 9 - Receive Data Match Only

impl W<u32, Reg<u32, _MCFGR1>>

pub fn prescale(&mut self) -> PRESCALE_W

Bits 0:2 - Prescaler

pub fn autostop(&mut self) -> AUTOSTOP_W

Bit 8 - Automatic STOP Generation

pub fn ignack(&mut self) -> IGNACK_W

Bit 9 - IGNACK

pub fn timecfg(&mut self) -> TIMECFG_W

Bit 10 - Timeout Configuration

pub fn matcfg(&mut self) -> MATCFG_W

Bits 16:18 - Match Configuration

pub fn pincfg(&mut self) -> PINCFG_W

Bits 24:26 - Pin Configuration

impl W<u32, Reg<u32, _MCFGR2>>

pub fn busidle(&mut self) -> BUSIDLE_W

Bits 0:11 - Bus Idle Timeout

pub fn filtscl(&mut self) -> FILTSCL_W

Bits 16:19 - Glitch Filter SCL

pub fn filtsda(&mut self) -> FILTSDA_W

Bits 24:27 - Glitch Filter SDA

impl W<u32, Reg<u32, _MCFGR3>>

pub fn pinlow(&mut self) -> PINLOW_W

Bits 8:19 - Pin Low Timeout

impl W<u32, Reg<u32, _MDMR>>

pub fn match0(&mut self) -> MATCH0_W

Bits 0:7 - Match 0 Value

pub fn match1(&mut self) -> MATCH1_W

Bits 16:23 - Match 1 Value

impl W<u32, Reg<u32, _MCCR0>>

pub fn clklo(&mut self) -> CLKLO_W

Bits 0:5 - Clock Low Period

pub fn clkhi(&mut self) -> CLKHI_W

Bits 8:13 - Clock High Period

pub fn sethold(&mut self) -> SETHOLD_W

Bits 16:21 - Setup Hold Delay

pub fn datavd(&mut self) -> DATAVD_W

Bits 24:29 - Data Valid Delay

impl W<u32, Reg<u32, _MCCR1>>

pub fn clklo(&mut self) -> CLKLO_W

Bits 0:5 - Clock Low Period

pub fn clkhi(&mut self) -> CLKHI_W

Bits 8:13 - Clock High Period

pub fn sethold(&mut self) -> SETHOLD_W

Bits 16:21 - Setup Hold Delay

pub fn datavd(&mut self) -> DATAVD_W

Bits 24:29 - Data Valid Delay

impl W<u32, Reg<u32, _MFCR>>

pub fn txwater(&mut self) -> TXWATER_W

Bits 0:1 - Transmit FIFO Watermark

pub fn rxwater(&mut self) -> RXWATER_W

Bits 16:17 - Receive FIFO Watermark

impl W<u32, Reg<u32, _MTDR>>

pub fn data(&mut self) -> DATA_W

Bits 0:7 - Transmit Data

pub fn cmd(&mut self) -> CMD_W

Bits 8:10 - Command Data

impl W<u32, Reg<u32, _SCR>>

pub fn sen(&mut self) -> SEN_W

Bit 0 - Slave Enable

pub fn rst(&mut self) -> RST_W

Bit 1 - Software Reset

pub fn filten(&mut self) -> FILTEN_W

Bit 4 - Filter Enable

pub fn filtdz(&mut self) -> FILTDZ_W

Bit 5 - Filter Doze Enable

impl W<u32, Reg<u32, _SSR>>

pub fn rsf(&mut self) -> RSF_W

Bit 8 - Repeated Start Flag

pub fn sdf(&mut self) -> SDF_W

Bit 9 - STOP Detect Flag

pub fn bef(&mut self) -> BEF_W

Bit 10 - Bit Error Flag

pub fn fef(&mut self) -> FEF_W

Bit 11 - FIFO Error Flag

impl W<u32, Reg<u32, _SIER>>

pub fn tdie(&mut self) -> TDIE_W

Bit 0 - Transmit Data Interrupt Enable

pub fn rdie(&mut self) -> RDIE_W

Bit 1 - Receive Data Interrupt Enable

pub fn avie(&mut self) -> AVIE_W

Bit 2 - Address Valid Interrupt Enable

pub fn taie(&mut self) -> TAIE_W

Bit 3 - Transmit ACK Interrupt Enable

pub fn rsie(&mut self) -> RSIE_W

Bit 8 - Repeated Start Interrupt Enable

pub fn sdie(&mut self) -> SDIE_W

Bit 9 - STOP Detect Interrupt Enable

pub fn beie(&mut self) -> BEIE_W

Bit 10 - Bit Error Interrupt Enable

pub fn feie(&mut self) -> FEIE_W

Bit 11 - FIFO Error Interrupt Enable

pub fn am0ie(&mut self) -> AM0IE_W

Bit 12 - Address Match 0 Interrupt Enable

pub fn am1f(&mut self) -> AM1F_W

Bit 13 - Address Match 1 Interrupt Enable

pub fn gcie(&mut self) -> GCIE_W

Bit 14 - General Call Interrupt Enable

pub fn sarie(&mut self) -> SARIE_W

Bit 15 - SMBus Alert Response Interrupt Enable

impl W<u32, Reg<u32, _SDER>>

pub fn tdde(&mut self) -> TDDE_W

Bit 0 - Transmit Data DMA Enable

pub fn rdde(&mut self) -> RDDE_W

Bit 1 - Receive Data DMA Enable

pub fn avde(&mut self) -> AVDE_W

Bit 2 - Address Valid DMA Enable

impl W<u32, Reg<u32, _SCFGR1>>

pub fn adrstall(&mut self) -> ADRSTALL_W

Bit 0 - Address SCL Stall

pub fn rxstall(&mut self) -> RXSTALL_W

Bit 1 - RX SCL Stall

pub fn txdstall(&mut self) -> TXDSTALL_W

Bit 2 - TX Data SCL Stall

pub fn ackstall(&mut self) -> ACKSTALL_W

Bit 3 - ACK SCL Stall

pub fn gcen(&mut self) -> GCEN_W

Bit 8 - General Call Enable

pub fn saen(&mut self) -> SAEN_W

Bit 9 - SMBus Alert Enable

pub fn txcfg(&mut self) -> TXCFG_W

Bit 10 - Transmit Flag Configuration

pub fn rxcfg(&mut self) -> RXCFG_W

Bit 11 - Receive Data Configuration

pub fn ignack(&mut self) -> IGNACK_W

Bit 12 - Ignore NACK

pub fn hsmen(&mut self) -> HSMEN_W

Bit 13 - High Speed Mode Enable

pub fn addrcfg(&mut self) -> ADDRCFG_W

Bits 16:18 - Address Configuration

impl W<u32, Reg<u32, _SCFGR2>>

pub fn clkhold(&mut self) -> CLKHOLD_W

Bits 0:3 - Clock Hold Time

pub fn datavd(&mut self) -> DATAVD_W

Bits 8:13 - Data Valid Delay

pub fn filtscl(&mut self) -> FILTSCL_W

Bits 16:19 - Glitch Filter SCL

pub fn filtsda(&mut self) -> FILTSDA_W

Bits 24:27 - Glitch Filter SDA

impl W<u32, Reg<u32, _SAMR>>

pub fn addr0(&mut self) -> ADDR0_W

Bits 1:10 - Address 0 Value

pub fn addr1(&mut self) -> ADDR1_W

Bits 17:26 - Address 1 Value

impl W<u32, Reg<u32, _STAR>>

pub fn txnack(&mut self) -> TXNACK_W

Bit 0 - Transmit NACK

impl W<u32, Reg<u32, _STDR>>

pub fn data(&mut self) -> DATA_W

Bits 0:7 - Transmit Data

impl W<u32, Reg<u32, _GLOBAL>>

pub fn rst(&mut self) -> RST_W

Bit 1 - Software Reset

impl W<u32, Reg<u32, _PINCFG>>

pub fn trgsel(&mut self) -> TRGSEL_W

Bits 0:1 - Trigger Select

impl W<u32, Reg<u32, _BAUD>>

pub fn sbr(&mut self) -> SBR_W

Bits 0:12 - Baud Rate Modulo Divisor.

pub fn sbns(&mut self) -> SBNS_W

Bit 13 - Stop Bit Number Select

pub fn rxedgie(&mut self) -> RXEDGIE_W

Bit 14 - RX Input Active Edge Interrupt Enable

pub fn lbkdie(&mut self) -> LBKDIE_W

Bit 15 - LIN Break Detect Interrupt Enable

pub fn resyncdis(&mut self) -> RESYNCDIS_W

Bit 16 - Resynchronization Disable

pub fn bothedge(&mut self) -> BOTHEDGE_W

Bit 17 - Both Edge Sampling

pub fn matcfg(&mut self) -> MATCFG_W

Bits 18:19 - Match Configuration

pub fn ridmae(&mut self) -> RIDMAE_W

Bit 20 - Receiver Idle DMA Enable

pub fn rdmae(&mut self) -> RDMAE_W

Bit 21 - Receiver Full DMA Enable

pub fn tdmae(&mut self) -> TDMAE_W

Bit 23 - Transmitter DMA Enable

pub fn osr(&mut self) -> OSR_W

Bits 24:28 - Oversampling Ratio

pub fn m10(&mut self) -> M10_W

Bit 29 - 10-bit Mode select

pub fn maen2(&mut self) -> MAEN2_W

Bit 30 - Match Address Mode Enable 2

pub fn maen1(&mut self) -> MAEN1_W

Bit 31 - Match Address Mode Enable 1

impl W<u32, Reg<u32, _STAT>>

pub fn ma2f(&mut self) -> MA2F_W

Bit 14 - Match 2 Flag

pub fn ma1f(&mut self) -> MA1F_W

Bit 15 - Match 1 Flag

pub fn pf(&mut self) -> PF_W

Bit 16 - Parity Error Flag

pub fn fe(&mut self) -> FE_W

Bit 17 - Framing Error Flag

pub fn nf(&mut self) -> NF_W

Bit 18 - Noise Flag

pub fn or(&mut self) -> OR_W

Bit 19 - Receiver Overrun Flag

pub fn idle(&mut self) -> IDLE_W

Bit 20 - Idle Line Flag

pub fn lbkde(&mut self) -> LBKDE_W

Bit 25 - LIN Break Detection Enable

pub fn brk13(&mut self) -> BRK13_W

Bit 26 - Break Character Generation Length

pub fn rwuid(&mut self) -> RWUID_W

Bit 27 - Receive Wake Up Idle Detect

pub fn rxinv(&mut self) -> RXINV_W

Bit 28 - Receive Data Inversion

pub fn msbf(&mut self) -> MSBF_W

Bit 29 - MSB First

pub fn rxedgif(&mut self) -> RXEDGIF_W

Bit 30 - RXD Pin Active Edge Interrupt Flag

pub fn lbkdif(&mut self) -> LBKDIF_W

Bit 31 - LIN Break Detect Interrupt Flag

impl W<u32, Reg<u32, _CTRL>>

pub fn pt(&mut self) -> PT_W

Bit 0 - Parity Type

pub fn pe(&mut self) -> PE_W

Bit 1 - Parity Enable

pub fn ilt(&mut self) -> ILT_W

Bit 2 - Idle Line Type Select

pub fn wake(&mut self) -> WAKE_W

Bit 3 - Receiver Wakeup Method Select

pub fn m(&mut self) -> M_W

Bit 4 - 9-Bit or 8-Bit Mode Select

pub fn rsrc(&mut self) -> RSRC_W

Bit 5 - Receiver Source Select

pub fn dozeen(&mut self) -> DOZEEN_W

Bit 6 - Doze Enable

pub fn loops(&mut self) -> LOOPS_W

Bit 7 - Loop Mode Select

pub fn idlecfg(&mut self) -> IDLECFG_W

Bits 8:10 - Idle Configuration

pub fn m7(&mut self) -> M7_W

Bit 11 - 7-Bit Mode Select

pub fn ma2ie(&mut self) -> MA2IE_W

Bit 14 - Match 2 Interrupt Enable

pub fn ma1ie(&mut self) -> MA1IE_W

Bit 15 - Match 1 Interrupt Enable

pub fn sbk(&mut self) -> SBK_W

Bit 16 - Send Break

pub fn rwu(&mut self) -> RWU_W

Bit 17 - Receiver Wakeup Control

pub fn re(&mut self) -> RE_W

Bit 18 - Receiver Enable

pub fn te(&mut self) -> TE_W

Bit 19 - Transmitter Enable

pub fn ilie(&mut self) -> ILIE_W

Bit 20 - Idle Line Interrupt Enable

pub fn rie(&mut self) -> RIE_W

Bit 21 - Receiver Interrupt Enable

pub fn tcie(&mut self) -> TCIE_W

Bit 22 - Transmission Complete Interrupt Enable for

pub fn tie(&mut self) -> TIE_W

Bit 23 - Transmit Interrupt Enable

pub fn peie(&mut self) -> PEIE_W

Bit 24 - Parity Error Interrupt Enable

pub fn feie(&mut self) -> FEIE_W

Bit 25 - Framing Error Interrupt Enable

pub fn neie(&mut self) -> NEIE_W

Bit 26 - Noise Error Interrupt Enable

pub fn orie(&mut self) -> ORIE_W

Bit 27 - Overrun Interrupt Enable

pub fn txinv(&mut self) -> TXINV_W

Bit 28 - Transmit Data Inversion

pub fn txdir(&mut self) -> TXDIR_W

Bit 29 - TXD Pin Direction in Single-Wire Mode

pub fn r9t8(&mut self) -> R9T8_W

Bit 30 - Receive Bit 9 / Transmit Bit 8

pub fn r8t9(&mut self) -> R8T9_W

Bit 31 - Receive Bit 8 / Transmit Bit 9

impl W<u32, Reg<u32, _DATA>>

pub fn r0t0(&mut self) -> R0T0_W

Bit 0 - R0T0

pub fn r1t1(&mut self) -> R1T1_W

Bit 1 - R1T1

pub fn r2t2(&mut self) -> R2T2_W

Bit 2 - R2T2

pub fn r3t3(&mut self) -> R3T3_W

Bit 3 - R3T3

pub fn r4t4(&mut self) -> R4T4_W

Bit 4 - R4T4

pub fn r5t5(&mut self) -> R5T5_W

Bit 5 - R5T5

pub fn r6t6(&mut self) -> R6T6_W

Bit 6 - R6T6

pub fn r7t7(&mut self) -> R7T7_W

Bit 7 - R7T7

pub fn r8t8(&mut self) -> R8T8_W

Bit 8 - R8T8

pub fn r9t9(&mut self) -> R9T9_W

Bit 9 - R9T9

pub fn fretsc(&mut self) -> FRETSC_W

Bit 13 - Frame Error / Transmit Special Character

impl W<u32, Reg<u32, _MATCH>>

pub fn ma1(&mut self) -> MA1_W

Bits 0:9 - Match Address 1

pub fn ma2(&mut self) -> MA2_W

Bits 16:25 - Match Address 2

impl W<u32, Reg<u32, _MODIR>>

pub fn txctse(&mut self) -> TXCTSE_W

Bit 0 - Transmitter clear-to-send enable

pub fn txrtse(&mut self) -> TXRTSE_W

Bit 1 - Transmitter request-to-send enable

pub fn txrtspol(&mut self) -> TXRTSPOL_W

Bit 2 - Transmitter request-to-send polarity

pub fn rxrtse(&mut self) -> RXRTSE_W

Bit 3 - Receiver request-to-send enable

pub fn txctsc(&mut self) -> TXCTSC_W

Bit 4 - Transmit CTS Configuration

pub fn txctssrc(&mut self) -> TXCTSSRC_W

Bit 5 - Transmit CTS Source

pub fn rtswater(&mut self) -> RTSWATER_W

Bits 8:9 - Receive RTS Configuration

pub fn tnp(&mut self) -> TNP_W

Bits 16:17 - Transmitter narrow pulse

pub fn iren(&mut self) -> IREN_W

Bit 18 - Infrared enable

impl W<u32, Reg<u32, _FIFO>>

pub fn rxfe(&mut self) -> RXFE_W

Bit 3 - Receive FIFO Enable

pub fn txfe(&mut self) -> TXFE_W

Bit 7 - Transmit FIFO Enable

pub fn rxufe(&mut self) -> RXUFE_W

Bit 8 - Receive FIFO Underflow Interrupt Enable

pub fn txofe(&mut self) -> TXOFE_W

Bit 9 - Transmit FIFO Overflow Interrupt Enable

pub fn rxiden(&mut self) -> RXIDEN_W

Bits 10:12 - Receiver Idle Empty Enable

pub fn rxflush(&mut self) -> RXFLUSH_W

Bit 14 - Receive FIFO/Buffer Flush

pub fn txflush(&mut self) -> TXFLUSH_W

Bit 15 - Transmit FIFO/Buffer Flush

pub fn rxuf(&mut self) -> RXUF_W

Bit 16 - Receiver Buffer Underflow Flag

pub fn txof(&mut self) -> TXOF_W

Bit 17 - Transmitter Buffer Overflow Flag

impl W<u32, Reg<u32, _WATER>>

pub fn txwater(&mut self) -> TXWATER_W

Bits 0:1 - Transmit Watermark

pub fn rxwater(&mut self) -> RXWATER_W

Bits 16:17 - Receive Watermark

impl W<u32, Reg<u32, _GLOBAL>>

pub fn rst(&mut self) -> RST_W

Bit 1 - Software Reset

impl W<u32, Reg<u32, _PINCFG>>

pub fn trgsel(&mut self) -> TRGSEL_W

Bits 0:1 - Trigger Select

impl W<u32, Reg<u32, _BAUD>>

pub fn sbr(&mut self) -> SBR_W

Bits 0:12 - Baud Rate Modulo Divisor.

pub fn sbns(&mut self) -> SBNS_W

Bit 13 - Stop Bit Number Select

pub fn rxedgie(&mut self) -> RXEDGIE_W

Bit 14 - RX Input Active Edge Interrupt Enable

pub fn lbkdie(&mut self) -> LBKDIE_W

Bit 15 - LIN Break Detect Interrupt Enable

pub fn resyncdis(&mut self) -> RESYNCDIS_W

Bit 16 - Resynchronization Disable

pub fn bothedge(&mut self) -> BOTHEDGE_W

Bit 17 - Both Edge Sampling

pub fn matcfg(&mut self) -> MATCFG_W

Bits 18:19 - Match Configuration

pub fn ridmae(&mut self) -> RIDMAE_W

Bit 20 - Receiver Idle DMA Enable

pub fn rdmae(&mut self) -> RDMAE_W

Bit 21 - Receiver Full DMA Enable

pub fn tdmae(&mut self) -> TDMAE_W

Bit 23 - Transmitter DMA Enable

pub fn osr(&mut self) -> OSR_W

Bits 24:28 - Oversampling Ratio

pub fn m10(&mut self) -> M10_W

Bit 29 - 10-bit Mode select

pub fn maen2(&mut self) -> MAEN2_W

Bit 30 - Match Address Mode Enable 2

pub fn maen1(&mut self) -> MAEN1_W

Bit 31 - Match Address Mode Enable 1

impl W<u32, Reg<u32, _STAT>>

pub fn ma2f(&mut self) -> MA2F_W

Bit 14 - Match 2 Flag

pub fn ma1f(&mut self) -> MA1F_W

Bit 15 - Match 1 Flag

pub fn pf(&mut self) -> PF_W

Bit 16 - Parity Error Flag

pub fn fe(&mut self) -> FE_W

Bit 17 - Framing Error Flag

pub fn nf(&mut self) -> NF_W

Bit 18 - Noise Flag

pub fn or(&mut self) -> OR_W

Bit 19 - Receiver Overrun Flag

pub fn idle(&mut self) -> IDLE_W

Bit 20 - Idle Line Flag

pub fn lbkde(&mut self) -> LBKDE_W

Bit 25 - LIN Break Detection Enable

pub fn brk13(&mut self) -> BRK13_W

Bit 26 - Break Character Generation Length

pub fn rwuid(&mut self) -> RWUID_W

Bit 27 - Receive Wake Up Idle Detect

pub fn rxinv(&mut self) -> RXINV_W

Bit 28 - Receive Data Inversion

pub fn msbf(&mut self) -> MSBF_W

Bit 29 - MSB First

pub fn rxedgif(&mut self) -> RXEDGIF_W

Bit 30 - RXD Pin Active Edge Interrupt Flag

pub fn lbkdif(&mut self) -> LBKDIF_W

Bit 31 - LIN Break Detect Interrupt Flag

impl W<u32, Reg<u32, _CTRL>>

pub fn pt(&mut self) -> PT_W

Bit 0 - Parity Type

pub fn pe(&mut self) -> PE_W

Bit 1 - Parity Enable

pub fn ilt(&mut self) -> ILT_W

Bit 2 - Idle Line Type Select

pub fn wake(&mut self) -> WAKE_W

Bit 3 - Receiver Wakeup Method Select

pub fn m(&mut self) -> M_W

Bit 4 - 9-Bit or 8-Bit Mode Select

pub fn rsrc(&mut self) -> RSRC_W

Bit 5 - Receiver Source Select

pub fn dozeen(&mut self) -> DOZEEN_W

Bit 6 - Doze Enable

pub fn loops(&mut self) -> LOOPS_W

Bit 7 - Loop Mode Select

pub fn idlecfg(&mut self) -> IDLECFG_W

Bits 8:10 - Idle Configuration

pub fn m7(&mut self) -> M7_W

Bit 11 - 7-Bit Mode Select

pub fn ma2ie(&mut self) -> MA2IE_W

Bit 14 - Match 2 Interrupt Enable

pub fn ma1ie(&mut self) -> MA1IE_W

Bit 15 - Match 1 Interrupt Enable

pub fn sbk(&mut self) -> SBK_W

Bit 16 - Send Break

pub fn rwu(&mut self) -> RWU_W

Bit 17 - Receiver Wakeup Control

pub fn re(&mut self) -> RE_W

Bit 18 - Receiver Enable

pub fn te(&mut self) -> TE_W

Bit 19 - Transmitter Enable

pub fn ilie(&mut self) -> ILIE_W

Bit 20 - Idle Line Interrupt Enable

pub fn rie(&mut self) -> RIE_W

Bit 21 - Receiver Interrupt Enable

pub fn tcie(&mut self) -> TCIE_W

Bit 22 - Transmission Complete Interrupt Enable for

pub fn tie(&mut self) -> TIE_W

Bit 23 - Transmit Interrupt Enable

pub fn peie(&mut self) -> PEIE_W

Bit 24 - Parity Error Interrupt Enable

pub fn feie(&mut self) -> FEIE_W

Bit 25 - Framing Error Interrupt Enable

pub fn neie(&mut self) -> NEIE_W

Bit 26 - Noise Error Interrupt Enable

pub fn orie(&mut self) -> ORIE_W

Bit 27 - Overrun Interrupt Enable

pub fn txinv(&mut self) -> TXINV_W

Bit 28 - Transmit Data Inversion

pub fn txdir(&mut self) -> TXDIR_W

Bit 29 - TXD Pin Direction in Single-Wire Mode

pub fn r9t8(&mut self) -> R9T8_W

Bit 30 - Receive Bit 9 / Transmit Bit 8

pub fn r8t9(&mut self) -> R8T9_W

Bit 31 - Receive Bit 8 / Transmit Bit 9

impl W<u32, Reg<u32, _DATA>>

pub fn r0t0(&mut self) -> R0T0_W

Bit 0 - R0T0

pub fn r1t1(&mut self) -> R1T1_W

Bit 1 - R1T1

pub fn r2t2(&mut self) -> R2T2_W

Bit 2 - R2T2

pub fn r3t3(&mut self) -> R3T3_W

Bit 3 - R3T3

pub fn r4t4(&mut self) -> R4T4_W

Bit 4 - R4T4

pub fn r5t5(&mut self) -> R5T5_W

Bit 5 - R5T5

pub fn r6t6(&mut self) -> R6T6_W

Bit 6 - R6T6

pub fn r7t7(&mut self) -> R7T7_W

Bit 7 - R7T7

pub fn r8t8(&mut self) -> R8T8_W

Bit 8 - R8T8

pub fn r9t9(&mut self) -> R9T9_W

Bit 9 - R9T9

pub fn fretsc(&mut self) -> FRETSC_W

Bit 13 - Frame Error / Transmit Special Character

impl W<u32, Reg<u32, _MATCH>>

pub fn ma1(&mut self) -> MA1_W

Bits 0:9 - Match Address 1

pub fn ma2(&mut self) -> MA2_W

Bits 16:25 - Match Address 2

impl W<u32, Reg<u32, _MODIR>>

pub fn txctse(&mut self) -> TXCTSE_W

Bit 0 - Transmitter clear-to-send enable

pub fn txrtse(&mut self) -> TXRTSE_W

Bit 1 - Transmitter request-to-send enable

pub fn txrtspol(&mut self) -> TXRTSPOL_W

Bit 2 - Transmitter request-to-send polarity

pub fn rxrtse(&mut self) -> RXRTSE_W

Bit 3 - Receiver request-to-send enable

pub fn txctsc(&mut self) -> TXCTSC_W

Bit 4 - Transmit CTS Configuration

pub fn txctssrc(&mut self) -> TXCTSSRC_W

Bit 5 - Transmit CTS Source

pub fn rtswater(&mut self) -> RTSWATER_W

Bits 8:9 - Receive RTS Configuration

pub fn tnp(&mut self) -> TNP_W

Bits 16:17 - Transmitter narrow pulse

pub fn iren(&mut self) -> IREN_W

Bit 18 - Infrared enable

impl W<u32, Reg<u32, _FIFO>>

pub fn rxfe(&mut self) -> RXFE_W

Bit 3 - Receive FIFO Enable

pub fn txfe(&mut self) -> TXFE_W

Bit 7 - Transmit FIFO Enable

pub fn rxufe(&mut self) -> RXUFE_W

Bit 8 - Receive FIFO Underflow Interrupt Enable

pub fn txofe(&mut self) -> TXOFE_W

Bit 9 - Transmit FIFO Overflow Interrupt Enable

pub fn rxiden(&mut self) -> RXIDEN_W

Bits 10:12 - Receiver Idle Empty Enable

pub fn rxflush(&mut self) -> RXFLUSH_W

Bit 14 - Receive FIFO/Buffer Flush

pub fn txflush(&mut self) -> TXFLUSH_W

Bit 15 - Transmit FIFO/Buffer Flush

pub fn rxuf(&mut self) -> RXUF_W

Bit 16 - Receiver Buffer Underflow Flag

pub fn txof(&mut self) -> TXOF_W

Bit 17 - Transmitter Buffer Overflow Flag

impl W<u32, Reg<u32, _WATER>>

pub fn txwater(&mut self) -> TXWATER_W

Bits 0:1 - Transmit Watermark

pub fn rxwater(&mut self) -> RXWATER_W

Bits 16:17 - Receive Watermark

impl W<u32, Reg<u32, _GLOBAL>>

pub fn rst(&mut self) -> RST_W

Bit 1 - Software Reset

impl W<u32, Reg<u32, _PINCFG>>

pub fn trgsel(&mut self) -> TRGSEL_W

Bits 0:1 - Trigger Select

impl W<u32, Reg<u32, _BAUD>>

pub fn sbr(&mut self) -> SBR_W

Bits 0:12 - Baud Rate Modulo Divisor.

pub fn sbns(&mut self) -> SBNS_W

Bit 13 - Stop Bit Number Select

pub fn rxedgie(&mut self) -> RXEDGIE_W

Bit 14 - RX Input Active Edge Interrupt Enable

pub fn lbkdie(&mut self) -> LBKDIE_W

Bit 15 - LIN Break Detect Interrupt Enable

pub fn resyncdis(&mut self) -> RESYNCDIS_W

Bit 16 - Resynchronization Disable

pub fn bothedge(&mut self) -> BOTHEDGE_W

Bit 17 - Both Edge Sampling

pub fn matcfg(&mut self) -> MATCFG_W

Bits 18:19 - Match Configuration

pub fn ridmae(&mut self) -> RIDMAE_W

Bit 20 - Receiver Idle DMA Enable

pub fn rdmae(&mut self) -> RDMAE_W

Bit 21 - Receiver Full DMA Enable

pub fn tdmae(&mut self) -> TDMAE_W

Bit 23 - Transmitter DMA Enable

pub fn osr(&mut self) -> OSR_W

Bits 24:28 - Oversampling Ratio

pub fn m10(&mut self) -> M10_W

Bit 29 - 10-bit Mode select

pub fn maen2(&mut self) -> MAEN2_W

Bit 30 - Match Address Mode Enable 2

pub fn maen1(&mut self) -> MAEN1_W

Bit 31 - Match Address Mode Enable 1

impl W<u32, Reg<u32, _STAT>>

pub fn ma2f(&mut self) -> MA2F_W

Bit 14 - Match 2 Flag

pub fn ma1f(&mut self) -> MA1F_W

Bit 15 - Match 1 Flag

pub fn pf(&mut self) -> PF_W

Bit 16 - Parity Error Flag

pub fn fe(&mut self) -> FE_W

Bit 17 - Framing Error Flag

pub fn nf(&mut self) -> NF_W

Bit 18 - Noise Flag

pub fn or(&mut self) -> OR_W

Bit 19 - Receiver Overrun Flag

pub fn idle(&mut self) -> IDLE_W

Bit 20 - Idle Line Flag

pub fn lbkde(&mut self) -> LBKDE_W

Bit 25 - LIN Break Detection Enable

pub fn brk13(&mut self) -> BRK13_W

Bit 26 - Break Character Generation Length

pub fn rwuid(&mut self) -> RWUID_W

Bit 27 - Receive Wake Up Idle Detect

pub fn rxinv(&mut self) -> RXINV_W

Bit 28 - Receive Data Inversion

pub fn msbf(&mut self) -> MSBF_W

Bit 29 - MSB First

pub fn rxedgif(&mut self) -> RXEDGIF_W

Bit 30 - RXD Pin Active Edge Interrupt Flag

pub fn lbkdif(&mut self) -> LBKDIF_W

Bit 31 - LIN Break Detect Interrupt Flag

impl W<u32, Reg<u32, _CTRL>>

pub fn pt(&mut self) -> PT_W

Bit 0 - Parity Type

pub fn pe(&mut self) -> PE_W

Bit 1 - Parity Enable

pub fn ilt(&mut self) -> ILT_W

Bit 2 - Idle Line Type Select

pub fn wake(&mut self) -> WAKE_W

Bit 3 - Receiver Wakeup Method Select

pub fn m(&mut self) -> M_W

Bit 4 - 9-Bit or 8-Bit Mode Select

pub fn rsrc(&mut self) -> RSRC_W

Bit 5 - Receiver Source Select

pub fn dozeen(&mut self) -> DOZEEN_W

Bit 6 - Doze Enable

pub fn loops(&mut self) -> LOOPS_W

Bit 7 - Loop Mode Select

pub fn idlecfg(&mut self) -> IDLECFG_W

Bits 8:10 - Idle Configuration

pub fn m7(&mut self) -> M7_W

Bit 11 - 7-Bit Mode Select

pub fn ma2ie(&mut self) -> MA2IE_W

Bit 14 - Match 2 Interrupt Enable

pub fn ma1ie(&mut self) -> MA1IE_W

Bit 15 - Match 1 Interrupt Enable

pub fn sbk(&mut self) -> SBK_W

Bit 16 - Send Break

pub fn rwu(&mut self) -> RWU_W

Bit 17 - Receiver Wakeup Control

pub fn re(&mut self) -> RE_W

Bit 18 - Receiver Enable

pub fn te(&mut self) -> TE_W

Bit 19 - Transmitter Enable

pub fn ilie(&mut self) -> ILIE_W

Bit 20 - Idle Line Interrupt Enable

pub fn rie(&mut self) -> RIE_W

Bit 21 - Receiver Interrupt Enable

pub fn tcie(&mut self) -> TCIE_W

Bit 22 - Transmission Complete Interrupt Enable for

pub fn tie(&mut self) -> TIE_W

Bit 23 - Transmit Interrupt Enable

pub fn peie(&mut self) -> PEIE_W

Bit 24 - Parity Error Interrupt Enable

pub fn feie(&mut self) -> FEIE_W

Bit 25 - Framing Error Interrupt Enable

pub fn neie(&mut self) -> NEIE_W

Bit 26 - Noise Error Interrupt Enable

pub fn orie(&mut self) -> ORIE_W

Bit 27 - Overrun Interrupt Enable

pub fn txinv(&mut self) -> TXINV_W

Bit 28 - Transmit Data Inversion

pub fn txdir(&mut self) -> TXDIR_W

Bit 29 - TXD Pin Direction in Single-Wire Mode

pub fn r9t8(&mut self) -> R9T8_W

Bit 30 - Receive Bit 9 / Transmit Bit 8

pub fn r8t9(&mut self) -> R8T9_W

Bit 31 - Receive Bit 8 / Transmit Bit 9

impl W<u32, Reg<u32, _DATA>>

pub fn r0t0(&mut self) -> R0T0_W

Bit 0 - R0T0

pub fn r1t1(&mut self) -> R1T1_W

Bit 1 - R1T1

pub fn r2t2(&mut self) -> R2T2_W

Bit 2 - R2T2

pub fn r3t3(&mut self) -> R3T3_W

Bit 3 - R3T3

pub fn r4t4(&mut self) -> R4T4_W

Bit 4 - R4T4

pub fn r5t5(&mut self) -> R5T5_W

Bit 5 - R5T5

pub fn r6t6(&mut self) -> R6T6_W

Bit 6 - R6T6

pub fn r7t7(&mut self) -> R7T7_W

Bit 7 - R7T7

pub fn r8t8(&mut self) -> R8T8_W

Bit 8 - R8T8

pub fn r9t9(&mut self) -> R9T9_W

Bit 9 - R9T9

pub fn fretsc(&mut self) -> FRETSC_W

Bit 13 - Frame Error / Transmit Special Character

impl W<u32, Reg<u32, _MATCH>>

pub fn ma1(&mut self) -> MA1_W

Bits 0:9 - Match Address 1

pub fn ma2(&mut self) -> MA2_W

Bits 16:25 - Match Address 2

impl W<u32, Reg<u32, _MODIR>>

pub fn txctse(&mut self) -> TXCTSE_W

Bit 0 - Transmitter clear-to-send enable

pub fn txrtse(&mut self) -> TXRTSE_W

Bit 1 - Transmitter request-to-send enable

pub fn txrtspol(&mut self) -> TXRTSPOL_W

Bit 2 - Transmitter request-to-send polarity

pub fn rxrtse(&mut self) -> RXRTSE_W

Bit 3 - Receiver request-to-send enable

pub fn txctsc(&mut self) -> TXCTSC_W

Bit 4 - Transmit CTS Configuration

pub fn txctssrc(&mut self) -> TXCTSSRC_W

Bit 5 - Transmit CTS Source

pub fn rtswater(&mut self) -> RTSWATER_W

Bits 8:9 - Receive RTS Configuration

pub fn tnp(&mut self) -> TNP_W

Bits 16:17 - Transmitter narrow pulse

pub fn iren(&mut self) -> IREN_W

Bit 18 - Infrared enable

impl W<u32, Reg<u32, _FIFO>>

pub fn rxfe(&mut self) -> RXFE_W

Bit 3 - Receive FIFO Enable

pub fn txfe(&mut self) -> TXFE_W

Bit 7 - Transmit FIFO Enable

pub fn rxufe(&mut self) -> RXUFE_W

Bit 8 - Receive FIFO Underflow Interrupt Enable

pub fn txofe(&mut self) -> TXOFE_W

Bit 9 - Transmit FIFO Overflow Interrupt Enable

pub fn rxiden(&mut self) -> RXIDEN_W

Bits 10:12 - Receiver Idle Empty Enable

pub fn rxflush(&mut self) -> RXFLUSH_W

Bit 14 - Receive FIFO/Buffer Flush

pub fn txflush(&mut self) -> TXFLUSH_W

Bit 15 - Transmit FIFO/Buffer Flush

pub fn rxuf(&mut self) -> RXUF_W

Bit 16 - Receiver Buffer Underflow Flag

pub fn txof(&mut self) -> TXOF_W

Bit 17 - Transmitter Buffer Overflow Flag

impl W<u32, Reg<u32, _WATER>>

pub fn txwater(&mut self) -> TXWATER_W

Bits 0:1 - Transmit Watermark

pub fn rxwater(&mut self) -> RXWATER_W

Bits 16:17 - Receive Watermark

impl W<u32, Reg<u32, _C0>>

pub fn hystctr(&mut self) -> HYSTCTR_W

Bits 0:1 - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level

pub fn offset(&mut self) -> OFFSET_W

Bit 2 - Comparator hard block offset control. See chip data sheet to get the actual offset value with each level

pub fn filter_cnt(&mut self) -> FILTER_CNT_W

Bits 4:6 - Filter Sample Count

pub fn en(&mut self) -> EN_W

Bit 8 - Comparator Module Enable

pub fn ope(&mut self) -> OPE_W

Bit 9 - Comparator Output Pin Enable

pub fn cos(&mut self) -> COS_W

Bit 10 - Comparator Output Select

pub fn invt(&mut self) -> INVT_W

Bit 11 - Comparator invert

pub fn pmode(&mut self) -> PMODE_W

Bit 12 - Power Mode Select

pub fn we(&mut self) -> WE_W

Bit 14 - Windowing Enable

pub fn se(&mut self) -> SE_W

Bit 15 - Sample Enable

pub fn fpr(&mut self) -> FPR_W

Bits 16:23 - Filter Sample Period

pub fn cff(&mut self) -> CFF_W

Bit 25 - Analog Comparator Flag Falling

pub fn cfr(&mut self) -> CFR_W

Bit 26 - Analog Comparator Flag Rising

pub fn ief(&mut self) -> IEF_W

Bit 27 - Comparator Interrupt Enable Falling

pub fn ier(&mut self) -> IER_W

Bit 28 - Comparator Interrupt Enable Rising

pub fn dmaen(&mut self) -> DMAEN_W

Bit 30 - DMA Enable

impl W<u32, Reg<u32, _C1>>

pub fn vosel(&mut self) -> VOSEL_W

Bits 0:7 - DAC Output Voltage Select

pub fn msel(&mut self) -> MSEL_W

Bits 8:10 - Minus Input MUX Control

pub fn psel(&mut self) -> PSEL_W

Bits 11:13 - Plus Input MUX Control

pub fn vrsel(&mut self) -> VRSEL_W

Bit 14 - Supply Voltage Reference Source Select

pub fn dacen(&mut self) -> DACEN_W

Bit 15 - DAC Enable

pub fn chn0(&mut self) -> CHN0_W

Bit 16 - Channel 0 input enable

pub fn chn1(&mut self) -> CHN1_W

Bit 17 - Channel 1 input enable

pub fn chn2(&mut self) -> CHN2_W

Bit 18 - Channel 2 input enable

pub fn chn3(&mut self) -> CHN3_W

Bit 19 - Channel 3 input enable

pub fn chn4(&mut self) -> CHN4_W

Bit 20 - Channel 4 input enable

pub fn chn5(&mut self) -> CHN5_W

Bit 21 - Channel 5 input enable

pub fn chn6(&mut self) -> CHN6_W

Bit 22 - Channel 6 input enable

pub fn chn7(&mut self) -> CHN7_W

Bit 23 - Channel 7 input enable

pub fn innsel(&mut self) -> INNSEL_W

Bits 24:25 - Selection of the input to the negative port of the comparator

pub fn inpsel(&mut self) -> INPSEL_W

Bits 27:28 - Selection of the input to the positive port of the comparator

impl W<u32, Reg<u32, _C2>>

pub fn acon(&mut self) -> ACON_W

Bits 0:7 - The result of the input comparison for channel n

pub fn initmod(&mut self) -> INITMOD_W

Bits 8:13 - Comparator and DAC initialization delay modulus.

pub fn nsam(&mut self) -> NSAM_W

Bits 14:15 - Number of sample clocks

pub fn ch0f(&mut self) -> CH0F_W

Bit 16 - Channel 0 input changed flag

pub fn ch1f(&mut self) -> CH1F_W

Bit 17 - Channel 1 input changed flag

pub fn ch2f(&mut self) -> CH2F_W

Bit 18 - Channel 2 input changed flag

pub fn ch3f(&mut self) -> CH3F_W

Bit 19 - Channel 3 input changed flag

pub fn ch4f(&mut self) -> CH4F_W

Bit 20 - Channel 4 input changed flag

pub fn ch5f(&mut self) -> CH5F_W

Bit 21 - Channel 5 input changed flag

pub fn ch6f(&mut self) -> CH6F_W

Bit 22 - Channel 6 input changed flag

pub fn ch7f(&mut self) -> CH7F_W

Bit 23 - Channel 7 input changed flag

pub fn fxmxch(&mut self) -> FXMXCH_W

Bits 25:27 - Fixed channel selection

pub fn fxmp(&mut self) -> FXMP_W

Bit 29 - Fixed MUX Port

pub fn rrie(&mut self) -> RRIE_W

Bit 30 - Round-Robin interrupt enable

pub fn rre(&mut self) -> RRE_W

Bit 31 - Round-Robin Enable

impl W<u8, Reg<u8, _LVDSC1>>

pub fn lvdre(&mut self) -> LVDRE_W

Bit 4 - Low Voltage Detect Reset Enable

pub fn lvdie(&mut self) -> LVDIE_W

Bit 5 - Low Voltage Detect Interrupt Enable

pub fn lvdack(&mut self) -> LVDACK_W

Bit 6 - Low Voltage Detect Acknowledge

impl W<u8, Reg<u8, _LVDSC2>>

pub fn lvwie(&mut self) -> LVWIE_W

Bit 5 - Low-Voltage Warning Interrupt Enable

pub fn lvwack(&mut self) -> LVWACK_W

Bit 6 - Low-Voltage Warning Acknowledge

impl W<u8, Reg<u8, _REGSC>>

pub fn biasen(&mut self) -> BIASEN_W

Bit 0 - Bias Enable Bit

pub fn clkbiasdis(&mut self) -> CLKBIASDIS_W

Bit 1 - Clock Bias Disable Bit

pub fn lpodis(&mut self) -> LPODIS_W

Bit 7 - LPO Disable Bit

impl W<u8, Reg<u8, _LPOTRIM>>

pub fn lpotrim(&mut self) -> LPOTRIM_W

Bits 0:4 - LPO trimming bits

impl W<u32, Reg<u32, _PMPROT>>

pub fn avlp(&mut self) -> AVLP_W

Bit 5 - Allow Very-Low-Power Modes

pub fn ahsrun(&mut self) -> AHSRUN_W

Bit 7 - Allow High Speed Run mode

impl W<u32, Reg<u32, _PMCTRL>>

pub fn stopm(&mut self) -> STOPM_W

Bits 0:2 - Stop Mode Control

pub fn runm(&mut self) -> RUNM_W

Bits 5:6 - Run Mode Control

impl W<u32, Reg<u32, _STOPCTRL>>

pub fn stopo(&mut self) -> STOPO_W

Bits 6:7 - Stop Option

impl W<u32, Reg<u32, _RPC>>

pub fn rstfltsrw(&mut self) -> RSTFLTSRW_W

Bits 0:1 - Reset Pin Filter Select in Run and Wait Modes

pub fn rstfltss(&mut self) -> RSTFLTSS_W

Bit 2 - Reset Pin Filter Select in Stop Mode

pub fn rstfltsel(&mut self) -> RSTFLTSEL_W

Bits 8:12 - Reset Pin Filter Bus Clock Select

impl W<u32, Reg<u32, _SSRS>>

pub fn slvd(&mut self) -> SLVD_W

Bit 1 - Sticky Low-Voltage Detect Reset

pub fn sloc(&mut self) -> SLOC_W

Bit 2 - Sticky Loss-of-Clock Reset

pub fn slol(&mut self) -> SLOL_W

Bit 3 - Sticky Loss-of-Lock Reset

pub fn swdog(&mut self) -> SWDOG_W

Bit 5 - Sticky Watchdog

pub fn spin(&mut self) -> SPIN_W

Bit 6 - Sticky External Reset Pin

pub fn spor(&mut self) -> SPOR_W

Bit 7 - Sticky Power-On Reset

pub fn sjtag(&mut self) -> SJTAG_W

Bit 8 - Sticky JTAG generated reset

pub fn slockup(&mut self) -> SLOCKUP_W

Bit 9 - Sticky Core Lockup

pub fn ssw(&mut self) -> SSW_W

Bit 10 - Sticky Software

pub fn smdm_ap(&mut self) -> SMDM_AP_W

Bit 11 - Sticky MDM-AP System Reset Request

pub fn ssackerr(&mut self) -> SSACKERR_W

Bit 13 - Sticky Stop Acknowledge Error

impl W<u32, Reg<u32, _SRIE>>

pub fn delay(&mut self) -> DELAY_W

Bits 0:1 - Reset Delay Time

pub fn loc(&mut self) -> LOC_W

Bit 2 - Loss-of-Clock Interrupt

pub fn lol(&mut self) -> LOL_W

Bit 3 - Loss-of-Lock Interrupt

pub fn wdog(&mut self) -> WDOG_W

Bit 5 - Watchdog Interrupt

pub fn pin(&mut self) -> PIN_W

Bit 6 - External Reset Pin Interrupt

pub fn gie(&mut self) -> GIE_W

Bit 7 - Global Interrupt Enable

pub fn jtag(&mut self) -> JTAG_W

Bit 8 - JTAG generated reset

pub fn lockup(&mut self) -> LOCKUP_W

Bit 9 - Core Lockup Interrupt

pub fn sw(&mut self) -> SW_W

Bit 10 - Software Interrupt

pub fn mdm_ap(&mut self) -> MDM_AP_W

Bit 11 - MDM-AP System Reset Request

pub fn sackerr(&mut self) -> SACKERR_W

Bit 13 - Stop Acknowledge Error Interrupt

impl W<u32, Reg<u32, _PDOR>>

pub fn pdo(&mut self) -> PDO_W

Bits 0:31 - Port Data Output

impl W<u32, Reg<u32, _PSOR>>

pub fn ptso(&mut self) -> PTSO_W

Bits 0:31 - Port Set Output

impl W<u32, Reg<u32, _PCOR>>

pub fn ptco(&mut self) -> PTCO_W

Bits 0:31 - Port Clear Output

impl W<u32, Reg<u32, _PTOR>>

pub fn ptto(&mut self) -> PTTO_W

Bits 0:31 - Port Toggle Output

impl W<u32, Reg<u32, _PDDR>>

pub fn pdd(&mut self) -> PDD_W

Bits 0:31 - Port Data Direction

impl W<u32, Reg<u32, _PIDR>>

pub fn pid(&mut self) -> PID_W

Bits 0:31 - Port Input Disable

impl W<u32, Reg<u32, _PDOR>>

pub fn pdo(&mut self) -> PDO_W

Bits 0:31 - Port Data Output

impl W<u32, Reg<u32, _PSOR>>

pub fn ptso(&mut self) -> PTSO_W

Bits 0:31 - Port Set Output

impl W<u32, Reg<u32, _PCOR>>

pub fn ptco(&mut self) -> PTCO_W

Bits 0:31 - Port Clear Output

impl W<u32, Reg<u32, _PTOR>>

pub fn ptto(&mut self) -> PTTO_W

Bits 0:31 - Port Toggle Output

impl W<u32, Reg<u32, _PDDR>>

pub fn pdd(&mut self) -> PDD_W

Bits 0:31 - Port Data Direction

impl W<u32, Reg<u32, _PIDR>>

pub fn pid(&mut self) -> PID_W

Bits 0:31 - Port Input Disable

impl W<u32, Reg<u32, _PDOR>>

pub fn pdo(&mut self) -> PDO_W

Bits 0:31 - Port Data Output

impl W<u32, Reg<u32, _PSOR>>

pub fn ptso(&mut self) -> PTSO_W

Bits 0:31 - Port Set Output

impl W<u32, Reg<u32, _PCOR>>

pub fn ptco(&mut self) -> PTCO_W

Bits 0:31 - Port Clear Output

impl W<u32, Reg<u32, _PTOR>>

pub fn ptto(&mut self) -> PTTO_W

Bits 0:31 - Port Toggle Output

impl W<u32, Reg<u32, _PDDR>>

pub fn pdd(&mut self) -> PDD_W

Bits 0:31 - Port Data Direction

impl W<u32, Reg<u32, _PIDR>>

pub fn pid(&mut self) -> PID_W

Bits 0:31 - Port Input Disable

impl W<u32, Reg<u32, _PDOR>>

pub fn pdo(&mut self) -> PDO_W

Bits 0:31 - Port Data Output

impl W<u32, Reg<u32, _PSOR>>

pub fn ptso(&mut self) -> PTSO_W

Bits 0:31 - Port Set Output

impl W<u32, Reg<u32, _PCOR>>

pub fn ptco(&mut self) -> PTCO_W

Bits 0:31 - Port Clear Output

impl W<u32, Reg<u32, _PTOR>>

pub fn ptto(&mut self) -> PTTO_W

Bits 0:31 - Port Toggle Output

impl W<u32, Reg<u32, _PDDR>>

pub fn pdd(&mut self) -> PDD_W

Bits 0:31 - Port Data Direction

impl W<u32, Reg<u32, _PIDR>>

pub fn pid(&mut self) -> PID_W

Bits 0:31 - Port Input Disable

impl W<u32, Reg<u32, _PDOR>>

pub fn pdo(&mut self) -> PDO_W

Bits 0:31 - Port Data Output

impl W<u32, Reg<u32, _PSOR>>

pub fn ptso(&mut self) -> PTSO_W

Bits 0:31 - Port Set Output

impl W<u32, Reg<u32, _PCOR>>

pub fn ptco(&mut self) -> PTCO_W

Bits 0:31 - Port Clear Output

impl W<u32, Reg<u32, _PTOR>>

pub fn ptto(&mut self) -> PTTO_W

Bits 0:31 - Port Toggle Output

impl W<u32, Reg<u32, _PDDR>>

pub fn pdd(&mut self) -> PDD_W

Bits 0:31 - Port Data Direction

impl W<u32, Reg<u32, _PIDR>>

pub fn pid(&mut self) -> PID_W

Bits 0:31 - Port Input Disable

impl W<u32, Reg<u32, _CPCR>>

pub fn cbrr(&mut self) -> CBRR_W

Bit 9 - Crossbar Round-robin Arbitration Enable

pub fn sramuap(&mut self) -> SRAMUAP_W

Bits 24:25 - SRAM_U Arbitration Priority

pub fn sramuwp(&mut self) -> SRAMUWP_W

Bit 26 - SRAM_U Write Protect

pub fn sramlap(&mut self) -> SRAMLAP_W

Bits 28:29 - SRAM_L Arbitration Priority

pub fn sramlwp(&mut self) -> SRAMLWP_W

Bit 30 - SRAM_L Write Protect

impl W<u32, Reg<u32, _ISCR>>

pub fn fioce(&mut self) -> FIOCE_W

Bit 24 - FPU Invalid Operation Interrupt Enable

pub fn fdzce(&mut self) -> FDZCE_W

Bit 25 - FPU Divide-by-Zero Interrupt Enable

pub fn fofce(&mut self) -> FOFCE_W

Bit 26 - FPU Overflow Interrupt Enable

pub fn fufce(&mut self) -> FUFCE_W

Bit 27 - FPU Underflow Interrupt Enable

pub fn fixce(&mut self) -> FIXCE_W

Bit 28 - FPU Inexact Interrupt Enable

pub fn fidce(&mut self) -> FIDCE_W

Bit 31 - FPU Input Denormal Interrupt Enable

impl W<u32, Reg<u32, _PID>>

pub fn pid(&mut self) -> PID_W

Bits 0:7 - M0_PID and M1_PID for MPU

impl W<u32, Reg<u32, _CPO>>

pub fn cporeq(&mut self) -> CPOREQ_W

Bit 0 - Compute Operation Request

pub fn cpowoi(&mut self) -> CPOWOI_W

Bit 2 - Compute Operation Wakeup On Interrupt

impl W<u32, Reg<u32, _LMDR0>>

pub fn cf0(&mut self) -> CF0_W

Bits 0:3 - Control Field 0

pub fn cf1(&mut self) -> CF1_W

Bits 4:7 - Control Field 1

pub fn lock(&mut self) -> LOCK_W

Bit 16 - LOCK

impl W<u32, Reg<u32, _LMDR1>>

pub fn cf0(&mut self) -> CF0_W

Bits 0:3 - Control Field 0

pub fn cf1(&mut self) -> CF1_W

Bits 4:7 - Control Field 1

pub fn lock(&mut self) -> LOCK_W

Bit 16 - LOCK

impl W<u32, Reg<u32, _LMDR2>>

pub fn cf1(&mut self) -> CF1_W

Bits 4:7 - Control Field 1

pub fn lock(&mut self) -> LOCK_W

Bit 16 - LOCK

impl W<u32, Reg<u32, _LMPECR>>

pub fn erncr(&mut self) -> ERNCR_W

Bit 0 - Enable RAM ECC Noncorrectable Reporting

pub fn er1br(&mut self) -> ER1BR_W

Bit 8 - Enable RAM ECC 1 Bit Reporting

pub fn ecpr(&mut self) -> ECPR_W

Bit 20 - Enable Cache Parity Reporting

impl W<u32, Reg<u32, _LMPEIR>>

pub fn enc(&mut self) -> ENC_W

Bits 0:7 - ENCn = ECC Noncorrectable Error n

pub fn e1b(&mut self) -> E1B_W

Bits 8:15 - E1Bn = ECC 1-bit Error n

pub fn pe(&mut self) -> PE_W

Bits 16:23 - Cache Parity Error

impl W<u32, Reg<u32, _LMEM_PCCCR>>

pub fn encache(&mut self) -> ENCACHE_W

Bit 0 - Cache enable

pub fn pccr2(&mut self) -> PCCR2_W

Bit 2 - Forces all cacheable spaces to write through

pub fn pccr3(&mut self) -> PCCR3_W

Bit 3 - Forces no allocation on cache misses (must also have PCCR2 asserted)

pub fn invw0(&mut self) -> INVW0_W

Bit 24 - Invalidate Way 0

pub fn pushw0(&mut self) -> PUSHW0_W

Bit 25 - Push Way 0

pub fn invw1(&mut self) -> INVW1_W

Bit 26 - Invalidate Way 1

pub fn pushw1(&mut self) -> PUSHW1_W

Bit 27 - Push Way 1

pub fn go(&mut self) -> GO_W

Bit 31 - Initiate Cache Command

impl W<u32, Reg<u32, _LMEM_PCCLCR>>

pub fn lgo(&mut self) -> LGO_W

Bit 0 - Initiate Cache Line Command

pub fn cacheaddr(&mut self) -> CACHEADDR_W

Bits 2:13 - Cache address

pub fn wsel(&mut self) -> WSEL_W

Bit 14 - Way select

pub fn tdsel(&mut self) -> TDSEL_W

Bit 16 - Tag/Data Select

pub fn lcivb(&mut self) -> LCIVB_W

Bit 20 - Line Command Initial Valid Bit

pub fn lcimb(&mut self) -> LCIMB_W

Bit 21 - Line Command Initial Modified Bit

pub fn lcway(&mut self) -> LCWAY_W

Bit 22 - Line Command Way

pub fn lcmd(&mut self) -> LCMD_W

Bits 24:25 - Line Command

pub fn ladsel(&mut self) -> LADSEL_W

Bit 26 - Line Address Select

pub fn lacc(&mut self) -> LACC_W

Bit 27 - Line access type

impl W<u32, Reg<u32, _LMEM_PCCSAR>>

pub fn lgo(&mut self) -> LGO_W

Bit 0 - Initiate Cache Line Command

pub fn phyaddr(&mut self) -> PHYADDR_W

Bits 2:31 - Physical Address

impl W<u32, Reg<u32, _LMEM_PCCCVR>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Cache read/write Data

impl W<u32, Reg<u32, _PCCRMR>>

pub fn r15(&mut self) -> R15_W

Bits 0:1 - Region 15 mode

pub fn r14(&mut self) -> R14_W

Bits 2:3 - Region 14 mode

pub fn r13(&mut self) -> R13_W

Bits 4:5 - Region 13 mode

pub fn r12(&mut self) -> R12_W

Bits 6:7 - Region 12 mode

pub fn r11(&mut self) -> R11_W

Bits 8:9 - Region 11 mode

pub fn r10(&mut self) -> R10_W

Bits 10:11 - Region 10 mode

pub fn r9(&mut self) -> R9_W

Bits 12:13 - Region 9 mode

pub fn r8(&mut self) -> R8_W

Bits 14:15 - Region 8 mode

pub fn r7(&mut self) -> R7_W

Bits 16:17 - Region 7 mode

pub fn r6(&mut self) -> R6_W

Bits 18:19 - Region 6 mode

pub fn r5(&mut self) -> R5_W

Bits 20:21 - Region 5 mode

pub fn r4(&mut self) -> R4_W

Bits 22:23 - Region 4 mode

pub fn r3(&mut self) -> R3_W

Bits 24:25 - Region 3 mode

pub fn r2(&mut self) -> R2_W

Bits 26:27 - Region 2 mode

pub fn r1(&mut self) -> R1_W

Bits 28:29 - Region 1 mode

pub fn r0(&mut self) -> R0_W

Bits 30:31 - Region 0 mode