Struct Flash

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pub struct Flash<SPI, CS: OutputPin> { /* private fields */ }

Expand description

Driver for 25-series SPI Flash chips.

§Type Parameters

SPI: The SPI master to which the flash chip is attached.
CS: The Chip-Select line attached to the \CS/\CE pin of the flash chip.

Implementations§

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impl<SPI: Transfer<u8>, CS: OutputPin> Flash<SPI, CS>

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pub fn init(spi: SPI, cs: CS) -> Result<Self, Error<SPI, CS>>

Creates a new 25-series flash driver.

§Parameters

spi: An SPI master. Must be configured to operate in the correct mode for the device.
cs: The Chip-Select Pin connected to the \CS/\CE pin of the flash chip. Will be driven low when accessing the device.

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pub fn read_jedec_id(&mut self) -> Result<Identification, Error<SPI, CS>>

Reads the JEDEC manufacturer/device identification.

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pub fn read_status(&mut self) -> Result<Status, Error<SPI, CS>>

Reads the status register.

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pub fn get_device_info(&mut self) -> Result<FlashInfo, Error<SPI, CS>>

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pub fn write_enable(&mut self) -> Result<(), Error<SPI, CS>>

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pub fn power_down(&mut self) -> Result<(), Error<SPI, CS>>

Enters power down mode. Datasheet, 8.2.35: Power-down: Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in Figure 44.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down instruction will not be executed. After /CS is driven high, the power-down state will entered within the time duration of tDP (See AC Characteristics). While in the power-down state only the Release Power-down / Device ID (ABh) instruction, which restores the device to normal operation, will be recognized. All other instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1.

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pub fn release_power_down<D: DelayUs<u8>>( &mut self, delay: &mut D, ) -> Result<(), Error<SPI, CS>>

Exits Power Down Mode Datasheet, 8.2.36: Release Power-down: The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number.
To release the device from the power-down state, the instruction is issued by driving the /CS pin low, shifting the instruction code “ABh” and driving /CS high as shown in Figure 45. Release from power-down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other instructions are accepted. The /CS pin must remain high during the tRES1 time duration.

Note: must manually delay after running this, IOC

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pub fn read(&mut self, addr: u32, buf: &mut [u8]) -> Result<(), Error<SPI, CS>>

Reads flash contents into buf, starting at addr.

Note that addr is not fully decoded: Flash chips will typically only look at the lowest N bits needed to encode their size, which means that the contents are “mirrored” to addresses that are a multiple of the flash size. Only 24 bits of addr are transferred to the device in any case, limiting the maximum size of 25-series SPI flash chips to 16 MiB.