Crate sv_sim_sim 

sv-sim-sim: the netlist/analysis/state/scheduler/process/determinism kernel (ARCHITECTURE.md §3, §6.2-6.5).

This wave materializes only the cross-track contract surface each module exposes to the others and to sv-sim-codegen/sv-sim-runtime/sv-sim-debug (types, traits, #[repr(C)] ABI-adjacent shapes) — the tracks that own each module (state, sched, netlist, A2-process, and the determinism face-off winner) fill in the real elaboration/scheduling/rollback logic in later waves. See docs/CONTRACTS.md for the full item -> owning-track -> consumer -> ledger-id table.

Modules

analysis

ANALYSIS (sv-sim-sim::analysis) — the WOCB static-analysis pass’s hand-off surface (netlist-analysis.md §Key Data Structures — partitioning, CDC edges, DPI/VPI tagging, and the ForceObserved runtime-invalidation hook ARCHITECTURE §4/§9 requires), plus (as of Task 8) the real, sv-lang-Analysis-backed driver graph, WOCB partitioning and clock-domain/CDC-edge inference: crate::analysis:: analyze(). See docs/superpowers/plans/2026-09-23-wave-A-netlist.md Task 8.

collections

SV queues, dynamic arrays and associative arrays (LRM 1800-2023 §7.5, §7.8, §7.10): variable-size collections held outside STATE.

constraints

Constraint solving for randomize() (LRM 1800-2023 Clause 18).

covergroup

Functional coverage (IEEE 1800-2023 Clause 19): the pure model.

determinism

DETERMINISM (sv-sim-sim::determinism) — cross-track contract and, as of Task 3, its v1 implementation: the pluggable ordering/rollback interface the scheduler hands ready-sets to (scheduler.md §6, ARCHITECTURE §4). The scheduler “never itself assigns threads or implements rollback” — every concrete controller (the v1 degenerate sequential oracle, and later WOCB) is this track’s own implementation, not materialized in sched.

dpi_task

Blocking DPI import-task calls (LRM 1800-2023 35.5.3, 35.7, 35.9).

driver_counts

$countdrivers data (IEEE 1800-2023 D.2, Table D.1): per net bit, how many drivers are at 0, 1 and x (a driver at z is not counted). A net resolver records them next to its %v strengths (sv_sim_exec::nets) under the net’s strength key; a net no resolver runs for has at most one driver, so sv_rt_net_drivers reads its count off the net itself.

fiber

Stackful fibers for blocking DPI import tasks (LRM 1800-2023 35.5.3, 35.7, 35.9).

image

The design image: everything a slang-free runner needs, as plain data.

netlist

NETLIST (sv-sim-sim::netlist) — the identity/dedup ID types and the Netlist hand-off surface (netlist-analysis.md §Key Data Structures / Public Interfaces) that CODEGEN, STATE, SCHED, RUNTIME and the debugger all address signals/instances through, plus (as of this wave’s Task 1) the real, sv-lang-backed elaboration pipeline: a deterministic DFS over Design::top_instances() producing a Netlist that implements NetlistView. See docs/superpowers/plans/2026-09-23-wave-A-netlist.md.

objects

Classes plan (docs/superpowers/plans/2026-10-03-classes.md) Task 3: the object heap runtime (LRM 1800-2023 §8.29 memory management, §8.4 object identity). Pure-Rust, zero sv-lang/codegen dependency (this task’s own acceptance text) — see crate::netlist::ClassTemplateId’s doc comment for why that id, despite being produced by the frontend-gated netlist::classes module, is itself defined unconditionally and usable from here.

patterns

Pattern matching (IEEE 1800-2023 12.6): what the analysis side needs.

process

A2-PROCESS (sv-sim-sim::process) — cross-track contract only: the process template lowering shape shared between the A2-process track and CODEGEN (process.md). Real liveness analysis / CFG construction belongs to the A2-process track, not this wave.

sched

SCHED (sv-sim-sim::sched) — cross-track contract only: the event scheduler/kernel-control surface shared with STATE, A2-PROCESS, DETERMINISM, RUNTIME and the debugger (scheduler.md). Real event-queue/time-wheel implementation belongs to the sched track, not this wave.

state

STATE (sv-sim-sim::state) — cross-track contract only: the Rust-owned 4-state arena’s SoA layout query shape, its value-change fan-out primitive, and the one canonical signal read/write/subscribe interface (ARCHITECTURE §2: “Signal read/write/subscribe: STATE owns the one canonical primitive; VPI/FST/debugger are pure consumers”). The arena implementation itself belongs to the state track, not this contracts wave.

strings

SV string values (LRM 1800-2023 §6.16).

sva

SVA (concurrent assertions, Clause 16/17) runtime support (docs/superpowers/plans/2026-10-03-sva.md).

symid

A symbol’s identity as a map key.

timing_types

Slang-free timing data shared by the planner (netlist::specify, behind the frontend feature) and the executors (sv-sim-exec, which a built .so links): a module path’s transition-delay table and the pulse style. Both travel inside a design image, hence the serde derives.

winref

ref arguments bound to a window of a variable or class property (LRM 1800-2023 13.5.2): f(s.n), f(v[3:0]), f(obj.x), f(g).