#[repr(u16)]pub enum Opcode {
Show 319 variants
HALT = 0,
NOP = 1,
REI = 2,
BPT = 3,
RET = 4,
RSB = 5,
LDPCTX = 6,
SVPCTX = 7,
CVTPS = 8,
CVTSP = 9,
INDEX = 10,
CRC = 11,
PROBER = 12,
PROBEW = 13,
INSQUE = 14,
REMQUE = 15,
BSBB = 16,
BRB = 17,
BNEQ = 18,
BEQL = 19,
BGTR = 20,
BLEQ = 21,
JSB = 22,
JMP = 23,
BGEQ = 24,
BLSS = 25,
BGTRU = 26,
BLEQU = 27,
BVC = 28,
BVS = 29,
BGEQU = 30,
BLSSU = 31,
ADDP4 = 32,
ADDP6 = 33,
SUBP4 = 34,
SUBP6 = 35,
CVTPT = 36,
MULP = 37,
CVTTP = 38,
DIVP = 39,
MOVC3 = 40,
CMPC3 = 41,
SCANC = 42,
SPANC = 43,
MOVC5 = 44,
CMPC5 = 45,
MOVTC = 46,
MOVTUC = 47,
BSBW = 48,
BRW = 49,
CVTWL = 50,
CVTWB = 51,
MOVP = 52,
CMPP3 = 53,
CVTPL = 54,
CMPP4 = 55,
EDITPC = 56,
MATCHC = 57,
LOCC = 58,
SKPC = 59,
MOVZWL = 60,
ACBW = 61,
MOVAW = 62,
PUSHAW = 63,
ADDF2 = 64,
ADDF3 = 65,
SUBF2 = 66,
SUBF3 = 67,
MULF2 = 68,
MULF3 = 69,
DIVF2 = 70,
DIVF3 = 71,
CVTFB = 72,
CVTFW = 73,
CVTFL = 74,
CVTRFL = 75,
CVTBF = 76,
CVTWF = 77,
CVTLF = 78,
ACBF = 79,
MOVF = 80,
CMPF = 81,
MNEGF = 82,
TSTF = 83,
EMODF = 84,
POLYF = 85,
CVTFD = 86,
ADAWI = 87,
INSQHI = 88,
INSQTI = 89,
REMQHI = 90,
REMQTI = 91,
ADDD2 = 92,
ADDD3 = 93,
SUBD2 = 94,
SUBD3 = 95,
MULD2 = 96,
MULD3 = 97,
DIVD2 = 98,
DIVD3 = 99,
CVTDB = 100,
CVTDW = 101,
CVTDL = 102,
CVTRDL = 103,
CVTBD = 104,
CVTWD = 105,
CVTLD = 106,
ACBD = 107,
MOVD = 108,
CMPD = 109,
MNEGD = 110,
TSTD = 111,
EMODD = 112,
POLYD = 113,
CVTDF = 114,
ASHL = 115,
ASHQ = 116,
EMUL = 117,
EDIV = 118,
CLRQ = 119,
MOVQ = 120,
MOVAQ = 121,
PUSHAQ = 122,
ADDB2 = 123,
ADDB3 = 124,
SUBB2 = 125,
SUBB3 = 126,
MULB2 = 127,
MULB3 = 128,
DIVB2 = 129,
DIVB3 = 130,
BISB2 = 131,
BISB3 = 132,
BICB2 = 133,
BICB3 = 134,
XORB2 = 135,
XORB3 = 136,
MNEGB = 137,
CASEB = 138,
MOVB = 139,
CMPB = 140,
MCOMB = 141,
BITB = 142,
CLRB = 143,
TSTB = 144,
INCB = 145,
DECB = 146,
CVTBL = 147,
CVTBW = 148,
MOVZBL = 149,
MOVZBW = 150,
ROTL = 151,
ACBB = 152,
MOVAB = 153,
PUSHAB = 154,
ADDW2 = 155,
ADDW3 = 156,
SUBW2 = 157,
SUBW3 = 158,
MULW2 = 159,
MULW3 = 160,
DIVW2 = 161,
DIVW3 = 162,
BISW2 = 163,
BISW3 = 164,
BICW2 = 165,
BICW3 = 166,
XORW2 = 167,
XORW3 = 168,
MNEGW = 169,
CASEW = 170,
MOVW = 171,
CMPW = 172,
MCOMW = 173,
BITW = 174,
CLRW = 175,
TSTW = 176,
INCW = 177,
DECW = 178,
BISPSW = 179,
BICPSW = 180,
POPR = 181,
PUSHR = 182,
CHMK = 183,
CHME = 184,
CHMS = 185,
CHMU = 186,
ADDL2 = 187,
ADDL3 = 188,
SUBL2 = 189,
SUBL3 = 190,
MULL2 = 191,
MULL3 = 192,
DIVL2 = 193,
DIVL3 = 194,
BISL2 = 195,
BISL3 = 196,
BICL2 = 197,
BICL3 = 198,
XORL2 = 199,
XORL3 = 200,
MNEGL = 201,
CASEL = 202,
MOVL = 203,
CMPL = 204,
MCOML = 205,
BITL = 206,
CLRL = 207,
TSTL = 208,
INCL = 209,
DECL = 210,
ADWC = 211,
SBWC = 212,
MTPR = 213,
MFPR = 214,
MOVPSL = 215,
PUSHL = 216,
MOVAL = 217,
PUSHAL = 218,
BBS = 219,
BBC = 220,
BBSS = 221,
BBCS = 222,
BBSC = 223,
BBCC = 224,
BBSSI = 225,
BBCCI = 226,
BLBS = 227,
BLBC = 228,
FFS = 229,
FFC = 230,
CMPV = 231,
CMPZV = 232,
EXTV = 233,
EXTZV = 234,
INSV = 235,
ACBL = 236,
AOBLSS = 237,
AOBLEQ = 238,
SOBGEQ = 239,
SOBGTR = 240,
CVTLB = 241,
CVTLW = 242,
ASHP = 243,
CVTLP = 244,
CALLG = 245,
CALLC = 246,
XFC = 247,
CVTDH = 248,
CVTGF = 249,
ADDG2 = 250,
ADDG3 = 251,
SUBG2 = 252,
SUBG3 = 253,
MULG2 = 254,
MULG3 = 255,
DIVG2 = 256,
DIVG3 = 257,
CVTGB = 258,
CVTGW = 259,
CVTGL = 260,
CVTRGL = 261,
CVTBG = 262,
CVTWG = 263,
CVTLG = 264,
ACBG = 265,
MOVG = 266,
CMPG = 267,
MNEGG = 268,
TSTG = 269,
EMODG = 270,
POLYG = 271,
CVTGH = 272,
ADDH2 = 273,
ADDH3 = 274,
SUBH2 = 275,
SUBH3 = 276,
MULH2 = 277,
MULH3 = 278,
DIVH2 = 279,
DIVH3 = 280,
CVTHB = 281,
CVTHW = 282,
CVTHL = 283,
CVTRHL = 284,
CVTBH = 285,
CVTWH = 286,
CVTLH = 287,
ACBH = 288,
MOVH = 289,
CMPH = 290,
MNEGH = 291,
TSTH = 292,
EMODH = 293,
POLYH = 294,
CVTHG = 295,
CLRO = 296,
MOVO = 297,
MOVAO = 298,
PUSHAO = 299,
CVTFH = 300,
CVTFG = 301,
CVTHF = 302,
CVTHD = 303,
BUGL = 304,
BUGW = 305,
BNEQU = 306,
BEQLU = 307,
BCC = 308,
BCS = 309,
CLRD = 310,
CLRG = 311,
MOVAD = 312,
MOVAG = 313,
PUSHAD = 314,
PUSHAG = 315,
CLRH = 316,
MOVAH = 317,
PUSHAH = 318,
}
Expand description
§VAX Opcode
Variants§
HALT = 0
Halt
Opcode HALT = 0x00
NOP = 1
No Operation
Opcode NOP = 0x01
REI = 2
Return from Exception or Interrupt
Opcode REI = 0x02
BPT = 3
Breakpoint
Opcode BPT = 0x03
RET = 4
Return from Procedure
Opcode RET = 0x04
RSB = 5
Return From Subroutine
Opcode RSB = 0x05
LDPCTX = 6
Load Process Context
Opcode LDPCTX = 0x06
SVPCTX = 7
Save Process Context
Opcode SVPCTX = 0x07
CVTPS = 8
Convert Packed to Leading Separate Numeric
Opcode CVTPS = 0x08
CVTSP = 9
Convert Leading Separate Numeric to Packed
Opcode CVTSP = 0x09
INDEX = 10
Compute Index
Opcode INDEX = 0x0A
CRC = 11
Calculate Cyclic Redundancy Check
Opcode CRC = 0x0B
PROBER = 12
Probe Read Accessibility
Opcode PROBER = 0x0C
PROBEW = 13
Probe Write Accessibility
Opcode PROBEW = 0x0D
INSQUE = 14
Insert Entry in Queue
Opcode INSQUE = 0x0E
REMQUE = 15
Remove Entry from Queue
Opcode REMQUE = 0x0F
BSBB = 16
Branch to Subroutine With Byte Displacement
Opcode BSBB = 0x10
BRB = 17
Branch With Byte Displacement
Opcode BRB = 0x11
BNEQ = 18
Branch on Not Equal (signed) [Z EQL 0]
Opcode BNEQ = 0x12
BEQL = 19
Branch on Equal (signed) [Z EQL 1]
Opcode BEQL = 0x13
BGTR = 20
Branch on Greater Than (signed) [{N OR Z} EQL 0]
Opcode BGTR = 0x14
BLEQ = 21
Branch on Less Than or Equal (signed) [{N OR Z} EQL 1]
Opcode BLEQ = 0x15
JSB = 22
Jump to Subroutine
Opcode JSB = 0x16
JMP = 23
Jump
Opcode JMP = 0x17
BGEQ = 24
Branch on Greater Than or Equal (signed) [N EQL 0]
Opcode BGEQ = 0x18
BLSS = 25
Branch on Less Than (signed) [N EQL 1]
Opcode BLSS = 0x19
BGTRU = 26
Branch on Greater Than (unsigned) [{C OR Z} EQL 0]
Opcode BGTRU = 0x1A
BLEQU = 27
Branch on Less Than or Equal (unsigned) [{C OR Z} EQL 1]
Opcode BLEQU = 0x1B
BVC = 28
Branch on Overflow Clear [V EQL 0]
Opcode BVC = 0x1C
BVS = 29
Branch on Overflow Set [V EQL 1]
Opcode BVS = 0x1D
BGEQU = 30
Branch on Greater Than or Equal (unsigned) [C EQL 0]
Opcode BGEQU = 0x1E
BLSSU = 31
Branch on Less Than (unsigned) [C EQL 1]
Opcode BLSSU = 0x1F
ADDP4 = 32
Add Packed 4 Operand
Opcode ADDP4 = 0x20
ADDP6 = 33
Add Packed 6 Operand
Opcode ADDP6 = 0x21
SUBP4 = 34
Subtract Packed 4 Operand
Opcode SUBP4 = 0x22
SUBP6 = 35
Subtract Packed 6 Operand
Opcode SUBP6 = 0x23
CVTPT = 36
Convert Packed to Trailing Numeric
Opcode CVTPT = 0x24
MULP = 37
Multiply Packed
Opcode MULP = 0x25
CVTTP = 38
Convert Trailing Numeric to Packed
Opcode CVTTP = 0x26
DIVP = 39
Divide Packed
Opcode DIVP = 0x27
MOVC3 = 40
Move Character 3 Operand
Opcode MOVC3 = 0x28
CMPC3 = 41
Compare Characters 3 Operand
Opcode CMPC3 = 0x29
SCANC = 42
Scan Characters
Opcode SCANC = 0x2A
SPANC = 43
Span Characters
Opcode SPANC = 0x2B
MOVC5 = 44
Move Character 5 Operand
Opcode MOVC5 = 0x2C
CMPC5 = 45
Compare Characters 5 Operand
Opcode CMPC5 = 0x2D
MOVTC = 46
Move Translated Characters
Opcode MOVTC = 0x2E
MOVTUC = 47
Move Translated Until Character
Opcode MOVTUC = 0x2F
BSBW = 48
Branch to Subroutine With Word Displacement
Opcode BSBW = 0x30
BRW = 49
Branch With Word Displacement
Opcode BRW = 0x31
CVTWL = 50
Convert Word to Long
Opcode CVTWL = 0x32
CVTWB = 51
Convert Word to Byte
Opcode CVTWB = 0x33
MOVP = 52
Move Packed
Opcode MOVP = 0x34
CMPP3 = 53
Compare Packed 3 Operand
Opcode CMPP3 = 0x35
CVTPL = 54
Convert Packed to Long
Opcode CVTPL = 0x36
CMPP4 = 55
Compare Packed 4 Operand
Opcode CMPP4 = 0x37
EDITPC = 56
Edit Packed to Character String
Opcode EDITPC = 0x38
MATCHC = 57
Match Character
Opcode MATCHC = 0x39
LOCC = 58
Locate Character
Opcode LOCC = 0x3A
SKPC = 59
Skip Character
Opcode SKPC = 0x3B
MOVZWL = 60
Move Zero-Extended Word to Long
Opcode MOVZWL = 0x3C
ACBW = 61
Add Compare and Branch Word
Opcode ACBW = 0x3D
MOVAW = 62
Move Address Word
Opcode MOVAW = 0x3E
PUSHAW = 63
Push Address Word
Opcode PUSHAW = 0x3F
ADDF2 = 64
Add F_floating 2 Operand
Opcode ADDF2 = 0x40
ADDF3 = 65
Add F_floating 3 Operand
Opcode ADDF3 = 0x41
SUBF2 = 66
Subtract F_floating 2 Operand
Opcode SUBF2 = 0x42
SUBF3 = 67
Subtract F_floating 3 Operand
Opcode SUBF3 = 0x43
MULF2 = 68
Multiply F_floating 2 Operand
Opcode MULF2 = 0x44
MULF3 = 69
Multiply F_floating 3 Operand
Opcode MULF3 = 0x45
DIVF2 = 70
Divide F_floating 2 Operand
Opcode DIVF2 = 0x46
DIVF3 = 71
Divide F_floating 3 Operand
Opcode DIVF3 = 0x47
CVTFB = 72
Convert F_floating to Byte
Opcode CVTFB = 0x48
CVTFW = 73
Convert F_floating to Word
Opcode CVTFW = 0x49
CVTFL = 74
Convert F_floating to Long
Opcode CVTFL = 0x4A
CVTRFL = 75
Convert Rounded F_floating to Long
Opcode CVTRFL = 0x4B
CVTBF = 76
Convert Byte to F_floating
Opcode CVTBF = 0x4C
CVTWF = 77
Convert Word to F_floating
Opcode CVTWF = 0x4D
CVTLF = 78
Convert Long to F_floating
Opcode CVTLF = 0x4E
ACBF = 79
Add Compare and Branch F_floating
Opcode ACBF = 0x4F
MOVF = 80
Move F_floating
Opcode MOVF = 0x50
CMPF = 81
Compare F_floating
Opcode CMPF = 0x51
MNEGF = 82
Move Negated F_floating
Opcode MNEGF = 0x52
TSTF = 83
Test F_floating
Opcode TSTF = 0x53
EMODF = 84
Extended Multiply and Integerize F_floating
Opcode EMODF = 0x54
POLYF = 85
Polynomial Evaluation F_floating
Opcode POLYF = 0x55
CVTFD = 86
Convert F_floating to D_floating
Opcode CVTFD = 0x56
ADAWI = 87
Add Aligned Word Interlocked
Opcode ADAWI = 0x58
INSQHI = 88
Insert Entry into Queue at Head Interlocked
Opcode INSQHI = 0x5C
INSQTI = 89
Insert Entry into Queue at Tail Interlocked
Opcode INSQTI = 0x5D
REMQHI = 90
Remove Entry from Queue at Head Interlocked
Opcode REMQHI = 0x5E
REMQTI = 91
Remove Entry from Queue at Tail Interlocked
Opcode REMQTI = 0x5F
ADDD2 = 92
Add D_floating 2 Operand
Opcode ADDD2 = 0x60
ADDD3 = 93
Add D_floating 3 Operand
Opcode ADDD3 = 0x61
SUBD2 = 94
Subtract D_floating 2 Operand
Opcode SUBD2 = 0x62
SUBD3 = 95
Subtract D_floating 3 Operand
Opcode SUBD3 = 0x63
MULD2 = 96
Multiply D_floating 2 Operand
Opcode MULD2 = 0x64
MULD3 = 97
Multiply D_floating 3 Operand
Opcode MULD3 = 0x65
DIVD2 = 98
Divide D_floating 2 Operand
Opcode DIVD2 = 0x66
DIVD3 = 99
Divide D_floating 3 Operand
Opcode DIVD3 = 0x67
CVTDB = 100
Convert D_floating to Byte
Opcode CVTDB = 0x68
CVTDW = 101
Convert D_floating to Word
Opcode CVTDW = 0x69
CVTDL = 102
Convert D_floating to Long
Opcode CVTDL = 0x6A
CVTRDL = 103
Convert Rounded D_floating to Long
Opcode CVTRDL = 0x6B
CVTBD = 104
Convert Byte to D_floating
Opcode CVTBD = 0x6C
CVTWD = 105
Convert Word to D_floating
Opcode CVTWD = 0x6D
CVTLD = 106
Convert Long to D_floating
Opcode CVTLD = 0x6E
ACBD = 107
Add Compare and Branch D_floating
Opcode ACBD = 0x6F
MOVD = 108
Move D_floating
Opcode MOVD = 0x70
CMPD = 109
Compare D_floating
Opcode CMPD = 0x71
MNEGD = 110
Move Negated D_floating
Opcode MNEGD = 0x72
TSTD = 111
Test D_floating
Opcode TSTD = 0x73
EMODD = 112
Extended Multiply and Integerize D_floating
Opcode EMODD = 0x74
POLYD = 113
Polynomial Evaluation D_floating
Opcode POLYD = 0x75
CVTDF = 114
Convert D_floating to F_floating
Opcode CVTDF = 0x76
ASHL = 115
Arithmetic Shift Long
Opcode ASHL = 0x78
ASHQ = 116
Arithmetic Shift Quad
Opcode ASHQ = 0x79
EMUL = 117
Extended Multiply
Opcode EMUL = 0x7A
EDIV = 118
Extended Divide
Opcode EDIV = 0x7B
CLRQ = 119
Clear Quad
Opcode CLRQ = 0x7C
MOVQ = 120
Move Quad
Opcode MOVQ = 0x7D
MOVAQ = 121
Move Address Quad
Opcode MOVAQ = 0x7E
PUSHAQ = 122
Push Address Quad
Opcode PUSHAQ = 0x7F
ADDB2 = 123
Add Byte 2 Operand
Opcode ADDB2 = 0x80
ADDB3 = 124
Add Byte 3 Operand
Opcode ADDB3 = 0x81
SUBB2 = 125
Subtract Byte 2 Operand
Opcode SUBB2 = 0x82
SUBB3 = 126
Subtract Byte 3 Operand
Opcode SUBB3 = 0x83
MULB2 = 127
Multiply Byte 2 Operand
Opcode MULB2 = 0x84
MULB3 = 128
Multiply Byte 3 Operand
Opcode MULB3 = 0x85
DIVB2 = 129
Divide Byte 2 Operand
Opcode DIVB2 = 0x86
DIVB3 = 130
Divide Byte 3 Operand
Opcode DIVB3 = 0x87
BISB2 = 131
Bit Set Byte 2 Operand
Opcode BISB2 = 0x88
BISB3 = 132
Bit Set Byte 3 Operand
Opcode BISB3 = 0x89
BICB2 = 133
Bit Clear Byte 2 Operand
Opcode BICB2 = 0x8A
BICB3 = 134
Bit Clear Byte 3 Operand
Opcode BICB3 = 0x8B
XORB2 = 135
Exclusive-OR Byte 2 Operand
Opcode XORB2 = 0x8C
XORB3 = 136
Exclusive-OR Byte 3 Operand
Opcode XORB3 = 0x8D
MNEGB = 137
Move Negated Byte
Opcode MNEGB = 0x8E
CASEB = 138
Case Byte
Opcode CASEB = 0x8F
MOVB = 139
Move Byte
Opcode MOVB = 0x90
CMPB = 140
Compare Byte
Opcode CMPB = 0x91
MCOMB = 141
Move Complemented Byte
Opcode MCOMB = 0x92
BITB = 142
Bit Test Byte
Opcode BITB = 0x93
CLRB = 143
Clear Byte
Opcode CLRB = 0x94
TSTB = 144
Test Byte
Opcode TSTB = 0x95
INCB = 145
Increment Byte
Opcode INCB = 0x96
DECB = 146
Decrement Byte
Opcode DECB = 0x97
CVTBL = 147
Convert Byte to Long
Opcode CVTBL = 0x98
CVTBW = 148
Convert Byte to Word
Opcode CVTBW = 0x99
MOVZBL = 149
Move Zero-Extended Byte to Long
Opcode MOVZBL = 0x9A
MOVZBW = 150
Move Zero-Extended Byte to Word
Opcode MOVZBW = 0x9B
ROTL = 151
Rotate Long
Opcode ROTL = 0x9C
ACBB = 152
Add Compare and Branch Byte
Opcode ACBB = 0x9D
MOVAB = 153
Move Address Byte
Opcode MOVAB = 0x9E
PUSHAB = 154
Push Address Byte
Opcode PUSHAB = 0x9F
ADDW2 = 155
Add Word 2 Operand
Opcode ADDW2 = 0xA0
ADDW3 = 156
Add Word 3 Operand
Opcode ADDW3 = 0xA1
SUBW2 = 157
Subtract Word 2 Operand
Opcode SUBW2 = 0xA2
SUBW3 = 158
Subtract Word 3 Operand
Opcode SUBW3 = 0xA3
MULW2 = 159
Multiply Word 2 Operand
Opcode MULW2 = 0xA4
MULW3 = 160
Multiply Word 3 Operand
Opcode MULW3 = 0xA5
DIVW2 = 161
Divide Word 2 Operand
Opcode DIVW2 = 0xA6
DIVW3 = 162
Divide Word 3 Operand
Opcode DIVW3 = 0xA7
BISW2 = 163
Bit Set Word 2 Operand
Opcode BISW2 = 0xA8
BISW3 = 164
Bit Set Word 3 Operand
Opcode BISW3 = 0xA9
BICW2 = 165
Bit Clear Word 2 Operand
Opcode BICW2 = 0xAA
BICW3 = 166
Bit Clear Word 3 Operand
Opcode BICW3 = 0xAB
XORW2 = 167
Exclusive-OR Word 2 Operand
Opcode XORW2 = 0xAC
XORW3 = 168
Exclusive-OR Word 3 Operand
Opcode XORW3 = 0xAD
MNEGW = 169
Move Negated Word
Opcode MNEGW = 0xAE
CASEW = 170
Case Word
Opcode CASEW = 0xAF
MOVW = 171
Move Word
Opcode MOVW = 0xB0
CMPW = 172
Compare Word
Opcode CMPW = 0xB1
MCOMW = 173
Move Complemented Word
Opcode MCOMW = 0xB2
BITW = 174
Bit Test Word
Opcode BITW = 0xB3
CLRW = 175
Clear Word
Opcode CLRW = 0xB4
TSTW = 176
Test Word
Opcode TSTW = 0xB5
INCW = 177
Increment Word
Opcode INCW = 0xB6
DECW = 178
Decrement Word
Opcode DECW = 0xB7
BISPSW = 179
Bit Set PSW
Opcode BISPSW = 0xB8
BICPSW = 180
Bit Clear PSW
Opcode BICPSW = 0xB9
POPR = 181
Pop Registers
Opcode POPR = 0xBA
PUSHR = 182
Push Registers
Opcode PUSHR = 0xBB
CHMK = 183
Change Mode to Kernel
Opcode CHMK = 0xBC
CHME = 184
Change Mode to Executive
Opcode CHME = 0xBD
CHMS = 185
Change Mode to Supervisor
Opcode CHMS = 0xBE
CHMU = 186
Change Mode to User
Opcode CHMU = 0xBF
ADDL2 = 187
Add Long 2 Operand
Opcode ADDL2 = 0xC0
ADDL3 = 188
Add Long 3 Operand
Opcode ADDL3 = 0xC1
SUBL2 = 189
Subtract Long 2 Operand
Opcode SUBL2 = 0xC2
SUBL3 = 190
Subtract Long 3 Operand
Opcode SUBL3 = 0xC3
MULL2 = 191
Multiply Long 2 Operand
Opcode MULL2 = 0xC4
MULL3 = 192
Multiply Long 3 Operand
Opcode MULL3 = 0xC5
DIVL2 = 193
Divide Long 2 Operand
Opcode DIVL2 = 0xC6
DIVL3 = 194
Divide Long 3 Operand
Opcode DIVL3 = 0xC7
BISL2 = 195
Bit Set Long 2 Operand
Opcode BISL2 = 0xC8
BISL3 = 196
Bit Set Long 3 Operand
Opcode BISL3 = 0xC9
BICL2 = 197
Bit Clear Long 2 Operand
Opcode BICL2 = 0xCA
BICL3 = 198
Bit Clear Long 3 Operand
Opcode BICL3 = 0xCB
XORL2 = 199
Exclusive-OR Long 2 Operand
Opcode XORL2 = 0xCC
XORL3 = 200
Exclusive-OR Long 3 Operand
Opcode XORL3 = 0xCD
MNEGL = 201
Move Negated Long
Opcode MNEGL = 0xCE
CASEL = 202
Case Long
Opcode CASEL = 0xCF
MOVL = 203
Move Long
Opcode MOVL = 0xD0
CMPL = 204
Compare Long
Opcode CMPL = 0xD1
MCOML = 205
Move Complemented Long
Opcode MCOML = 0xD2
BITL = 206
Bit Test Long
Opcode BITL = 0xD3
CLRL = 207
Clear Long
Opcode CLRL = 0xD4
TSTL = 208
Test Long
Opcode TSTL = 0xD5
INCL = 209
Increment Long
Opcode INCL = 0xD6
DECL = 210
Decrement Long
Opcode DECL = 0xD7
ADWC = 211
Add With Carry
Opcode ADWC = 0xD8
SBWC = 212
Subtract With Carry
Opcode SBWC = 0xD9
MTPR = 213
Move To Processor Register
Opcode MTPR = 0xDA
MFPR = 214
Move From Processor Register
Opcode MFPR = 0xDB
MOVPSL = 215
Move from PSL
Opcode MOVPSL = 0xDC
PUSHL = 216
Push Long
Opcode PUSHL = 0xDD
MOVAL = 217
Move Address Long
Opcode MOVAL = 0xDE
PUSHAL = 218
Push Address Long
Opcode PUSHAL = 0xDF
BBS = 219
Branch on Bit Set
Opcode BBS = 0xE0
BBC = 220
Branch on Bit Clear
Opcode BBC = 0xE1
BBSS = 221
Branch on Bit Set and Set
Opcode BBSS = 0xE2
BBCS = 222
Branch on Bit Clear and Set
Opcode BBCS = 0xE3
BBSC = 223
Branch on Bit Set and Clear
Opcode BBSC = 0xE4
BBCC = 224
Branch on Bit Clear and Clear
Opcode BBCC = 0xE5
BBSSI = 225
Branch on Bit Set and Set Interlocked
Opcode BBSSI = 0xE6
BBCCI = 226
Branch on Bit Clear and Clear Interlocked
Opcode BBCCI = 0xE7
BLBS = 227
Branch on Low Bit Set
Opcode BLBS = 0xE8
BLBC = 228
Branch on Low Bit Clear
Opcode BLBC = 0xE9
FFS = 229
Find First Set
Opcode FFS = 0xEA
FFC = 230
Find First Clear
Opcode FFC = 0xEB
CMPV = 231
Compare Field
Opcode CMPV = 0xEC
CMPZV = 232
Compare Zero-Extended Field
Opcode CMPZV = 0xED
EXTV = 233
Extract Field
Opcode EXTV = 0xEE
EXTZV = 234
Extract Zero-Extended Field
Opcode EXTZV = 0xEF
INSV = 235
Insert Field
Opcode INSV = 0xF0
ACBL = 236
Add Compare and Branch Long
Opcode ACBL = 0xF1
AOBLSS = 237
Add One and Branch Less Than
Opcode AOBLSS = 0xF2
AOBLEQ = 238
Add One and Branch Less Than or Equal
Opcode AOBLEQ = 0xF3
SOBGEQ = 239
Subtract One and Branch Greater Than or Equal
Opcode SOBGEQ = 0xF4
SOBGTR = 240
Subtract One and Branch Greater Than
Opcode SOBGTR = 0xF5
CVTLB = 241
Convert Long to Byte
Opcode CVTLB = 0xF6
CVTLW = 242
Convert Long to Word
Opcode CVTLW = 0xF7
ASHP = 243
Arithmetic Shift and Round Packed
Opcode ASHP = 0xF8
CVTLP = 244
Convert Long to Packed
Opcode CVTLP = 0xF9
CALLG = 245
Call Procedure with General Argument List
Opcode CALLG = 0xFA
CALLC = 246
Call Procedure with Stack Argument List
Opcode CALLC = 0xFB
XFC = 247
Extended Function Call
Opcode XFC = 0xFC
CVTDH = 248
Convert D_floating to H_floating
Opcode CVTDH = 0x32FD
CVTGF = 249
Convert G_floating to F_floating
Opcode CVTGF = 0x33FD
ADDG2 = 250
Add G_floating 2 Operand
Opcode ADDG2 = 0x40FD
ADDG3 = 251
Add G_floating 3 Operand
Opcode ADDG3 = 0x41FD
SUBG2 = 252
Subtract G_floating 2 Operand
Opcode SUBG2 = 0x42FD
SUBG3 = 253
Subtract G_floating 3 Operand
Opcode SUBG3 = 0x43FD
MULG2 = 254
Multiply G_floating 2 Operand
Opcode MULG2 = 0x44FD
MULG3 = 255
Multiply G_floating 3 Operand
Opcode MULG3 = 0x45FD
DIVG2 = 256
Divide G_floating 2 Operand
Opcode DIVG2 = 0x46FD
DIVG3 = 257
Divide G_floating 3 Operand
Opcode DIVG3 = 0x47FD
CVTGB = 258
Convert G_floating to Byte
Opcode CVTGB = 0x48FD
CVTGW = 259
Convert G_floating to Word
Opcode CVTGW = 0x49FD
CVTGL = 260
Convert G_floating to Long
Opcode CVTGL = 0x4AFD
CVTRGL = 261
Convert Rounded G_floating to Long
Opcode CVTRGL = 0x4BFD
CVTBG = 262
Convert Byte to G_floating
Opcode CVTBG = 0x4CFD
CVTWG = 263
Convert Word to G_floating
Opcode CVTWG = 0x4DFD
CVTLG = 264
Convert Long to G_floating
Opcode CVTLG = 0x4EFD
ACBG = 265
Add Compare and Branch G_floating
Opcode ACBG = 0x4FFD
MOVG = 266
Move G_floating
Opcode MOVG = 0x50FD
CMPG = 267
Compare G_floating
Opcode CMPG = 0x51FD
MNEGG = 268
Move Negated G_floating
Opcode MNEGG = 0x52FD
TSTG = 269
Test G_floating
Opcode TSTG = 0x53FD
EMODG = 270
Extended Multiply and Integerize G_floating
Opcode EMODG = 0x54FD
POLYG = 271
Polynomial Evaluation G_floating
Opcode POLYG = 0x55FD
CVTGH = 272
Convert G_floating to H_floating
Opcode CVTGH = 0x56FD
ADDH2 = 273
Add H_floating 2 Operand
Opcode ADDH2 = 0x60FD
ADDH3 = 274
Add H_floating 3 Operand
Opcode ADDH3 = 0x61FD
SUBH2 = 275
Subtract H_floating 2 Operand
Opcode SUBH2 = 0x62FD
SUBH3 = 276
Subtract H_floating 3 Operand
Opcode SUBH3 = 0x63FD
MULH2 = 277
Multiply H_floating 2 Operand
Opcode MULH2 = 0x64FD
MULH3 = 278
Multiply H_floating 3 Operand
Opcode MULH3 = 0x65FD
DIVH2 = 279
Divide H_floating 2 Operand
Opcode DIVH2 = 0x66FD
DIVH3 = 280
Divide H_floating 3 Operand
Opcode DIVH3 = 0x67FD
CVTHB = 281
Convert H_floating to Byte
Opcode CVTHB = 0x68FD
CVTHW = 282
Convert H_floating to Word
Opcode CVTHW = 0x69FD
CVTHL = 283
Convert H_floating to Long
Opcode CVTHL = 0x6AFD
CVTRHL = 284
Convert Rounded H_floating to Long
Opcode CVTRHL = 0x6BFD
CVTBH = 285
Convert Byte to H_floating
Opcode CVTBH = 0x6CFD
CVTWH = 286
Convert Word to H_floating
Opcode CVTWH = 0x6DFD
CVTLH = 287
Convert Long to H_floating
Opcode CVTLH = 0x6EFD
ACBH = 288
Add Compare and Branch H_floating
Opcode ACBH = 0x6FFD
MOVH = 289
Move H_floating
Opcode MOVH = 0x70FD
CMPH = 290
Compare H_floating
Opcode CMPH = 0x71FD
MNEGH = 291
Move Negated H_floating
Opcode MNEGH = 0x72FD
TSTH = 292
Test H_floating
Opcode TSTH = 0x73FD
EMODH = 293
Extended Multiply and Integerize H_floating
Opcode EMODH = 0x74FD
POLYH = 294
Polynomial Evaluation H_floating
Opcode POLYH = 0x75FD
CVTHG = 295
Convert H_floating to G_floating
Opcode CVTHG = 0x76FD
CLRO = 296
Clear Octa
Opcode CLRO = 0x7CFD
MOVO = 297
Move Octa
Opcode MOVO = 0x7DFD
MOVAO = 298
Move Address Octa
Opcode MOVAO = 0x7EFD
PUSHAO = 299
Push Address Octa
Opcode PUSHAO = 0x7FFD
CVTFH = 300
Convert F_floating to H_floating
Opcode CVTFH = 0x98FD
CVTFG = 301
Convert F_floating to G_floating
Opcode CVTFG = 0x99FD
CVTHF = 302
Convert H_floating to F_floating
Opcode CVTHF = 0xF6FD
CVTHD = 303
Convert H_floating to D_floating
Opcode CVTHD = 0xF7FD
BUGL = 304
Bugcheck with Longword Message Identifier
Opcode BUGL = 0xFDFF
BUGW = 305
Bugcheck with Word Message Identifier
Opcode BUGW = 0xFEFF
BNEQU = 306
Branch on Not Equal Unsigned [Z EQL 0]
Opcode BNEQU = 0x12
BEQLU = 307
Branch on Equal Unsigned [Z EQL 1]
Opcode BEQLU = 0x13
BCC = 308
Branch on Carry Clear [C EQL 0]
Opcode BCC = 0x1E
BCS = 309
Branch on Carry Set [C EQL 1]
Opcode BCS = 0x1F
CLRD = 310
Clear D_floating
Opcode CLRD = 0x7C
CLRG = 311
Clear G_floating
Opcode CLRG = 0x7C
MOVAD = 312
Move Address D_floating
Opcode MOVAD = 0x7E
MOVAG = 313
Move Address G_floating
Opcode MOVAG = 0x7E
PUSHAD = 314
Push Address D_floating
Opcode PUSHAD = 0x7F
PUSHAG = 315
Push Address G_floating
Opcode PUSHAG = 0x7F
CLRH = 316
Clear H_floating
Opcode CLRH = 0x7CFD
MOVAH = 317
Move Address H_floating
Opcode MOVAH = 0x7EFD
PUSHAH = 318
Push Address H_floating
Opcode PUSHAH = 0x7FFD
Implementations§
Source§impl Opcode
impl Opcode
Sourcepub fn operand_specs(&self) -> &[(AccessType, DataType)]
pub fn operand_specs(&self) -> &[(AccessType, DataType)]
Return a reference to an array with the access type and data type of the operands for a specific opcode.
§Examples
use vax_disassembler::opcode::{AccessType, DataType, Opcode};
assert_eq!(Opcode::HALT.operand_specs().len(), 0);
assert_eq!(Opcode::HALT.operand_specs(), &[]);
assert_eq!(Opcode::BRB.operand_specs().len(), 1);
assert_eq!(Opcode::BRB.operand_specs(), &[(AccessType::Branch, DataType::Byte)]);
assert_eq!(Opcode::MOVC5.operand_specs().len(), 5);
assert_eq!(Opcode::MOVC5.operand_specs(), &[
(AccessType::Read, DataType::Word),
(AccessType::Address, DataType::Byte),
(AccessType::Read, DataType::Byte),
(AccessType::Read, DataType::Word),
(AccessType::Address, DataType::Byte),
]);
Trait Implementations§
Source§impl Display for Opcode
impl Display for Opcode
Source§fn fmt(&self, f: &mut Formatter<'_>) -> Result
fn fmt(&self, f: &mut Formatter<'_>) -> Result
Formats the value using the given formatter.
§Examples
use vax_disassembler::opcode::{Instruction, Opcode};
use vax_disassembler::operand::{Operand, Register};
assert_eq!(&format!("{}", Opcode::NOP), "NOP");
assert_eq!(&format!("{}", Opcode::MOVC5) , "MOVC5");
assert_eq!(&format!("{}", Opcode::PUSHAW) , "PUSHAW");
assert_eq!(&format!("{}", Opcode::CVTFB) , "CVTFB");
assert_eq!(&format!("{}", Opcode::INSQUE) , "INSQUE");
Source§impl From<&Opcode> for u16
impl From<&Opcode> for u16
Source§fn from(opcode: &Opcode) -> Self
fn from(opcode: &Opcode) -> Self
Convert from a Opcode
reference into the corresponding u16 value.
§Examples
use vax_disassembler::opcode::{Opcode};
use std::convert::TryFrom;
assert_eq!(u16::from(&Opcode::NOP), 1);
assert_eq!(u16::from(&Opcode::BPT), 3);
assert_eq!(u16::from(&Opcode::CLRQ), 0x7c);
assert_eq!(u16::from(&Opcode::CLRD), 0x7c);
assert_eq!(u16::from(&Opcode::CLRO), 0x7cfd);
assert_eq!(u16::from(&Opcode::CLRH), 0x7cfd);
Source§impl From<Opcode> for Instruction
impl From<Opcode> for Instruction
Source§impl TryFrom<u16> for Opcode
impl TryFrom<u16> for Opcode
Source§fn try_from(value: u16) -> Result<Self>
fn try_from(value: u16) -> Result<Self>
Convert from a u16 value into the corresponding Opcode
.
The majority of MACRO32 opcodes are one-byte opcodes, and the u8 value as a u16 will translate into that opcode. If the first byte is 0xFD, 0xFE, or 0xFF, then it is a two-byte opcode. In those cases, the little-endian interpretation of the two byte is used for the conversion (i.e. [0xFD, 0x7C] (the CLRO opcode) is 0x7CFD).
§Examples
use vax_disassembler::opcode::{Opcode};
use std::convert::TryFrom;
assert_eq!(Opcode::try_from(1).unwrap(), Opcode::NOP);
assert_eq!(Opcode::try_from(3).unwrap(), Opcode::BPT);
assert_eq!(Opcode::try_from(0x7c).unwrap(), Opcode::CLRQ);
assert_eq!(Opcode::try_from(0x7cfd).unwrap(), Opcode::CLRO);