1#![doc = "Peripheral access API for VA416XX microcontrollers (generated using svd2rust v0.37.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
2#![allow(non_camel_case_types)]
3#![allow(non_snake_case)]
4#![no_std]
5#![cfg_attr(docsrs, feature(doc_auto_cfg))]
6#[doc = r"Number available in the NVIC for configuring priority"]
7pub const NVIC_PRIO_BITS: u8 = 4;
8#[cfg(feature = "rt")]
9pub use self::Interrupt as interrupt;
10#[cfg(feature = "rt")]
11pub use cortex_m_rt::interrupt;
12#[allow(unused_imports)]
13use generic::*;
14#[doc = r"Common register and bit access and modify traits"]
15pub mod generic;
16#[cfg(feature = "rt")]
17extern "C" {
18 fn U0();
19 fn U1();
20 fn U2();
21 fn U3();
22 fn U4();
23 fn U5();
24 fn U6();
25 fn U7();
26 fn U8();
27 fn U9();
28 fn U10();
29 fn U11();
30 fn U12();
31 fn U13();
32 fn U14();
33 fn U15();
34 fn SPI0_TX();
35 fn SPI0_RX();
36 fn SPI1_TX();
37 fn SPI1_RX();
38 fn SPI2_TX();
39 fn SPI2_RX();
40 fn SPI3_TX();
41 fn SPI3_RX();
42 fn UART0_TX();
43 fn UART0_RX();
44 fn UART1_TX();
45 fn UART1_RX();
46 fn UART2_TX();
47 fn UART2_RX();
48 fn I2C0_MS();
49 fn I2C0_SL();
50 fn I2C1_MS();
51 fn I2C1_SL();
52 fn I2C2_MS();
53 fn I2C2_SL();
54 fn Ethernet();
55 fn U37();
56 fn SpW();
57 fn U39();
58 fn DAC0();
59 fn DAC1();
60 fn TRNG();
61 fn DMA_ERROR();
62 fn ADC();
63 fn LoCLK();
64 fn LVD();
65 fn WATCHDOG();
66 fn TIM0();
67 fn TIM1();
68 fn TIM2();
69 fn TIM3();
70 fn TIM4();
71 fn TIM5();
72 fn TIM6();
73 fn TIM7();
74 fn TIM8();
75 fn TIM9();
76 fn TIM10();
77 fn TIM11();
78 fn TIM12();
79 fn TIM13();
80 fn TIM14();
81 fn TIM15();
82 fn TIM16();
83 fn TIM17();
84 fn TIM18();
85 fn TIM19();
86 fn TIM20();
87 fn TIM21();
88 fn TIM22();
89 fn TIM23();
90 fn CAN0();
91 fn U73();
92 fn CAN1();
93 fn U75();
94 fn EDAC_MBE();
95 fn EDAC_SBE();
96 fn PORTA0();
97 fn PORTA1();
98 fn PORTA2();
99 fn PORTA3();
100 fn PORTA4();
101 fn PORTA5();
102 fn PORTA6();
103 fn PORTA7();
104 fn PORTA8();
105 fn PORTA9();
106 fn PORTA10();
107 fn PORTA11();
108 fn PORTA12();
109 fn PORTA13();
110 fn PORTA14();
111 fn PORTA15();
112 fn PORTB0();
113 fn PORTB1();
114 fn PORTB2();
115 fn PORTB3();
116 fn PORTB4();
117 fn PORTB5();
118 fn PORTB6();
119 fn PORTB7();
120 fn PORTB8();
121 fn PORTB9();
122 fn PORTB10();
123 fn PORTB11();
124 fn PORTB12();
125 fn PORTB13();
126 fn PORTB14();
127 fn PORTB15();
128 fn PORTC0();
129 fn PORTC1();
130 fn PORTC2();
131 fn PORTC3();
132 fn PORTC4();
133 fn PORTC5();
134 fn PORTC6();
135 fn PORTC7();
136 fn PORTC8();
137 fn PORTC9();
138 fn PORTC10();
139 fn PORTC11();
140 fn PORTC12();
141 fn PORTC13();
142 fn PORTC14();
143 fn PORTC15();
144 fn PORTD0();
145 fn PORTD1();
146 fn PORTD2();
147 fn PORTD3();
148 fn PORTD4();
149 fn PORTD5();
150 fn PORTD6();
151 fn PORTD7();
152 fn PORTD8();
153 fn PORTD9();
154 fn PORTD10();
155 fn PORTD11();
156 fn PORTD12();
157 fn PORTD13();
158 fn PORTD14();
159 fn PORTD15();
160 fn PORTE0();
161 fn PORTE1();
162 fn PORTE2();
163 fn PORTE3();
164 fn PORTE4();
165 fn PORTE5();
166 fn PORTE6();
167 fn PORTE7();
168 fn PORTE8();
169 fn PORTE9();
170 fn PORTE10();
171 fn PORTE11();
172 fn PORTE12();
173 fn PORTE13();
174 fn PORTE14();
175 fn PORTE15();
176 fn PORTF0();
177 fn PORTF1();
178 fn PORTF2();
179 fn PORTF3();
180 fn PORTF4();
181 fn PORTF5();
182 fn PORTF6();
183 fn PORTF7();
184 fn PORTF8();
185 fn PORTF9();
186 fn PORTF10();
187 fn PORTF11();
188 fn PORTF12();
189 fn PORTF13();
190 fn PORTF14();
191 fn PORTF15();
192 fn DMA_ACTIVE0();
193 fn DMA_ACTIVE1();
194 fn DMA_ACTIVE2();
195 fn DMA_ACTIVE3();
196 fn DMA_DONE0();
197 fn DMA_DONE1();
198 fn DMA_DONE2();
199 fn DMA_DONE3();
200 fn I2C0_MS_RX();
201 fn I2C0_MS_TX();
202 fn I2C0_SL_RX();
203 fn I2C0_SL_TX();
204 fn I2C1_MS_RX();
205 fn I2C1_MS_TX();
206 fn I2C1_SL_RX();
207 fn I2C1_SL_TX();
208 fn I2C2_MS_RX();
209 fn I2C2_MS_TX();
210 fn I2C2_SL_RX();
211 fn I2C2_SL_TX();
212 fn FPU();
213 fn TXEV();
214}
215#[doc(hidden)]
216#[repr(C)]
217pub union Vector {
218 _handler: unsafe extern "C" fn(),
219 _reserved: u32,
220}
221#[cfg(feature = "rt")]
222#[doc(hidden)]
223#[link_section = ".vector_table.interrupts"]
224#[no_mangle]
225pub static __INTERRUPTS: [Vector; 196] = [
226 Vector { _handler: U0 },
227 Vector { _handler: U1 },
228 Vector { _handler: U2 },
229 Vector { _handler: U3 },
230 Vector { _handler: U4 },
231 Vector { _handler: U5 },
232 Vector { _handler: U6 },
233 Vector { _handler: U7 },
234 Vector { _handler: U8 },
235 Vector { _handler: U9 },
236 Vector { _handler: U10 },
237 Vector { _handler: U11 },
238 Vector { _handler: U12 },
239 Vector { _handler: U13 },
240 Vector { _handler: U14 },
241 Vector { _handler: U15 },
242 Vector { _handler: SPI0_TX },
243 Vector { _handler: SPI0_RX },
244 Vector { _handler: SPI1_TX },
245 Vector { _handler: SPI1_RX },
246 Vector { _handler: SPI2_TX },
247 Vector { _handler: SPI2_RX },
248 Vector { _handler: SPI3_TX },
249 Vector { _handler: SPI3_RX },
250 Vector { _handler: UART0_TX },
251 Vector { _handler: UART0_RX },
252 Vector { _handler: UART1_TX },
253 Vector { _handler: UART1_RX },
254 Vector { _handler: UART2_TX },
255 Vector { _handler: UART2_RX },
256 Vector { _handler: I2C0_MS },
257 Vector { _handler: I2C0_SL },
258 Vector { _handler: I2C1_MS },
259 Vector { _handler: I2C1_SL },
260 Vector { _handler: I2C2_MS },
261 Vector { _handler: I2C2_SL },
262 Vector { _handler: Ethernet },
263 Vector { _handler: U37 },
264 Vector { _handler: SpW },
265 Vector { _handler: U39 },
266 Vector { _handler: DAC0 },
267 Vector { _handler: DAC1 },
268 Vector { _handler: TRNG },
269 Vector {
270 _handler: DMA_ERROR,
271 },
272 Vector { _handler: ADC },
273 Vector { _handler: LoCLK },
274 Vector { _handler: LVD },
275 Vector { _handler: WATCHDOG },
276 Vector { _handler: TIM0 },
277 Vector { _handler: TIM1 },
278 Vector { _handler: TIM2 },
279 Vector { _handler: TIM3 },
280 Vector { _handler: TIM4 },
281 Vector { _handler: TIM5 },
282 Vector { _handler: TIM6 },
283 Vector { _handler: TIM7 },
284 Vector { _handler: TIM8 },
285 Vector { _handler: TIM9 },
286 Vector { _handler: TIM10 },
287 Vector { _handler: TIM11 },
288 Vector { _handler: TIM12 },
289 Vector { _handler: TIM13 },
290 Vector { _handler: TIM14 },
291 Vector { _handler: TIM15 },
292 Vector { _handler: TIM16 },
293 Vector { _handler: TIM17 },
294 Vector { _handler: TIM18 },
295 Vector { _handler: TIM19 },
296 Vector { _handler: TIM20 },
297 Vector { _handler: TIM21 },
298 Vector { _handler: TIM22 },
299 Vector { _handler: TIM23 },
300 Vector { _handler: CAN0 },
301 Vector { _handler: U73 },
302 Vector { _handler: CAN1 },
303 Vector { _handler: U75 },
304 Vector { _handler: EDAC_MBE },
305 Vector { _handler: EDAC_SBE },
306 Vector { _handler: PORTA0 },
307 Vector { _handler: PORTA1 },
308 Vector { _handler: PORTA2 },
309 Vector { _handler: PORTA3 },
310 Vector { _handler: PORTA4 },
311 Vector { _handler: PORTA5 },
312 Vector { _handler: PORTA6 },
313 Vector { _handler: PORTA7 },
314 Vector { _handler: PORTA8 },
315 Vector { _handler: PORTA9 },
316 Vector { _handler: PORTA10 },
317 Vector { _handler: PORTA11 },
318 Vector { _handler: PORTA12 },
319 Vector { _handler: PORTA13 },
320 Vector { _handler: PORTA14 },
321 Vector { _handler: PORTA15 },
322 Vector { _handler: PORTB0 },
323 Vector { _handler: PORTB1 },
324 Vector { _handler: PORTB2 },
325 Vector { _handler: PORTB3 },
326 Vector { _handler: PORTB4 },
327 Vector { _handler: PORTB5 },
328 Vector { _handler: PORTB6 },
329 Vector { _handler: PORTB7 },
330 Vector { _handler: PORTB8 },
331 Vector { _handler: PORTB9 },
332 Vector { _handler: PORTB10 },
333 Vector { _handler: PORTB11 },
334 Vector { _handler: PORTB12 },
335 Vector { _handler: PORTB13 },
336 Vector { _handler: PORTB14 },
337 Vector { _handler: PORTB15 },
338 Vector { _handler: PORTC0 },
339 Vector { _handler: PORTC1 },
340 Vector { _handler: PORTC2 },
341 Vector { _handler: PORTC3 },
342 Vector { _handler: PORTC4 },
343 Vector { _handler: PORTC5 },
344 Vector { _handler: PORTC6 },
345 Vector { _handler: PORTC7 },
346 Vector { _handler: PORTC8 },
347 Vector { _handler: PORTC9 },
348 Vector { _handler: PORTC10 },
349 Vector { _handler: PORTC11 },
350 Vector { _handler: PORTC12 },
351 Vector { _handler: PORTC13 },
352 Vector { _handler: PORTC14 },
353 Vector { _handler: PORTC15 },
354 Vector { _handler: PORTD0 },
355 Vector { _handler: PORTD1 },
356 Vector { _handler: PORTD2 },
357 Vector { _handler: PORTD3 },
358 Vector { _handler: PORTD4 },
359 Vector { _handler: PORTD5 },
360 Vector { _handler: PORTD6 },
361 Vector { _handler: PORTD7 },
362 Vector { _handler: PORTD8 },
363 Vector { _handler: PORTD9 },
364 Vector { _handler: PORTD10 },
365 Vector { _handler: PORTD11 },
366 Vector { _handler: PORTD12 },
367 Vector { _handler: PORTD13 },
368 Vector { _handler: PORTD14 },
369 Vector { _handler: PORTD15 },
370 Vector { _handler: PORTE0 },
371 Vector { _handler: PORTE1 },
372 Vector { _handler: PORTE2 },
373 Vector { _handler: PORTE3 },
374 Vector { _handler: PORTE4 },
375 Vector { _handler: PORTE5 },
376 Vector { _handler: PORTE6 },
377 Vector { _handler: PORTE7 },
378 Vector { _handler: PORTE8 },
379 Vector { _handler: PORTE9 },
380 Vector { _handler: PORTE10 },
381 Vector { _handler: PORTE11 },
382 Vector { _handler: PORTE12 },
383 Vector { _handler: PORTE13 },
384 Vector { _handler: PORTE14 },
385 Vector { _handler: PORTE15 },
386 Vector { _handler: PORTF0 },
387 Vector { _handler: PORTF1 },
388 Vector { _handler: PORTF2 },
389 Vector { _handler: PORTF3 },
390 Vector { _handler: PORTF4 },
391 Vector { _handler: PORTF5 },
392 Vector { _handler: PORTF6 },
393 Vector { _handler: PORTF7 },
394 Vector { _handler: PORTF8 },
395 Vector { _handler: PORTF9 },
396 Vector { _handler: PORTF10 },
397 Vector { _handler: PORTF11 },
398 Vector { _handler: PORTF12 },
399 Vector { _handler: PORTF13 },
400 Vector { _handler: PORTF14 },
401 Vector { _handler: PORTF15 },
402 Vector {
403 _handler: DMA_ACTIVE0,
404 },
405 Vector {
406 _handler: DMA_ACTIVE1,
407 },
408 Vector {
409 _handler: DMA_ACTIVE2,
410 },
411 Vector {
412 _handler: DMA_ACTIVE3,
413 },
414 Vector {
415 _handler: DMA_DONE0,
416 },
417 Vector {
418 _handler: DMA_DONE1,
419 },
420 Vector {
421 _handler: DMA_DONE2,
422 },
423 Vector {
424 _handler: DMA_DONE3,
425 },
426 Vector {
427 _handler: I2C0_MS_RX,
428 },
429 Vector {
430 _handler: I2C0_MS_TX,
431 },
432 Vector {
433 _handler: I2C0_SL_RX,
434 },
435 Vector {
436 _handler: I2C0_SL_TX,
437 },
438 Vector {
439 _handler: I2C1_MS_RX,
440 },
441 Vector {
442 _handler: I2C1_MS_TX,
443 },
444 Vector {
445 _handler: I2C1_SL_RX,
446 },
447 Vector {
448 _handler: I2C1_SL_TX,
449 },
450 Vector {
451 _handler: I2C2_MS_RX,
452 },
453 Vector {
454 _handler: I2C2_MS_TX,
455 },
456 Vector {
457 _handler: I2C2_SL_RX,
458 },
459 Vector {
460 _handler: I2C2_SL_TX,
461 },
462 Vector { _handler: FPU },
463 Vector { _handler: TXEV },
464];
465#[doc = r"Enumeration of all the interrupts."]
466#[cfg_attr(feature = "defmt", derive(defmt::Format))]
467#[derive(Copy, Clone, Debug, PartialEq, Eq)]
468#[repr(u16)]
469pub enum Interrupt {
470 #[doc = "0 - U0"]
471 U0 = 0,
472 #[doc = "1 - U1"]
473 U1 = 1,
474 #[doc = "2 - U2"]
475 U2 = 2,
476 #[doc = "3 - U3"]
477 U3 = 3,
478 #[doc = "4 - U4"]
479 U4 = 4,
480 #[doc = "5 - U5"]
481 U5 = 5,
482 #[doc = "6 - U6"]
483 U6 = 6,
484 #[doc = "7 - U7"]
485 U7 = 7,
486 #[doc = "8 - U8"]
487 U8 = 8,
488 #[doc = "9 - U9"]
489 U9 = 9,
490 #[doc = "10 - U10"]
491 U10 = 10,
492 #[doc = "11 - U11"]
493 U11 = 11,
494 #[doc = "12 - U12"]
495 U12 = 12,
496 #[doc = "13 - U13"]
497 U13 = 13,
498 #[doc = "14 - U14"]
499 U14 = 14,
500 #[doc = "15 - U15"]
501 U15 = 15,
502 #[doc = "16 - SPI0_TX"]
503 SPI0_TX = 16,
504 #[doc = "17 - SPI0_RX"]
505 SPI0_RX = 17,
506 #[doc = "18 - SPI1_TX"]
507 SPI1_TX = 18,
508 #[doc = "19 - SPI1_RX"]
509 SPI1_RX = 19,
510 #[doc = "20 - SPI2_TX"]
511 SPI2_TX = 20,
512 #[doc = "21 - SPI2_RX"]
513 SPI2_RX = 21,
514 #[doc = "22 - SPI3_TX"]
515 SPI3_TX = 22,
516 #[doc = "23 - SPI3_RX"]
517 SPI3_RX = 23,
518 #[doc = "24 - UART0_TX"]
519 UART0_TX = 24,
520 #[doc = "25 - UART0_RX"]
521 UART0_RX = 25,
522 #[doc = "26 - UART1_TX"]
523 UART1_TX = 26,
524 #[doc = "27 - UART1_RX"]
525 UART1_RX = 27,
526 #[doc = "28 - UART2_TX"]
527 UART2_TX = 28,
528 #[doc = "29 - UART2_RX"]
529 UART2_RX = 29,
530 #[doc = "30 - I2C0_MS"]
531 I2C0_MS = 30,
532 #[doc = "31 - I2C0_SL"]
533 I2C0_SL = 31,
534 #[doc = "32 - I2C1_MS"]
535 I2C1_MS = 32,
536 #[doc = "33 - I2C1_SL"]
537 I2C1_SL = 33,
538 #[doc = "34 - I2C2_MS"]
539 I2C2_MS = 34,
540 #[doc = "35 - I2C2_SL"]
541 I2C2_SL = 35,
542 #[doc = "36 - Ethernet"]
543 Ethernet = 36,
544 #[doc = "37 - U37"]
545 U37 = 37,
546 #[doc = "38 - SpW"]
547 SpW = 38,
548 #[doc = "39 - U39"]
549 U39 = 39,
550 #[doc = "40 - DAC0"]
551 DAC0 = 40,
552 #[doc = "41 - DAC1"]
553 DAC1 = 41,
554 #[doc = "42 - TRNG"]
555 TRNG = 42,
556 #[doc = "43 - DMA_ERROR"]
557 DMA_ERROR = 43,
558 #[doc = "44 - ADC"]
559 ADC = 44,
560 #[doc = "45 - LoCLK"]
561 LoCLK = 45,
562 #[doc = "46 - LVD"]
563 LVD = 46,
564 #[doc = "47 - WATCHDOG"]
565 WATCHDOG = 47,
566 #[doc = "48 - TIM0"]
567 TIM0 = 48,
568 #[doc = "49 - TIM1"]
569 TIM1 = 49,
570 #[doc = "50 - TIM2"]
571 TIM2 = 50,
572 #[doc = "51 - TIM3"]
573 TIM3 = 51,
574 #[doc = "52 - TIM4"]
575 TIM4 = 52,
576 #[doc = "53 - TIM5"]
577 TIM5 = 53,
578 #[doc = "54 - TIM6"]
579 TIM6 = 54,
580 #[doc = "55 - TIM7"]
581 TIM7 = 55,
582 #[doc = "56 - TIM8"]
583 TIM8 = 56,
584 #[doc = "57 - TIM9"]
585 TIM9 = 57,
586 #[doc = "58 - TIM10"]
587 TIM10 = 58,
588 #[doc = "59 - TIM11"]
589 TIM11 = 59,
590 #[doc = "60 - TIM12"]
591 TIM12 = 60,
592 #[doc = "61 - TIM13"]
593 TIM13 = 61,
594 #[doc = "62 - TIM14"]
595 TIM14 = 62,
596 #[doc = "63 - TIM15"]
597 TIM15 = 63,
598 #[doc = "64 - TIM16"]
599 TIM16 = 64,
600 #[doc = "65 - TIM17"]
601 TIM17 = 65,
602 #[doc = "66 - TIM18"]
603 TIM18 = 66,
604 #[doc = "67 - TIM19"]
605 TIM19 = 67,
606 #[doc = "68 - TIM20"]
607 TIM20 = 68,
608 #[doc = "69 - TIM21"]
609 TIM21 = 69,
610 #[doc = "70 - TIM22"]
611 TIM22 = 70,
612 #[doc = "71 - TIM23"]
613 TIM23 = 71,
614 #[doc = "72 - CAN0"]
615 CAN0 = 72,
616 #[doc = "73 - U73"]
617 U73 = 73,
618 #[doc = "74 - CAN1"]
619 CAN1 = 74,
620 #[doc = "75 - U75"]
621 U75 = 75,
622 #[doc = "76 - EDAC_MBE"]
623 EDAC_MBE = 76,
624 #[doc = "77 - EDAC_SBE"]
625 EDAC_SBE = 77,
626 #[doc = "78 - PORTA0"]
627 PORTA0 = 78,
628 #[doc = "79 - PORTA1"]
629 PORTA1 = 79,
630 #[doc = "80 - PORTA2"]
631 PORTA2 = 80,
632 #[doc = "81 - PORTA3"]
633 PORTA3 = 81,
634 #[doc = "82 - PORTA4"]
635 PORTA4 = 82,
636 #[doc = "83 - PORTA5"]
637 PORTA5 = 83,
638 #[doc = "84 - PORTA6"]
639 PORTA6 = 84,
640 #[doc = "85 - PORTA7"]
641 PORTA7 = 85,
642 #[doc = "86 - PORTA8"]
643 PORTA8 = 86,
644 #[doc = "87 - PORTA9"]
645 PORTA9 = 87,
646 #[doc = "88 - PORTA10"]
647 PORTA10 = 88,
648 #[doc = "89 - PORTA11"]
649 PORTA11 = 89,
650 #[doc = "90 - PORTA12"]
651 PORTA12 = 90,
652 #[doc = "91 - PORTA13"]
653 PORTA13 = 91,
654 #[doc = "92 - PORTA14"]
655 PORTA14 = 92,
656 #[doc = "93 - PORTA15"]
657 PORTA15 = 93,
658 #[doc = "94 - PORTB0"]
659 PORTB0 = 94,
660 #[doc = "95 - PORTB1"]
661 PORTB1 = 95,
662 #[doc = "96 - PORTB2"]
663 PORTB2 = 96,
664 #[doc = "97 - PORTB3"]
665 PORTB3 = 97,
666 #[doc = "98 - PORTB4"]
667 PORTB4 = 98,
668 #[doc = "99 - PORTB5"]
669 PORTB5 = 99,
670 #[doc = "100 - PORTB6"]
671 PORTB6 = 100,
672 #[doc = "101 - PORTB7"]
673 PORTB7 = 101,
674 #[doc = "102 - PORTB8"]
675 PORTB8 = 102,
676 #[doc = "103 - PORTB9"]
677 PORTB9 = 103,
678 #[doc = "104 - PORTB10"]
679 PORTB10 = 104,
680 #[doc = "105 - PORTB11"]
681 PORTB11 = 105,
682 #[doc = "106 - PORTB12"]
683 PORTB12 = 106,
684 #[doc = "107 - PORTB13"]
685 PORTB13 = 107,
686 #[doc = "108 - PORTB14"]
687 PORTB14 = 108,
688 #[doc = "109 - PORTB15"]
689 PORTB15 = 109,
690 #[doc = "110 - PORTC0"]
691 PORTC0 = 110,
692 #[doc = "111 - PORTC1"]
693 PORTC1 = 111,
694 #[doc = "112 - PORTC2"]
695 PORTC2 = 112,
696 #[doc = "113 - PORTC3"]
697 PORTC3 = 113,
698 #[doc = "114 - PORTC4"]
699 PORTC4 = 114,
700 #[doc = "115 - PORTC5"]
701 PORTC5 = 115,
702 #[doc = "116 - PORTC6"]
703 PORTC6 = 116,
704 #[doc = "117 - PORTC7"]
705 PORTC7 = 117,
706 #[doc = "118 - PORTC8"]
707 PORTC8 = 118,
708 #[doc = "119 - PORTC9"]
709 PORTC9 = 119,
710 #[doc = "120 - PORTC10"]
711 PORTC10 = 120,
712 #[doc = "121 - PORTC11"]
713 PORTC11 = 121,
714 #[doc = "122 - PORTC12"]
715 PORTC12 = 122,
716 #[doc = "123 - PORTC13"]
717 PORTC13 = 123,
718 #[doc = "124 - PORTC14"]
719 PORTC14 = 124,
720 #[doc = "125 - PORTC15"]
721 PORTC15 = 125,
722 #[doc = "126 - PORTD0"]
723 PORTD0 = 126,
724 #[doc = "127 - PORTD1"]
725 PORTD1 = 127,
726 #[doc = "128 - PORTD2"]
727 PORTD2 = 128,
728 #[doc = "129 - PORTD3"]
729 PORTD3 = 129,
730 #[doc = "130 - PORTD4"]
731 PORTD4 = 130,
732 #[doc = "131 - PORTD5"]
733 PORTD5 = 131,
734 #[doc = "132 - PORTD6"]
735 PORTD6 = 132,
736 #[doc = "133 - PORTD7"]
737 PORTD7 = 133,
738 #[doc = "134 - PORTD8"]
739 PORTD8 = 134,
740 #[doc = "135 - PORTD9"]
741 PORTD9 = 135,
742 #[doc = "136 - PORTD10"]
743 PORTD10 = 136,
744 #[doc = "137 - PORTD11"]
745 PORTD11 = 137,
746 #[doc = "138 - PORTD12"]
747 PORTD12 = 138,
748 #[doc = "139 - PORTD13"]
749 PORTD13 = 139,
750 #[doc = "140 - PORTD14"]
751 PORTD14 = 140,
752 #[doc = "141 - PORTD15"]
753 PORTD15 = 141,
754 #[doc = "142 - PORTE0"]
755 PORTE0 = 142,
756 #[doc = "143 - PORTE1"]
757 PORTE1 = 143,
758 #[doc = "144 - PORTE2"]
759 PORTE2 = 144,
760 #[doc = "145 - PORTE3"]
761 PORTE3 = 145,
762 #[doc = "146 - PORTE4"]
763 PORTE4 = 146,
764 #[doc = "147 - PORTE5"]
765 PORTE5 = 147,
766 #[doc = "148 - PORTE6"]
767 PORTE6 = 148,
768 #[doc = "149 - PORTE7"]
769 PORTE7 = 149,
770 #[doc = "150 - PORTE8"]
771 PORTE8 = 150,
772 #[doc = "151 - PORTE9"]
773 PORTE9 = 151,
774 #[doc = "152 - PORTE10"]
775 PORTE10 = 152,
776 #[doc = "153 - PORTE11"]
777 PORTE11 = 153,
778 #[doc = "154 - PORTE12"]
779 PORTE12 = 154,
780 #[doc = "155 - PORTE13"]
781 PORTE13 = 155,
782 #[doc = "156 - PORTE14"]
783 PORTE14 = 156,
784 #[doc = "157 - PORTE15"]
785 PORTE15 = 157,
786 #[doc = "158 - PORTF0"]
787 PORTF0 = 158,
788 #[doc = "159 - PORTF1"]
789 PORTF1 = 159,
790 #[doc = "160 - PORTF2"]
791 PORTF2 = 160,
792 #[doc = "161 - PORTF3"]
793 PORTF3 = 161,
794 #[doc = "162 - PORTF4"]
795 PORTF4 = 162,
796 #[doc = "163 - PORTF5"]
797 PORTF5 = 163,
798 #[doc = "164 - PORTF6"]
799 PORTF6 = 164,
800 #[doc = "165 - PORTF7"]
801 PORTF7 = 165,
802 #[doc = "166 - PORTF8"]
803 PORTF8 = 166,
804 #[doc = "167 - PORTF9"]
805 PORTF9 = 167,
806 #[doc = "168 - PORTF10"]
807 PORTF10 = 168,
808 #[doc = "169 - PORTF11"]
809 PORTF11 = 169,
810 #[doc = "170 - PORTF12"]
811 PORTF12 = 170,
812 #[doc = "171 - PORTF13"]
813 PORTF13 = 171,
814 #[doc = "172 - PORTF14"]
815 PORTF14 = 172,
816 #[doc = "173 - PORTF15"]
817 PORTF15 = 173,
818 #[doc = "174 - DMA_ACTIVE0"]
819 DMA_ACTIVE0 = 174,
820 #[doc = "175 - DMA_ACTIVE1"]
821 DMA_ACTIVE1 = 175,
822 #[doc = "176 - DMA_ACTIVE2"]
823 DMA_ACTIVE2 = 176,
824 #[doc = "177 - DMA_ACTIVE3"]
825 DMA_ACTIVE3 = 177,
826 #[doc = "178 - DMA_DONE0"]
827 DMA_DONE0 = 178,
828 #[doc = "179 - DMA_DONE1"]
829 DMA_DONE1 = 179,
830 #[doc = "180 - DMA_DONE2"]
831 DMA_DONE2 = 180,
832 #[doc = "181 - DMA_DONE3"]
833 DMA_DONE3 = 181,
834 #[doc = "182 - I2C0_MS_RX"]
835 I2C0_MS_RX = 182,
836 #[doc = "183 - I2C0_MS_TX"]
837 I2C0_MS_TX = 183,
838 #[doc = "184 - I2C0_SL_RX"]
839 I2C0_SL_RX = 184,
840 #[doc = "185 - I2C0_SL_TX"]
841 I2C0_SL_TX = 185,
842 #[doc = "186 - I2C1_MS_RX"]
843 I2C1_MS_RX = 186,
844 #[doc = "187 - I2C1_MS_TX"]
845 I2C1_MS_TX = 187,
846 #[doc = "188 - I2C1_SL_RX"]
847 I2C1_SL_RX = 188,
848 #[doc = "189 - I2C1_SL_TX"]
849 I2C1_SL_TX = 189,
850 #[doc = "190 - I2C2_MS_RX"]
851 I2C2_MS_RX = 190,
852 #[doc = "191 - I2C2_MS_TX"]
853 I2C2_MS_TX = 191,
854 #[doc = "192 - I2C2_SL_RX"]
855 I2C2_SL_RX = 192,
856 #[doc = "193 - I2C2_SL_TX"]
857 I2C2_SL_TX = 193,
858 #[doc = "194 - FPU"]
859 FPU = 194,
860 #[doc = "195 - TXEV"]
861 TXEV = 195,
862}
863unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
864 #[inline(always)]
865 fn number(self) -> u16 {
866 self as u16
867 }
868}
869#[doc = "Clock Generation Peripheral"]
870pub type Clkgen = crate::Periph<clkgen::RegisterBlock, 0x4000_6000>;
871impl core::fmt::Debug for Clkgen {
872 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
873 f.debug_struct("Clkgen").finish()
874 }
875}
876#[doc = "Clock Generation Peripheral"]
877pub mod clkgen;
878#[doc = "System Configuration Peripheral"]
879pub type Sysconfig = crate::Periph<sysconfig::RegisterBlock, 0x4001_0000>;
880impl core::fmt::Debug for Sysconfig {
881 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
882 f.debug_struct("Sysconfig").finish()
883 }
884}
885#[doc = "System Configuration Peripheral"]
886pub mod sysconfig;
887#[doc = "DMA Controller Block"]
888pub type Dma = crate::Periph<dma::RegisterBlock, 0x4000_1000>;
889impl core::fmt::Debug for Dma {
890 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
891 f.debug_struct("Dma").finish()
892 }
893}
894#[doc = "DMA Controller Block"]
895pub mod dma;
896#[doc = "IO Pin Configuration Peripheral"]
897pub type Ioconfig = crate::Periph<ioconfig::RegisterBlock, 0x4001_1000>;
898impl core::fmt::Debug for Ioconfig {
899 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
900 f.debug_struct("Ioconfig").finish()
901 }
902}
903#[doc = "IO Pin Configuration Peripheral"]
904pub mod ioconfig;
905#[doc = "Utility Peripheral"]
906pub type Utility = crate::Periph<utility::RegisterBlock, 0x4002_0000>;
907impl core::fmt::Debug for Utility {
908 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
909 f.debug_struct("Utility").finish()
910 }
911}
912#[doc = "Utility Peripheral"]
913pub mod utility;
914#[doc = "GPIO Peripheral"]
915pub type Porta = crate::Periph<porta::RegisterBlock, 0x4001_2000>;
916impl core::fmt::Debug for Porta {
917 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
918 f.debug_struct("Porta").finish()
919 }
920}
921#[doc = "GPIO Peripheral"]
922pub mod porta;
923#[doc = "GPIO Peripheral"]
924pub type Portb = crate::Periph<porta::RegisterBlock, 0x4001_2400>;
925impl core::fmt::Debug for Portb {
926 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
927 f.debug_struct("Portb").finish()
928 }
929}
930#[doc = "GPIO Peripheral"]
931pub use self::porta as portb;
932#[doc = "GPIO Peripheral"]
933pub type Portc = crate::Periph<porta::RegisterBlock, 0x4001_2800>;
934impl core::fmt::Debug for Portc {
935 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
936 f.debug_struct("Portc").finish()
937 }
938}
939#[doc = "GPIO Peripheral"]
940pub use self::porta as portc;
941#[doc = "GPIO Peripheral"]
942pub type Portd = crate::Periph<porta::RegisterBlock, 0x4001_2c00>;
943impl core::fmt::Debug for Portd {
944 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
945 f.debug_struct("Portd").finish()
946 }
947}
948#[doc = "GPIO Peripheral"]
949pub use self::porta as portd;
950#[doc = "GPIO Peripheral"]
951pub type Porte = crate::Periph<porta::RegisterBlock, 0x4001_3000>;
952impl core::fmt::Debug for Porte {
953 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
954 f.debug_struct("Porte").finish()
955 }
956}
957#[doc = "GPIO Peripheral"]
958pub use self::porta as porte;
959#[doc = "GPIO Peripheral"]
960pub type Portf = crate::Periph<porta::RegisterBlock, 0x4001_3400>;
961impl core::fmt::Debug for Portf {
962 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
963 f.debug_struct("Portf").finish()
964 }
965}
966#[doc = "GPIO Peripheral"]
967pub use self::porta as portf;
968#[doc = "GPIO Peripheral"]
969pub type Portg = crate::Periph<porta::RegisterBlock, 0x4001_3800>;
970impl core::fmt::Debug for Portg {
971 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
972 f.debug_struct("Portg").finish()
973 }
974}
975#[doc = "GPIO Peripheral"]
976pub use self::porta as portg;
977#[doc = "Timer/Counter Peripheral"]
978pub type Tim0 = crate::Periph<tim0::RegisterBlock, 0x4001_8000>;
979impl core::fmt::Debug for Tim0 {
980 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
981 f.debug_struct("Tim0").finish()
982 }
983}
984#[doc = "Timer/Counter Peripheral"]
985pub mod tim0;
986#[doc = "Timer/Counter Peripheral"]
987pub type Tim1 = crate::Periph<tim0::RegisterBlock, 0x4001_8400>;
988impl core::fmt::Debug for Tim1 {
989 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
990 f.debug_struct("Tim1").finish()
991 }
992}
993#[doc = "Timer/Counter Peripheral"]
994pub use self::tim0 as tim1;
995#[doc = "Timer/Counter Peripheral"]
996pub type Tim2 = crate::Periph<tim0::RegisterBlock, 0x4001_8800>;
997impl core::fmt::Debug for Tim2 {
998 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
999 f.debug_struct("Tim2").finish()
1000 }
1001}
1002#[doc = "Timer/Counter Peripheral"]
1003pub use self::tim0 as tim2;
1004#[doc = "Timer/Counter Peripheral"]
1005pub type Tim3 = crate::Periph<tim0::RegisterBlock, 0x4001_8c00>;
1006impl core::fmt::Debug for Tim3 {
1007 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1008 f.debug_struct("Tim3").finish()
1009 }
1010}
1011#[doc = "Timer/Counter Peripheral"]
1012pub use self::tim0 as tim3;
1013#[doc = "Timer/Counter Peripheral"]
1014pub type Tim4 = crate::Periph<tim0::RegisterBlock, 0x4001_9000>;
1015impl core::fmt::Debug for Tim4 {
1016 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1017 f.debug_struct("Tim4").finish()
1018 }
1019}
1020#[doc = "Timer/Counter Peripheral"]
1021pub use self::tim0 as tim4;
1022#[doc = "Timer/Counter Peripheral"]
1023pub type Tim5 = crate::Periph<tim0::RegisterBlock, 0x4001_9400>;
1024impl core::fmt::Debug for Tim5 {
1025 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1026 f.debug_struct("Tim5").finish()
1027 }
1028}
1029#[doc = "Timer/Counter Peripheral"]
1030pub use self::tim0 as tim5;
1031#[doc = "Timer/Counter Peripheral"]
1032pub type Tim6 = crate::Periph<tim0::RegisterBlock, 0x4001_9800>;
1033impl core::fmt::Debug for Tim6 {
1034 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1035 f.debug_struct("Tim6").finish()
1036 }
1037}
1038#[doc = "Timer/Counter Peripheral"]
1039pub use self::tim0 as tim6;
1040#[doc = "Timer/Counter Peripheral"]
1041pub type Tim7 = crate::Periph<tim0::RegisterBlock, 0x4001_9c00>;
1042impl core::fmt::Debug for Tim7 {
1043 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1044 f.debug_struct("Tim7").finish()
1045 }
1046}
1047#[doc = "Timer/Counter Peripheral"]
1048pub use self::tim0 as tim7;
1049#[doc = "Timer/Counter Peripheral"]
1050pub type Tim8 = crate::Periph<tim0::RegisterBlock, 0x4001_a000>;
1051impl core::fmt::Debug for Tim8 {
1052 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1053 f.debug_struct("Tim8").finish()
1054 }
1055}
1056#[doc = "Timer/Counter Peripheral"]
1057pub use self::tim0 as tim8;
1058#[doc = "Timer/Counter Peripheral"]
1059pub type Tim9 = crate::Periph<tim0::RegisterBlock, 0x4001_a400>;
1060impl core::fmt::Debug for Tim9 {
1061 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1062 f.debug_struct("Tim9").finish()
1063 }
1064}
1065#[doc = "Timer/Counter Peripheral"]
1066pub use self::tim0 as tim9;
1067#[doc = "Timer/Counter Peripheral"]
1068pub type Tim10 = crate::Periph<tim0::RegisterBlock, 0x4001_a800>;
1069impl core::fmt::Debug for Tim10 {
1070 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1071 f.debug_struct("Tim10").finish()
1072 }
1073}
1074#[doc = "Timer/Counter Peripheral"]
1075pub use self::tim0 as tim10;
1076#[doc = "Timer/Counter Peripheral"]
1077pub type Tim11 = crate::Periph<tim0::RegisterBlock, 0x4001_ac00>;
1078impl core::fmt::Debug for Tim11 {
1079 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1080 f.debug_struct("Tim11").finish()
1081 }
1082}
1083#[doc = "Timer/Counter Peripheral"]
1084pub use self::tim0 as tim11;
1085#[doc = "Timer/Counter Peripheral"]
1086pub type Tim12 = crate::Periph<tim0::RegisterBlock, 0x4001_b000>;
1087impl core::fmt::Debug for Tim12 {
1088 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1089 f.debug_struct("Tim12").finish()
1090 }
1091}
1092#[doc = "Timer/Counter Peripheral"]
1093pub use self::tim0 as tim12;
1094#[doc = "Timer/Counter Peripheral"]
1095pub type Tim13 = crate::Periph<tim0::RegisterBlock, 0x4001_b400>;
1096impl core::fmt::Debug for Tim13 {
1097 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1098 f.debug_struct("Tim13").finish()
1099 }
1100}
1101#[doc = "Timer/Counter Peripheral"]
1102pub use self::tim0 as tim13;
1103#[doc = "Timer/Counter Peripheral"]
1104pub type Tim14 = crate::Periph<tim0::RegisterBlock, 0x4001_b800>;
1105impl core::fmt::Debug for Tim14 {
1106 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1107 f.debug_struct("Tim14").finish()
1108 }
1109}
1110#[doc = "Timer/Counter Peripheral"]
1111pub use self::tim0 as tim14;
1112#[doc = "Timer/Counter Peripheral"]
1113pub type Tim15 = crate::Periph<tim0::RegisterBlock, 0x4001_bc00>;
1114impl core::fmt::Debug for Tim15 {
1115 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1116 f.debug_struct("Tim15").finish()
1117 }
1118}
1119#[doc = "Timer/Counter Peripheral"]
1120pub use self::tim0 as tim15;
1121#[doc = "Timer/Counter Peripheral"]
1122pub type Tim16 = crate::Periph<tim0::RegisterBlock, 0x4002_8000>;
1123impl core::fmt::Debug for Tim16 {
1124 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1125 f.debug_struct("Tim16").finish()
1126 }
1127}
1128#[doc = "Timer/Counter Peripheral"]
1129pub use self::tim0 as tim16;
1130#[doc = "Timer/Counter Peripheral"]
1131pub type Tim17 = crate::Periph<tim0::RegisterBlock, 0x4002_8400>;
1132impl core::fmt::Debug for Tim17 {
1133 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1134 f.debug_struct("Tim17").finish()
1135 }
1136}
1137#[doc = "Timer/Counter Peripheral"]
1138pub use self::tim0 as tim17;
1139#[doc = "Timer/Counter Peripheral"]
1140pub type Tim18 = crate::Periph<tim0::RegisterBlock, 0x4002_8800>;
1141impl core::fmt::Debug for Tim18 {
1142 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1143 f.debug_struct("Tim18").finish()
1144 }
1145}
1146#[doc = "Timer/Counter Peripheral"]
1147pub use self::tim0 as tim18;
1148#[doc = "Timer/Counter Peripheral"]
1149pub type Tim19 = crate::Periph<tim0::RegisterBlock, 0x4002_8c00>;
1150impl core::fmt::Debug for Tim19 {
1151 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1152 f.debug_struct("Tim19").finish()
1153 }
1154}
1155#[doc = "Timer/Counter Peripheral"]
1156pub use self::tim0 as tim19;
1157#[doc = "Timer/Counter Peripheral"]
1158pub type Tim20 = crate::Periph<tim0::RegisterBlock, 0x4002_9000>;
1159impl core::fmt::Debug for Tim20 {
1160 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1161 f.debug_struct("Tim20").finish()
1162 }
1163}
1164#[doc = "Timer/Counter Peripheral"]
1165pub use self::tim0 as tim20;
1166#[doc = "Timer/Counter Peripheral"]
1167pub type Tim21 = crate::Periph<tim0::RegisterBlock, 0x4002_9400>;
1168impl core::fmt::Debug for Tim21 {
1169 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1170 f.debug_struct("Tim21").finish()
1171 }
1172}
1173#[doc = "Timer/Counter Peripheral"]
1174pub use self::tim0 as tim21;
1175#[doc = "Timer/Counter Peripheral"]
1176pub type Tim22 = crate::Periph<tim0::RegisterBlock, 0x4002_9800>;
1177impl core::fmt::Debug for Tim22 {
1178 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1179 f.debug_struct("Tim22").finish()
1180 }
1181}
1182#[doc = "Timer/Counter Peripheral"]
1183pub use self::tim0 as tim22;
1184#[doc = "Timer/Counter Peripheral"]
1185pub type Tim23 = crate::Periph<tim0::RegisterBlock, 0x4002_9c00>;
1186impl core::fmt::Debug for Tim23 {
1187 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1188 f.debug_struct("Tim23").finish()
1189 }
1190}
1191#[doc = "Timer/Counter Peripheral"]
1192pub use self::tim0 as tim23;
1193#[doc = "UART Peripheral"]
1194pub type Uart0 = crate::Periph<uart0::RegisterBlock, 0x4002_4000>;
1195impl core::fmt::Debug for Uart0 {
1196 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1197 f.debug_struct("Uart0").finish()
1198 }
1199}
1200#[doc = "UART Peripheral"]
1201pub mod uart0;
1202#[doc = "UART Peripheral"]
1203pub type Uart1 = crate::Periph<uart0::RegisterBlock, 0x4002_5000>;
1204impl core::fmt::Debug for Uart1 {
1205 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1206 f.debug_struct("Uart1").finish()
1207 }
1208}
1209#[doc = "UART Peripheral"]
1210pub use self::uart0 as uart1;
1211#[doc = "UART Peripheral"]
1212pub type Uart2 = crate::Periph<uart0::RegisterBlock, 0x4001_7000>;
1213impl core::fmt::Debug for Uart2 {
1214 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1215 f.debug_struct("Uart2").finish()
1216 }
1217}
1218#[doc = "UART Peripheral"]
1219pub use self::uart0 as uart2;
1220#[doc = "SPI Peripheral"]
1221pub type Spi0 = crate::Periph<spi0::RegisterBlock, 0x4001_5000>;
1222impl core::fmt::Debug for Spi0 {
1223 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1224 f.debug_struct("Spi0").finish()
1225 }
1226}
1227#[doc = "SPI Peripheral"]
1228pub mod spi0;
1229#[doc = "SPI Peripheral"]
1230pub type Spi1 = crate::Periph<spi0::RegisterBlock, 0x4001_5400>;
1231impl core::fmt::Debug for Spi1 {
1232 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1233 f.debug_struct("Spi1").finish()
1234 }
1235}
1236#[doc = "SPI Peripheral"]
1237pub use self::spi0 as spi1;
1238#[doc = "SPI Peripheral"]
1239pub type Spi2 = crate::Periph<spi0::RegisterBlock, 0x4001_5800>;
1240impl core::fmt::Debug for Spi2 {
1241 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1242 f.debug_struct("Spi2").finish()
1243 }
1244}
1245#[doc = "SPI Peripheral"]
1246pub use self::spi0 as spi2;
1247#[doc = "SPI Peripheral"]
1248pub type Spi3 = crate::Periph<spi0::RegisterBlock, 0x4001_5c00>;
1249impl core::fmt::Debug for Spi3 {
1250 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1251 f.debug_struct("Spi3").finish()
1252 }
1253}
1254#[doc = "SPI Peripheral"]
1255pub use self::spi0 as spi3;
1256#[doc = "I2C Peripheral"]
1257pub type I2c0 = crate::Periph<i2c0::RegisterBlock, 0x4001_6000>;
1258impl core::fmt::Debug for I2c0 {
1259 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1260 f.debug_struct("I2c0").finish()
1261 }
1262}
1263#[doc = "I2C Peripheral"]
1264pub mod i2c0;
1265#[doc = "I2C Peripheral"]
1266pub type I2c1 = crate::Periph<i2c0::RegisterBlock, 0x4001_6400>;
1267impl core::fmt::Debug for I2c1 {
1268 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1269 f.debug_struct("I2c1").finish()
1270 }
1271}
1272#[doc = "I2C Peripheral"]
1273pub use self::i2c0 as i2c1;
1274#[doc = "I2C Peripheral"]
1275pub type I2c2 = crate::Periph<i2c0::RegisterBlock, 0x4001_6800>;
1276impl core::fmt::Debug for I2c2 {
1277 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1278 f.debug_struct("I2c2").finish()
1279 }
1280}
1281#[doc = "I2C Peripheral"]
1282pub use self::i2c0 as i2c2;
1283#[doc = "CAN Peripheral"]
1284pub type Can0 = crate::Periph<can0::RegisterBlock, 0x4001_4000>;
1285impl core::fmt::Debug for Can0 {
1286 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1287 f.debug_struct("Can0").finish()
1288 }
1289}
1290#[doc = "CAN Peripheral"]
1291pub mod can0;
1292#[doc = "CAN Peripheral"]
1293pub type Can1 = crate::Periph<can0::RegisterBlock, 0x4001_4400>;
1294impl core::fmt::Debug for Can1 {
1295 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1296 f.debug_struct("Can1").finish()
1297 }
1298}
1299#[doc = "CAN Peripheral"]
1300pub use self::can0 as can1;
1301#[doc = "Analog to Digital Converter Peripheral"]
1302pub type Adc = crate::Periph<adc::RegisterBlock, 0x4002_2000>;
1303impl core::fmt::Debug for Adc {
1304 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1305 f.debug_struct("Adc").finish()
1306 }
1307}
1308#[doc = "Analog to Digital Converter Peripheral"]
1309pub mod adc;
1310#[doc = "Digital to Analog Converter Peripheral"]
1311pub type Dac0 = crate::Periph<dac0::RegisterBlock, 0x4002_3000>;
1312impl core::fmt::Debug for Dac0 {
1313 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1314 f.debug_struct("Dac0").finish()
1315 }
1316}
1317#[doc = "Digital to Analog Converter Peripheral"]
1318pub mod dac0;
1319#[doc = "Digital to Analog Converter Peripheral"]
1320pub type Dac1 = crate::Periph<dac0::RegisterBlock, 0x4002_3800>;
1321impl core::fmt::Debug for Dac1 {
1322 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1323 f.debug_struct("Dac1").finish()
1324 }
1325}
1326#[doc = "Digital to Analog Converter Peripheral"]
1327pub use self::dac0 as dac1;
1328#[doc = "SpaceWire Peripheral"]
1329pub type Spw = crate::Periph<spw::RegisterBlock, 0x4000_3000>;
1330impl core::fmt::Debug for Spw {
1331 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1332 f.debug_struct("Spw").finish()
1333 }
1334}
1335#[doc = "SpaceWire Peripheral"]
1336pub mod spw;
1337#[doc = "Interrupt Router Peripheral"]
1338pub type IrqRouter = crate::Periph<irq_router::RegisterBlock, 0x4000_2000>;
1339impl core::fmt::Debug for IrqRouter {
1340 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1341 f.debug_struct("IrqRouter").finish()
1342 }
1343}
1344#[doc = "Interrupt Router Peripheral"]
1345pub mod irq_router;
1346#[doc = "Watchdog Block Peripheral"]
1347pub type WatchDog = crate::Periph<watch_dog::RegisterBlock, 0x4002_1000>;
1348impl core::fmt::Debug for WatchDog {
1349 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1350 f.debug_struct("WatchDog").finish()
1351 }
1352}
1353#[doc = "Watchdog Block Peripheral"]
1354pub mod watch_dog;
1355#[doc = "True Random Number Generator"]
1356pub type Trng = crate::Periph<trng::RegisterBlock, 0x4002_7000>;
1357impl core::fmt::Debug for Trng {
1358 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1359 f.debug_struct("Trng").finish()
1360 }
1361}
1362#[doc = "True Random Number Generator"]
1363pub mod trng;
1364#[doc = "Ethernet Block"]
1365pub type Eth = crate::Periph<eth::RegisterBlock, 0x4000_4000>;
1366impl core::fmt::Debug for Eth {
1367 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1368 f.debug_struct("Eth").finish()
1369 }
1370}
1371#[doc = "Ethernet Block"]
1372pub mod eth;
1373#[no_mangle]
1374static mut DEVICE_PERIPHERALS: bool = false;
1375#[doc = r" All the peripherals."]
1376#[allow(non_snake_case)]
1377pub struct Peripherals {
1378 #[doc = "CLKGEN"]
1379 pub clkgen: Clkgen,
1380 #[doc = "SYSCONFIG"]
1381 pub sysconfig: Sysconfig,
1382 #[doc = "DMA"]
1383 pub dma: Dma,
1384 #[doc = "IOCONFIG"]
1385 pub ioconfig: Ioconfig,
1386 #[doc = "UTILITY"]
1387 pub utility: Utility,
1388 #[doc = "PORTA"]
1389 pub porta: Porta,
1390 #[doc = "PORTB"]
1391 pub portb: Portb,
1392 #[doc = "PORTC"]
1393 pub portc: Portc,
1394 #[doc = "PORTD"]
1395 pub portd: Portd,
1396 #[doc = "PORTE"]
1397 pub porte: Porte,
1398 #[doc = "PORTF"]
1399 pub portf: Portf,
1400 #[doc = "PORTG"]
1401 pub portg: Portg,
1402 #[doc = "TIM0"]
1403 pub tim0: Tim0,
1404 #[doc = "TIM1"]
1405 pub tim1: Tim1,
1406 #[doc = "TIM2"]
1407 pub tim2: Tim2,
1408 #[doc = "TIM3"]
1409 pub tim3: Tim3,
1410 #[doc = "TIM4"]
1411 pub tim4: Tim4,
1412 #[doc = "TIM5"]
1413 pub tim5: Tim5,
1414 #[doc = "TIM6"]
1415 pub tim6: Tim6,
1416 #[doc = "TIM7"]
1417 pub tim7: Tim7,
1418 #[doc = "TIM8"]
1419 pub tim8: Tim8,
1420 #[doc = "TIM9"]
1421 pub tim9: Tim9,
1422 #[doc = "TIM10"]
1423 pub tim10: Tim10,
1424 #[doc = "TIM11"]
1425 pub tim11: Tim11,
1426 #[doc = "TIM12"]
1427 pub tim12: Tim12,
1428 #[doc = "TIM13"]
1429 pub tim13: Tim13,
1430 #[doc = "TIM14"]
1431 pub tim14: Tim14,
1432 #[doc = "TIM15"]
1433 pub tim15: Tim15,
1434 #[doc = "TIM16"]
1435 pub tim16: Tim16,
1436 #[doc = "TIM17"]
1437 pub tim17: Tim17,
1438 #[doc = "TIM18"]
1439 pub tim18: Tim18,
1440 #[doc = "TIM19"]
1441 pub tim19: Tim19,
1442 #[doc = "TIM20"]
1443 pub tim20: Tim20,
1444 #[doc = "TIM21"]
1445 pub tim21: Tim21,
1446 #[doc = "TIM22"]
1447 pub tim22: Tim22,
1448 #[doc = "TIM23"]
1449 pub tim23: Tim23,
1450 #[doc = "UART0"]
1451 pub uart0: Uart0,
1452 #[doc = "UART1"]
1453 pub uart1: Uart1,
1454 #[doc = "UART2"]
1455 pub uart2: Uart2,
1456 #[doc = "SPI0"]
1457 pub spi0: Spi0,
1458 #[doc = "SPI1"]
1459 pub spi1: Spi1,
1460 #[doc = "SPI2"]
1461 pub spi2: Spi2,
1462 #[doc = "SPI3"]
1463 pub spi3: Spi3,
1464 #[doc = "I2C0"]
1465 pub i2c0: I2c0,
1466 #[doc = "I2C1"]
1467 pub i2c1: I2c1,
1468 #[doc = "I2C2"]
1469 pub i2c2: I2c2,
1470 #[doc = "CAN0"]
1471 pub can0: Can0,
1472 #[doc = "CAN1"]
1473 pub can1: Can1,
1474 #[doc = "ADC"]
1475 pub adc: Adc,
1476 #[doc = "DAC0"]
1477 pub dac0: Dac0,
1478 #[doc = "DAC1"]
1479 pub dac1: Dac1,
1480 #[doc = "SPW"]
1481 pub spw: Spw,
1482 #[doc = "IRQ_ROUTER"]
1483 pub irq_router: IrqRouter,
1484 #[doc = "WATCH_DOG"]
1485 pub watch_dog: WatchDog,
1486 #[doc = "TRNG"]
1487 pub trng: Trng,
1488 #[doc = "ETH"]
1489 pub eth: Eth,
1490}
1491impl Peripherals {
1492 #[doc = r" Returns all the peripherals *once*."]
1493 #[cfg(feature = "critical-section")]
1494 #[inline]
1495 pub fn take() -> Option<Self> {
1496 critical_section::with(|_| {
1497 if unsafe { DEVICE_PERIPHERALS } {
1498 return None;
1499 }
1500 Some(unsafe { Peripherals::steal() })
1501 })
1502 }
1503 #[doc = r" Unchecked version of `Peripherals::take`."]
1504 #[doc = r""]
1505 #[doc = r" # Safety"]
1506 #[doc = r""]
1507 #[doc = r" Each of the returned peripherals must be used at most once."]
1508 #[inline]
1509 pub unsafe fn steal() -> Self {
1510 DEVICE_PERIPHERALS = true;
1511 Peripherals {
1512 clkgen: Clkgen::steal(),
1513 sysconfig: Sysconfig::steal(),
1514 dma: Dma::steal(),
1515 ioconfig: Ioconfig::steal(),
1516 utility: Utility::steal(),
1517 porta: Porta::steal(),
1518 portb: Portb::steal(),
1519 portc: Portc::steal(),
1520 portd: Portd::steal(),
1521 porte: Porte::steal(),
1522 portf: Portf::steal(),
1523 portg: Portg::steal(),
1524 tim0: Tim0::steal(),
1525 tim1: Tim1::steal(),
1526 tim2: Tim2::steal(),
1527 tim3: Tim3::steal(),
1528 tim4: Tim4::steal(),
1529 tim5: Tim5::steal(),
1530 tim6: Tim6::steal(),
1531 tim7: Tim7::steal(),
1532 tim8: Tim8::steal(),
1533 tim9: Tim9::steal(),
1534 tim10: Tim10::steal(),
1535 tim11: Tim11::steal(),
1536 tim12: Tim12::steal(),
1537 tim13: Tim13::steal(),
1538 tim14: Tim14::steal(),
1539 tim15: Tim15::steal(),
1540 tim16: Tim16::steal(),
1541 tim17: Tim17::steal(),
1542 tim18: Tim18::steal(),
1543 tim19: Tim19::steal(),
1544 tim20: Tim20::steal(),
1545 tim21: Tim21::steal(),
1546 tim22: Tim22::steal(),
1547 tim23: Tim23::steal(),
1548 uart0: Uart0::steal(),
1549 uart1: Uart1::steal(),
1550 uart2: Uart2::steal(),
1551 spi0: Spi0::steal(),
1552 spi1: Spi1::steal(),
1553 spi2: Spi2::steal(),
1554 spi3: Spi3::steal(),
1555 i2c0: I2c0::steal(),
1556 i2c1: I2c1::steal(),
1557 i2c2: I2c2::steal(),
1558 can0: Can0::steal(),
1559 can1: Can1::steal(),
1560 adc: Adc::steal(),
1561 dac0: Dac0::steal(),
1562 dac1: Dac1::steal(),
1563 spw: Spw::steal(),
1564 irq_router: IrqRouter::steal(),
1565 watch_dog: WatchDog::steal(),
1566 trng: Trng::steal(),
1567 eth: Eth::steal(),
1568 }
1569 }
1570}