1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4 ctrl0: Ctrl0,
5 ctrl1: Ctrl1,
6 data: Data,
7 status: Status,
8 clkprescale: Clkprescale,
9 irq_enb: IrqEnb,
10 irq_raw: IrqRaw,
11 irq_end: IrqEnd,
12 irq_clr: IrqClr,
13 rxfifoirqtrg: Rxfifoirqtrg,
14 txfifoirqtrg: Txfifoirqtrg,
15 fifo_clr: FifoClr,
16 state: State,
17 _reserved13: [u8; 0x03c8],
18 perid: Perid,
19}
20impl RegisterBlock {
21 #[doc = "0x00 - Control Register 0"]
22 #[inline(always)]
23 pub const fn ctrl0(&self) -> &Ctrl0 {
24 &self.ctrl0
25 }
26 #[doc = "0x04 - Control Register 1"]
27 #[inline(always)]
28 pub const fn ctrl1(&self) -> &Ctrl1 {
29 &self.ctrl1
30 }
31 #[doc = "0x08 - Data Input/Output"]
32 #[inline(always)]
33 pub const fn data(&self) -> &Data {
34 &self.data
35 }
36 #[doc = "0x0c - Status Register"]
37 #[inline(always)]
38 pub const fn status(&self) -> &Status {
39 &self.status
40 }
41 #[doc = "0x10 - Clock Pre Scale divide value"]
42 #[inline(always)]
43 pub const fn clkprescale(&self) -> &Clkprescale {
44 &self.clkprescale
45 }
46 #[doc = "0x14 - Interrupt Enable Register"]
47 #[inline(always)]
48 pub const fn irq_enb(&self) -> &IrqEnb {
49 &self.irq_enb
50 }
51 #[doc = "0x18 - Raw Interrupt Status Register"]
52 #[inline(always)]
53 pub const fn irq_raw(&self) -> &IrqRaw {
54 &self.irq_raw
55 }
56 #[doc = "0x1c - Enabled Interrupt Status Register"]
57 #[inline(always)]
58 pub const fn irq_end(&self) -> &IrqEnd {
59 &self.irq_end
60 }
61 #[doc = "0x20 - Clear Interrupt Status Register"]
62 #[inline(always)]
63 pub const fn irq_clr(&self) -> &IrqClr {
64 &self.irq_clr
65 }
66 #[doc = "0x24 - Rx FIFO IRQ Trigger Level"]
67 #[inline(always)]
68 pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg {
69 &self.rxfifoirqtrg
70 }
71 #[doc = "0x28 - Tx FIFO IRQ Trigger Level"]
72 #[inline(always)]
73 pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg {
74 &self.txfifoirqtrg
75 }
76 #[doc = "0x2c - Clear FIFO Register"]
77 #[inline(always)]
78 pub const fn fifo_clr(&self) -> &FifoClr {
79 &self.fifo_clr
80 }
81 #[doc = "0x30 - Internal STATE of SPI Controller"]
82 #[inline(always)]
83 pub const fn state(&self) -> &State {
84 &self.state
85 }
86 #[doc = "0x3fc - Peripheral ID Register"]
87 #[inline(always)]
88 pub const fn perid(&self) -> &Perid {
89 &self.perid
90 }
91}
92#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`] module"]
93#[doc(alias = "CTRL0")]
94pub type Ctrl0 = crate::Reg<ctrl0::Ctrl0Spec>;
95#[doc = "Control Register 0"]
96pub mod ctrl0;
97#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] module"]
98#[doc(alias = "CTRL1")]
99pub type Ctrl1 = crate::Reg<ctrl1::Ctrl1Spec>;
100#[doc = "Control Register 1"]
101pub mod ctrl1;
102#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"]
103#[doc(alias = "DATA")]
104pub type Data = crate::Reg<data::DataSpec>;
105#[doc = "Data Input/Output"]
106pub mod data;
107#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"]
108#[doc(alias = "STATUS")]
109pub type Status = crate::Reg<status::StatusSpec>;
110#[doc = "Status Register"]
111pub mod status;
112#[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`] module"]
113#[doc(alias = "CLKPRESCALE")]
114pub type Clkprescale = crate::Reg<clkprescale::ClkprescaleSpec>;
115#[doc = "Clock Pre Scale divide value"]
116pub mod clkprescale;
117#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"]
118#[doc(alias = "IRQ_ENB")]
119pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
120#[doc = "Interrupt Enable Register"]
121pub mod irq_enb;
122pub use irq_enb as irq_raw;
123pub use irq_enb as irq_end;
124pub use irq_enb as irq_clr;
125pub use IrqEnb as IrqRaw;
126pub use IrqEnb as IrqEnd;
127pub use IrqEnb as IrqClr;
128#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"]
129#[doc(alias = "RXFIFOIRQTRG")]
130pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
131#[doc = "Rx FIFO IRQ Trigger Level"]
132pub mod rxfifoirqtrg;
133#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] module"]
134#[doc(alias = "TXFIFOIRQTRG")]
135pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
136#[doc = "Tx FIFO IRQ Trigger Level"]
137pub mod txfifoirqtrg;
138#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"]
139#[doc(alias = "FIFO_CLR")]
140pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
141#[doc = "Clear FIFO Register"]
142pub mod fifo_clr;
143#[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"]
144#[doc(alias = "STATE")]
145pub type State = crate::Reg<state::StateSpec>;
146#[doc = "Internal STATE of SPI Controller"]
147pub mod state;
148#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
149#[doc(alias = "PERID")]
150pub type Perid = crate::Reg<perid::PeridSpec>;
151#[doc = "Peripheral ID Register"]
152pub mod perid;