Crate ud_arch_aarch64 

AArch64 instruction decoder + minimal lifter.

v0 scope is intentionally narrow: AArch64 instructions are fixed-width 4 bytes, so the decoder just splits the input into 4-byte chunks. Each chunk gets a coarse classification — enough to extract direct branch targets and identify returns, which is what the IR layer needs to build basic blocks. Full mnemonic + operand printing isn’t here yet; instructions render as <arm64 0xXXXXXXXX> placeholder text alongside their pinned bytes, so the round-trip property holds via byte identity.

Future iterations will wire in a real disassembler (bad64 or similar) to produce readable @asm text and unlock the same lifting passes the x86 backend has (prologue/epilogue lift, call-site analysis, if/else groups).

Structs

Aarch64Codec

Stateless aarch64 codec.

DecodedInsn

One decoded AArch64 instruction. Carries the raw 4-byte encoding, the address it lived at, and a coarse InsnKind.

Enums

Error

Errors specific to the AArch64 backend.

InsnKind

Coarse classification of an AArch64 instruction. Enough to pick out flow-control behaviour for CFG construction; everything else falls into Other.

Constants

INSN_SIZE

On-disk size of every AArch64 instruction.

Functions

decode

Decode bytes as an AArch64 instruction stream starting at virtual address start. The buffer length must be a multiple of INSN_SIZE — AArch64 has no concept of “the rest is data” the way x86 does, so a misaligned tail is a hard error.

format_text

Render an instruction as placeholder text alongside its bytes. v0: emits <arm64 0xXXXXXXXX> (mnemonic-based when classified) — full disassembly comes when we wire a real decoder.

lift_function

Lift a decoded instruction stream into a CFG.

register

Register the aarch64 codec factory with the registry.

Type Aliases

Result