AArch64 instruction decoder + minimal lifter.
v0 scope is intentionally narrow: AArch64 instructions are
fixed-width 4 bytes, so the decoder just splits the input into
4-byte chunks. Each chunk gets a coarse classification —
enough to extract direct branch targets and identify returns,
which is what the IR layer needs to build basic blocks. Full
mnemonic + operand printing isn't here yet; instructions render
as <arm64 0xXXXXXXXX> placeholder text alongside their pinned
bytes, so the round-trip property holds via byte identity.
Future iterations will wire in a real disassembler (bad64 or
similar) to produce readable @asm text and unlock the same
lifting passes the x86 backend has (prologue/epilogue lift,
call-site analysis, if/else groups).