[−][src]Type Definition tm4c129x::epi0::hb16cfg::W
type W = W<u32, HB16CFG>;
Writer for register HB16CFG
Methods
impl W[src]
pub fn mode(&mut self) -> MODE_W[src]
Bits 0:1 - Host Bus Sub-Mode
pub fn bsel(&mut self) -> BSEL_W[src]
Bit 2 - Byte Select Configuration
pub fn rdws(&mut self) -> RDWS_W[src]
Bits 4:5 - Read Wait States
pub fn wrws(&mut self) -> WRWS_W[src]
Bits 6:7 - Write Wait States
pub fn maxwait(&mut self) -> MAXWAIT_W[src]
Bits 8:15 - Maximum Wait
pub fn burst(&mut self) -> BURST_W[src]
Bit 16 - Burst Mode
pub fn rdcre(&mut self) -> RDCRE_W[src]
Bit 17 - PSRAM Configuration Register Read
pub fn wrcre(&mut self) -> WRCRE_W[src]
Bit 18 - PSRAM Configuration Register Write
pub fn alehigh(&mut self) -> ALEHIGH_W[src]
Bit 19 - ALE Strobe Polarity
pub fn rdhigh(&mut self) -> RDHIGH_W[src]
Bit 20 - READ Strobe Polarity
pub fn wrhigh(&mut self) -> WRHIGH_W[src]
Bit 21 - WRITE Strobe Polarity
pub fn xfeen(&mut self) -> XFEEN_W[src]
Bit 22 - External FIFO EMPTY Enable
pub fn xffen(&mut self) -> XFFEN_W[src]
Bit 23 - External FIFO FULL Enable
pub fn irdyinv(&mut self) -> IRDYINV_W[src]
Bit 27 - Input Ready Invert
pub fn rdyen(&mut self) -> RDYEN_W[src]
Bit 28 - Input Ready Enable
pub fn clkinv(&mut self) -> CLKINV_W[src]
Bit 29 - Invert Output Clock Enable
pub fn clkgatei(&mut self) -> CLKGATEI_W[src]
Bit 30 - Clock Gated Idle
pub fn clkgate(&mut self) -> CLKGATE_W[src]
Bit 31 - Clock Gated