Struct W

pub struct W<U, REG> { /* private fields */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _CTL>>

pub fn inten(&mut self) -> INTEN_W<'_>

Bit 0 - Watchdog Interrupt Enable

pub fn resen(&mut self) -> RESEN_W<'_>

Bit 1 - Watchdog Reset Enable

pub fn inttype(&mut self) -> INTTYPE_W<'_>

Bit 2 - Watchdog Interrupt Type

pub fn wrc(&mut self) -> WRC_W<'_>

Bit 31 - Write Complete

impl W<u32, Reg<u32, _TEST>>

pub fn stall(&mut self) -> STALL_W<'_>

Bit 8 - Watchdog Stall Enable

impl W<u32, Reg<u32, _LOCK>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 0:31 - Watchdog Lock

impl W<u32, Reg<u32, _IM>>

pub fn gpio(&mut self) -> GPIO_W<'_>

Bits 0:7 - GPIO Interrupt Mask Enable

impl W<u32, Reg<u32, _ICR>>

pub fn gpio(&mut self) -> GPIO_W<'_>

Bits 0:7 - GPIO Interrupt Clear

impl W<u32, Reg<u32, _LOCK>>

pub fn lock(&mut self) -> LOCK_W<'_>

Bits 0:31 - GPIO Lock

impl W<u32, Reg<u32, _CR0>>

pub fn dss(&mut self) -> DSS_W<'_>

Bits 0:3 - SSI Data Size Select

pub fn frf(&mut self) -> FRF_W<'_>

Bits 4:5 - SSI Frame Format Select

pub fn spo(&mut self) -> SPO_W<'_>

Bit 6 - SSI Serial Clock Polarity

pub fn sph(&mut self) -> SPH_W<'_>

Bit 7 - SSI Serial Clock Phase

pub fn scr(&mut self) -> SCR_W<'_>

Bits 8:15 - SSI Serial Clock Rate

impl W<u32, Reg<u32, _CR1>>

pub fn lbm(&mut self) -> LBM_W<'_>

Bit 0 - SSI Loopback Mode

pub fn sse(&mut self) -> SSE_W<'_>

Bit 1 - SSI Synchronous Serial Port Enable

pub fn ms(&mut self) -> MS_W<'_>

Bit 2 - SSI Master/Slave Select

pub fn eot(&mut self) -> EOT_W<'_>

Bit 4 - End of Transmission

impl W<u32, Reg<u32, _DR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - SSI Receive/Transmit Data

impl W<u32, Reg<u32, _CPSR>>

pub fn cpsdvsr(&mut self) -> CPSDVSR_W<'_>

Bits 0:7 - SSI Clock Prescale Divisor

impl W<u32, Reg<u32, _IM>>

pub fn rorim(&mut self) -> RORIM_W<'_>

Bit 0 - SSI Receive Overrun Interrupt Mask

pub fn rtim(&mut self) -> RTIM_W<'_>

Bit 1 - SSI Receive Time-Out Interrupt Mask

pub fn rxim(&mut self) -> RXIM_W<'_>

Bit 2 - SSI Receive FIFO Interrupt Mask

pub fn txim(&mut self) -> TXIM_W<'_>

Bit 3 - SSI Transmit FIFO Interrupt Mask

impl W<u32, Reg<u32, _ICR>>

pub fn roric(&mut self) -> RORIC_W<'_>

Bit 0 - SSI Receive Overrun Interrupt Clear

pub fn rtic(&mut self) -> RTIC_W<'_>

Bit 1 - SSI Receive Time-Out Interrupt Clear

impl W<u32, Reg<u32, _DMACTL>>

pub fn rxdmae(&mut self) -> RXDMAE_W<'_>

Bit 0 - Receive DMA Enable

pub fn txdmae(&mut self) -> TXDMAE_W<'_>

Bit 1 - Transmit DMA Enable

impl W<u32, Reg<u32, _CC>>

pub fn cs(&mut self) -> CS_W<'_>

Bits 0:3 - SSI Baud Clock Source

impl W<u32, Reg<u32, _DR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:7 - Data Transmitted or Received

pub fn fe(&mut self) -> FE_W<'_>

Bit 8 - UART Framing Error

pub fn pe(&mut self) -> PE_W<'_>

Bit 9 - UART Parity Error

pub fn be(&mut self) -> BE_W<'_>

Bit 10 - UART Break Error

pub fn oe(&mut self) -> OE_W<'_>

Bit 11 - UART Overrun Error

impl W<u32, Reg<u32, _RSR>>

pub fn fe(&mut self) -> FE_W<'_>

Bit 0 - UART Framing Error

pub fn pe(&mut self) -> PE_W<'_>

Bit 1 - UART Parity Error

pub fn be(&mut self) -> BE_W<'_>

Bit 2 - UART Break Error

pub fn oe(&mut self) -> OE_W<'_>

Bit 3 - UART Overrun Error

impl W<u32, Reg<u32, _ECR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:7 - Error Clear

impl W<u32, Reg<u32, _ILPR>>

pub fn ilpdvsr(&mut self) -> ILPDVSR_W<'_>

Bits 0:7 - IrDA Low-Power Divisor

impl W<u32, Reg<u32, _IBRD>>

pub fn divint(&mut self) -> DIVINT_W<'_>

Bits 0:15 - Integer Baud-Rate Divisor

impl W<u32, Reg<u32, _FBRD>>

pub fn divfrac(&mut self) -> DIVFRAC_W<'_>

Bits 0:5 - Fractional Baud-Rate Divisor

impl W<u32, Reg<u32, _LCRH>>

pub fn brk(&mut self) -> BRK_W<'_>

Bit 0 - UART Send Break

pub fn pen(&mut self) -> PEN_W<'_>

Bit 1 - UART Parity Enable

pub fn eps(&mut self) -> EPS_W<'_>

Bit 2 - UART Even Parity Select

pub fn stp2(&mut self) -> STP2_W<'_>

Bit 3 - UART Two Stop Bits Select

pub fn fen(&mut self) -> FEN_W<'_>

Bit 4 - UART Enable FIFOs

pub fn wlen(&mut self) -> WLEN_W<'_>

Bits 5:6 - UART Word Length

pub fn sps(&mut self) -> SPS_W<'_>

Bit 7 - UART Stick Parity Select

impl W<u32, Reg<u32, _CTL>>

pub fn uarten(&mut self) -> UARTEN_W<'_>

Bit 0 - UART Enable

pub fn siren(&mut self) -> SIREN_W<'_>

Bit 1 - UART SIR Enable

pub fn sirlp(&mut self) -> SIRLP_W<'_>

Bit 2 - UART SIR Low-Power Mode

pub fn smart(&mut self) -> SMART_W<'_>

Bit 3 - ISO 7816 Smart Card Support

pub fn eot(&mut self) -> EOT_W<'_>

Bit 4 - End of Transmission

pub fn hse(&mut self) -> HSE_W<'_>

Bit 5 - High-Speed Enable

pub fn lbe(&mut self) -> LBE_W<'_>

Bit 7 - UART Loop Back Enable

pub fn txe(&mut self) -> TXE_W<'_>

Bit 8 - UART Transmit Enable

pub fn rxe(&mut self) -> RXE_W<'_>

Bit 9 - UART Receive Enable

pub fn rts(&mut self) -> RTS_W<'_>

Bit 11 - Request to Send

pub fn rtsen(&mut self) -> RTSEN_W<'_>

Bit 14 - Enable Request to Send

pub fn ctsen(&mut self) -> CTSEN_W<'_>

Bit 15 - Enable Clear To Send

impl W<u32, Reg<u32, _IFLS>>

pub fn tx(&mut self) -> TX_W<'_>

Bits 0:2 - UART Transmit Interrupt FIFO Level Select

pub fn rx(&mut self) -> RX_W<'_>

Bits 3:5 - UART Receive Interrupt FIFO Level Select

impl W<u32, Reg<u32, _IM>>

pub fn ctsmim(&mut self) -> CTSMIM_W<'_>

Bit 1 - UART Clear to Send Modem Interrupt Mask

pub fn rxim(&mut self) -> RXIM_W<'_>

Bit 4 - UART Receive Interrupt Mask

pub fn txim(&mut self) -> TXIM_W<'_>

Bit 5 - UART Transmit Interrupt Mask

pub fn rtim(&mut self) -> RTIM_W<'_>

Bit 6 - UART Receive Time-Out Interrupt Mask

pub fn feim(&mut self) -> FEIM_W<'_>

Bit 7 - UART Framing Error Interrupt Mask

pub fn peim(&mut self) -> PEIM_W<'_>

Bit 8 - UART Parity Error Interrupt Mask

pub fn beim(&mut self) -> BEIM_W<'_>

Bit 9 - UART Break Error Interrupt Mask

pub fn oeim(&mut self) -> OEIM_W<'_>

Bit 10 - UART Overrun Error Interrupt Mask

pub fn _9bitim(&mut self) -> _9BITIM_W<'_>

Bit 12 - 9-Bit Mode Interrupt Mask

impl W<u32, Reg<u32, _ICR>>

pub fn ctsmic(&mut self) -> CTSMIC_W<'_>

Bit 1 - UART Clear to Send Modem Interrupt Clear

pub fn rxic(&mut self) -> RXIC_W<'_>

Bit 4 - Receive Interrupt Clear

pub fn txic(&mut self) -> TXIC_W<'_>

Bit 5 - Transmit Interrupt Clear

pub fn rtic(&mut self) -> RTIC_W<'_>

Bit 6 - Receive Time-Out Interrupt Clear

pub fn feic(&mut self) -> FEIC_W<'_>

Bit 7 - Framing Error Interrupt Clear

pub fn peic(&mut self) -> PEIC_W<'_>

Bit 8 - Parity Error Interrupt Clear

pub fn beic(&mut self) -> BEIC_W<'_>

Bit 9 - Break Error Interrupt Clear

pub fn oeic(&mut self) -> OEIC_W<'_>

Bit 10 - Overrun Error Interrupt Clear

pub fn _9bitic(&mut self) -> _9BITIC_W<'_>

Bit 12 - 9-Bit Mode Interrupt Clear

impl W<u32, Reg<u32, _DMACTL>>

pub fn rxdmae(&mut self) -> RXDMAE_W<'_>

Bit 0 - Receive DMA Enable

pub fn txdmae(&mut self) -> TXDMAE_W<'_>

Bit 1 - Transmit DMA Enable

pub fn dmaerr(&mut self) -> DMAERR_W<'_>

Bit 2 - DMA on Error

impl W<u32, Reg<u32, __9BITADDR>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:7 - Self Address for 9-Bit Mode

pub fn _9biten(&mut self) -> _9BITEN_W<'_>

Bit 15 - Enable 9-Bit Mode

impl W<u32, Reg<u32, __9BITAMASK>>

pub fn mask(&mut self) -> MASK_W<'_>

Bits 0:7 - Self Address Mask for 9-Bit Mode

impl W<u32, Reg<u32, _CC>>

pub fn cs(&mut self) -> CS_W<'_>

Bits 0:3 - UART Baud Clock Source

impl W<u32, Reg<u32, _MSA>>

pub fn rs(&mut self) -> RS_W<'_>

Bit 0 - Receive not send

pub fn sa(&mut self) -> SA_W<'_>

Bits 1:7 - I2C Slave Address

impl W<u32, Reg<u32, _MCS>>

pub fn run(&mut self) -> RUN_W<'_>

Bit 0 - I2C Master Enable

pub fn busy(&mut self) -> BUSY_W<'_>

Bit 0 - I2C Busy

pub fn error(&mut self) -> ERROR_W<'_>

Bit 1 - Error

pub fn start(&mut self) -> START_W<'_>

Bit 1 - Generate START

pub fn adrack(&mut self) -> ADRACK_W<'_>

Bit 2 - Acknowledge Address

pub fn stop(&mut self) -> STOP_W<'_>

Bit 2 - Generate STOP

pub fn ack(&mut self) -> ACK_W<'_>

Bit 3 - Data Acknowledge Enable

pub fn datack(&mut self) -> DATACK_W<'_>

Bit 3 - Acknowledge Data

pub fn arblst(&mut self) -> ARBLST_W<'_>

Bit 4 - Arbitration Lost

pub fn hs(&mut self) -> HS_W<'_>

Bit 4 - High-Speed Enable

pub fn idle(&mut self) -> IDLE_W<'_>

Bit 5 - I2C Idle

pub fn busbsy(&mut self) -> BUSBSY_W<'_>

Bit 6 - Bus Busy

pub fn clkto(&mut self) -> CLKTO_W<'_>

Bit 7 - Clock Timeout Error

impl W<u32, Reg<u32, _MDR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:7 - This byte contains the data transferred during a transaction

impl W<u32, Reg<u32, _MTPR>>

pub fn tpr(&mut self) -> TPR_W<'_>

Bits 0:6 - Timer Period

pub fn hs(&mut self) -> HS_W<'_>

Bit 7 - High-Speed Enable

impl W<u32, Reg<u32, _MIMR>>

pub fn im(&mut self) -> IM_W<'_>

Bit 0 - Master Interrupt Mask

pub fn clkim(&mut self) -> CLKIM_W<'_>

Bit 1 - Clock Timeout Interrupt Mask

impl W<u32, Reg<u32, _MICR>>

pub fn ic(&mut self) -> IC_W<'_>

Bit 0 - Master Interrupt Clear

pub fn clkic(&mut self) -> CLKIC_W<'_>

Bit 1 - Clock Timeout Interrupt Clear

impl W<u32, Reg<u32, _MCR>>

pub fn lpbk(&mut self) -> LPBK_W<'_>

Bit 0 - I2C Loopback

pub fn mfe(&mut self) -> MFE_W<'_>

Bit 4 - I2C Master Function Enable

pub fn sfe(&mut self) -> SFE_W<'_>

Bit 5 - I2C Slave Function Enable

pub fn gfe(&mut self) -> GFE_W<'_>

Bit 6 - I2C Glitch Filter Enable

impl W<u32, Reg<u32, _MCLKOCNT>>

pub fn cntl(&mut self) -> CNTL_W<'_>

Bits 0:7 - I2C Master Count

impl W<u32, Reg<u32, _MCR2>>

pub fn gfpw(&mut self) -> GFPW_W<'_>

Bits 4:6 - I2C Glitch Filter Pulse Width

impl W<u32, Reg<u32, _SOAR>>

pub fn oar(&mut self) -> OAR_W<'_>

Bits 0:6 - I2C Slave Own Address

impl W<u32, Reg<u32, _SDR>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:7 - Data for Transfer

impl W<u32, Reg<u32, _SIMR>>

pub fn dataim(&mut self) -> DATAIM_W<'_>

Bit 0 - Data Interrupt Mask

pub fn startim(&mut self) -> STARTIM_W<'_>

Bit 1 - Start Condition Interrupt Mask

pub fn stopim(&mut self) -> STOPIM_W<'_>

Bit 2 - Stop Condition Interrupt Mask

impl W<u32, Reg<u32, _SICR>>

pub fn dataic(&mut self) -> DATAIC_W<'_>

Bit 0 - Data Interrupt Clear

pub fn startic(&mut self) -> STARTIC_W<'_>

Bit 1 - Start Condition Interrupt Clear

pub fn stopic(&mut self) -> STOPIC_W<'_>

Bit 2 - Stop Condition Interrupt Clear

impl W<u32, Reg<u32, _SOAR2>>

pub fn oar2(&mut self) -> OAR2_W<'_>

Bits 0:6 - I2C Slave Own Address 2

pub fn oar2en(&mut self) -> OAR2EN_W<'_>

Bit 7 - I2C Slave Own Address 2 Enable

impl W<u32, Reg<u32, _SACKCTL>>

pub fn ackoen(&mut self) -> ACKOEN_W<'_>

Bit 0 - I2C Slave ACK Override Enable

pub fn ackoval(&mut self) -> ACKOVAL_W<'_>

Bit 1 - I2C Slave ACK Override Value

impl W<u32, Reg<u32, _CTL>>

pub fn globalsync0(&mut self) -> GLOBALSYNC0_W<'_>

Bit 0 - Update PWM Generator 0

pub fn globalsync1(&mut self) -> GLOBALSYNC1_W<'_>

Bit 1 - Update PWM Generator 1

pub fn globalsync2(&mut self) -> GLOBALSYNC2_W<'_>

Bit 2 - Update PWM Generator 2

pub fn globalsync3(&mut self) -> GLOBALSYNC3_W<'_>

Bit 3 - Update PWM Generator 3

impl W<u32, Reg<u32, _SYNC>>

pub fn sync0(&mut self) -> SYNC0_W<'_>

Bit 0 - Reset Generator 0 Counter

pub fn sync1(&mut self) -> SYNC1_W<'_>

Bit 1 - Reset Generator 1 Counter

pub fn sync2(&mut self) -> SYNC2_W<'_>

Bit 2 - Reset Generator 2 Counter

pub fn sync3(&mut self) -> SYNC3_W<'_>

Bit 3 - Reset Generator 3 Counter

impl W<u32, Reg<u32, _ENABLE>>

pub fn pwm0en(&mut self) -> PWM0EN_W<'_>

Bit 0 - MnPWM0 Output Enable

pub fn pwm1en(&mut self) -> PWM1EN_W<'_>

Bit 1 - MnPWM1 Output Enable

pub fn pwm2en(&mut self) -> PWM2EN_W<'_>

Bit 2 - MnPWM2 Output Enable

pub fn pwm3en(&mut self) -> PWM3EN_W<'_>

Bit 3 - MnPWM3 Output Enable

pub fn pwm4en(&mut self) -> PWM4EN_W<'_>

Bit 4 - MnPWM4 Output Enable

pub fn pwm5en(&mut self) -> PWM5EN_W<'_>

Bit 5 - MnPWM5 Output Enable

pub fn pwm6en(&mut self) -> PWM6EN_W<'_>

Bit 6 - MnPWM6 Output Enable

pub fn pwm7en(&mut self) -> PWM7EN_W<'_>

Bit 7 - MnPWM7 Output Enable

impl W<u32, Reg<u32, _INVERT>>

pub fn pwm0inv(&mut self) -> PWM0INV_W<'_>

Bit 0 - Invert MnPWM0 Signal

pub fn pwm1inv(&mut self) -> PWM1INV_W<'_>

Bit 1 - Invert MnPWM1 Signal

pub fn pwm2inv(&mut self) -> PWM2INV_W<'_>

Bit 2 - Invert MnPWM2 Signal

pub fn pwm3inv(&mut self) -> PWM3INV_W<'_>

Bit 3 - Invert MnPWM3 Signal

pub fn pwm4inv(&mut self) -> PWM4INV_W<'_>

Bit 4 - Invert MnPWM4 Signal

pub fn pwm5inv(&mut self) -> PWM5INV_W<'_>

Bit 5 - Invert MnPWM5 Signal

pub fn pwm6inv(&mut self) -> PWM6INV_W<'_>

Bit 6 - Invert MnPWM6 Signal

pub fn pwm7inv(&mut self) -> PWM7INV_W<'_>

Bit 7 - Invert MnPWM7 Signal

impl W<u32, Reg<u32, _FAULT>>

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 0 - MnPWM0 Fault

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 1 - MnPWM1 Fault

pub fn fault2(&mut self) -> FAULT2_W<'_>

Bit 2 - MnPWM2 Fault

pub fn fault3(&mut self) -> FAULT3_W<'_>

Bit 3 - MnPWM3 Fault

pub fn fault4(&mut self) -> FAULT4_W<'_>

Bit 4 - MnPWM4 Fault

pub fn fault5(&mut self) -> FAULT5_W<'_>

Bit 5 - MnPWM5 Fault

pub fn fault6(&mut self) -> FAULT6_W<'_>

Bit 6 - MnPWM6 Fault

pub fn fault7(&mut self) -> FAULT7_W<'_>

Bit 7 - MnPWM7 Fault

impl W<u32, Reg<u32, _INTEN>>

pub fn intpwm0(&mut self) -> INTPWM0_W<'_>

Bit 0 - PWM0 Interrupt Enable

pub fn intpwm1(&mut self) -> INTPWM1_W<'_>

Bit 1 - PWM1 Interrupt Enable

pub fn intpwm2(&mut self) -> INTPWM2_W<'_>

Bit 2 - PWM2 Interrupt Enable

pub fn intpwm3(&mut self) -> INTPWM3_W<'_>

Bit 3 - PWM3 Interrupt Enable

pub fn intfault0(&mut self) -> INTFAULT0_W<'_>

Bit 16 - Interrupt Fault 0

pub fn intfault1(&mut self) -> INTFAULT1_W<'_>

Bit 17 - Interrupt Fault 1

impl W<u32, Reg<u32, _ISC>>

pub fn intpwm0(&mut self) -> INTPWM0_W<'_>

Bit 0 - PWM0 Interrupt Status

pub fn intpwm1(&mut self) -> INTPWM1_W<'_>

Bit 1 - PWM1 Interrupt Status

pub fn intpwm2(&mut self) -> INTPWM2_W<'_>

Bit 2 - PWM2 Interrupt Status

pub fn intpwm3(&mut self) -> INTPWM3_W<'_>

Bit 3 - PWM3 Interrupt Status

pub fn intfault0(&mut self) -> INTFAULT0_W<'_>

Bit 16 - FAULT0 Interrupt Asserted

pub fn intfault1(&mut self) -> INTFAULT1_W<'_>

Bit 17 - FAULT1 Interrupt Asserted

impl W<u32, Reg<u32, _FAULTVAL>>

pub fn pwm0(&mut self) -> PWM0_W<'_>

Bit 0 - MnPWM0 Fault Value

pub fn pwm1(&mut self) -> PWM1_W<'_>

Bit 1 - MnPWM1 Fault Value

pub fn pwm2(&mut self) -> PWM2_W<'_>

Bit 2 - MnPWM2 Fault Value

pub fn pwm3(&mut self) -> PWM3_W<'_>

Bit 3 - MnPWM3 Fault Value

pub fn pwm4(&mut self) -> PWM4_W<'_>

Bit 4 - MnPWM4 Fault Value

pub fn pwm5(&mut self) -> PWM5_W<'_>

Bit 5 - MnPWM5 Fault Value

pub fn pwm6(&mut self) -> PWM6_W<'_>

Bit 6 - MnPWM6 Fault Value

pub fn pwm7(&mut self) -> PWM7_W<'_>

Bit 7 - MnPWM7 Fault Value

impl W<u32, Reg<u32, _ENUPD>>

pub fn enupd0(&mut self) -> ENUPD0_W<'_>

Bits 0:1 - MnPWM0 Enable Update Mode

pub fn enupd1(&mut self) -> ENUPD1_W<'_>

Bits 2:3 - MnPWM1 Enable Update Mode

pub fn enupd2(&mut self) -> ENUPD2_W<'_>

Bits 4:5 - MnPWM2 Enable Update Mode

pub fn enupd3(&mut self) -> ENUPD3_W<'_>

Bits 6:7 - MnPWM3 Enable Update Mode

pub fn enupd4(&mut self) -> ENUPD4_W<'_>

Bits 8:9 - MnPWM4 Enable Update Mode

pub fn enupd5(&mut self) -> ENUPD5_W<'_>

Bits 10:11 - MnPWM5 Enable Update Mode

pub fn enupd6(&mut self) -> ENUPD6_W<'_>

Bits 12:13 - MnPWM6 Enable Update Mode

pub fn enupd7(&mut self) -> ENUPD7_W<'_>

Bits 14:15 - MnPWM7 Enable Update Mode

impl W<u32, Reg<u32, __0_CTL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - PWM Block Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bit 1 - Counter Mode

pub fn debug(&mut self) -> DEBUG_W<'_>

Bit 2 - Debug Mode

pub fn loadupd(&mut self) -> LOADUPD_W<'_>

Bit 3 - Load Register Update Mode

pub fn cmpaupd(&mut self) -> CMPAUPD_W<'_>

Bit 4 - Comparator A Update Mode

pub fn cmpbupd(&mut self) -> CMPBUPD_W<'_>

Bit 5 - Comparator B Update Mode

pub fn genaupd(&mut self) -> GENAUPD_W<'_>

Bits 6:7 - PWMnGENA Update Mode

pub fn genbupd(&mut self) -> GENBUPD_W<'_>

Bits 8:9 - PWMnGENB Update Mode

pub fn dbctlupd(&mut self) -> DBCTLUPD_W<'_>

Bits 10:11 - PWMnDBCTL Update Mode

pub fn dbriseupd(&mut self) -> DBRISEUPD_W<'_>

Bits 12:13 - PWMnDBRISE Update Mode

pub fn dbfallupd(&mut self) -> DBFALLUPD_W<'_>

Bits 14:15 - PWMnDBFALL Update Mode

pub fn fltsrc(&mut self) -> FLTSRC_W<'_>

Bit 16 - Fault Condition Source

pub fn minfltper(&mut self) -> MINFLTPER_W<'_>

Bit 17 - Minimum Fault Period

pub fn latch(&mut self) -> LATCH_W<'_>

Bit 18 - Latch Fault Input

impl W<u32, Reg<u32, __0_INTEN>>

pub fn intcntzero(&mut self) -> INTCNTZERO_W<'_>

Bit 0 - Interrupt for Counter=0

pub fn intcntload(&mut self) -> INTCNTLOAD_W<'_>

Bit 1 - Interrupt for Counter=PWMnLOAD

pub fn intcmpau(&mut self) -> INTCMPAU_W<'_>

Bit 2 - Interrupt for Counter=PWMnCMPA Up

pub fn intcmpad(&mut self) -> INTCMPAD_W<'_>

Bit 3 - Interrupt for Counter=PWMnCMPA Down

pub fn intcmpbu(&mut self) -> INTCMPBU_W<'_>

Bit 4 - Interrupt for Counter=PWMnCMPB Up

pub fn intcmpbd(&mut self) -> INTCMPBD_W<'_>

Bit 5 - Interrupt for Counter=PWMnCMPB Down

pub fn trcntzero(&mut self) -> TRCNTZERO_W<'_>

Bit 8 - Trigger for Counter=0

pub fn trcntload(&mut self) -> TRCNTLOAD_W<'_>

Bit 9 - Trigger for Counter=PWMnLOAD

pub fn trcmpau(&mut self) -> TRCMPAU_W<'_>

Bit 10 - Trigger for Counter=PWMnCMPA Up

pub fn trcmpad(&mut self) -> TRCMPAD_W<'_>

Bit 11 - Trigger for Counter=PWMnCMPA Down

pub fn trcmpbu(&mut self) -> TRCMPBU_W<'_>

Bit 12 - Trigger for Counter=PWMnCMPB Up

pub fn trcmpbd(&mut self) -> TRCMPBD_W<'_>

Bit 13 - Trigger for Counter=PWMnCMPB Down

impl W<u32, Reg<u32, __0_ISC>>

pub fn intcntzero(&mut self) -> INTCNTZERO_W<'_>

Bit 0 - Counter=0 Interrupt

pub fn intcntload(&mut self) -> INTCNTLOAD_W<'_>

Bit 1 - Counter=Load Interrupt

pub fn intcmpau(&mut self) -> INTCMPAU_W<'_>

Bit 2 - Comparator A Up Interrupt

pub fn intcmpad(&mut self) -> INTCMPAD_W<'_>

Bit 3 - Comparator A Down Interrupt

pub fn intcmpbu(&mut self) -> INTCMPBU_W<'_>

Bit 4 - Comparator B Up Interrupt

pub fn intcmpbd(&mut self) -> INTCMPBD_W<'_>

Bit 5 - Comparator B Down Interrupt

impl W<u32, Reg<u32, __0_LOAD>>

pub fn load(&mut self) -> LOAD_W<'_>

Bits 0:15 - Counter Load Value

impl W<u32, Reg<u32, __0_CMPA>>

pub fn cmpa(&mut self) -> CMPA_W<'_>

Bits 0:15 - Comparator A Value

impl W<u32, Reg<u32, __0_CMPB>>

pub fn cmpb(&mut self) -> CMPB_W<'_>

Bits 0:15 - Comparator B Value

impl W<u32, Reg<u32, __0_GENA>>

pub fn actzero(&mut self) -> ACTZERO_W<'_>

Bits 0:1 - Action for Counter=0

pub fn actload(&mut self) -> ACTLOAD_W<'_>

Bits 2:3 - Action for Counter=LOAD

pub fn actcmpau(&mut self) -> ACTCMPAU_W<'_>

Bits 4:5 - Action for Comparator A Up

pub fn actcmpad(&mut self) -> ACTCMPAD_W<'_>

Bits 6:7 - Action for Comparator A Down

pub fn actcmpbu(&mut self) -> ACTCMPBU_W<'_>

Bits 8:9 - Action for Comparator B Up

pub fn actcmpbd(&mut self) -> ACTCMPBD_W<'_>

Bits 10:11 - Action for Comparator B Down

impl W<u32, Reg<u32, __0_GENB>>

pub fn actzero(&mut self) -> ACTZERO_W<'_>

Bits 0:1 - Action for Counter=0

pub fn actload(&mut self) -> ACTLOAD_W<'_>

Bits 2:3 - Action for Counter=LOAD

pub fn actcmpau(&mut self) -> ACTCMPAU_W<'_>

Bits 4:5 - Action for Comparator A Up

pub fn actcmpad(&mut self) -> ACTCMPAD_W<'_>

Bits 6:7 - Action for Comparator A Down

pub fn actcmpbu(&mut self) -> ACTCMPBU_W<'_>

Bits 8:9 - Action for Comparator B Up

pub fn actcmpbd(&mut self) -> ACTCMPBD_W<'_>

Bits 10:11 - Action for Comparator B Down

impl W<u32, Reg<u32, __0_DBCTL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Dead-Band Generator Enable

impl W<u32, Reg<u32, __0_DBRISE>>

pub fn delay(&mut self) -> DELAY_W<'_>

Bits 0:11 - Dead-Band Rise Delay

impl W<u32, Reg<u32, __0_DBFALL>>

pub fn delay(&mut self) -> DELAY_W<'_>

Bits 0:11 - Dead-Band Fall Delay

impl W<u32, Reg<u32, __0_FLTSRC0>>

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 0 - Fault0 Input

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 1 - Fault1 Input

impl W<u32, Reg<u32, __0_FLTSRC1>>

pub fn dcmp0(&mut self) -> DCMP0_W<'_>

Bit 0 - Digital Comparator 0

pub fn dcmp1(&mut self) -> DCMP1_W<'_>

Bit 1 - Digital Comparator 1

pub fn dcmp2(&mut self) -> DCMP2_W<'_>

Bit 2 - Digital Comparator 2

pub fn dcmp3(&mut self) -> DCMP3_W<'_>

Bit 3 - Digital Comparator 3

pub fn dcmp4(&mut self) -> DCMP4_W<'_>

Bit 4 - Digital Comparator 4

pub fn dcmp5(&mut self) -> DCMP5_W<'_>

Bit 5 - Digital Comparator 5

pub fn dcmp6(&mut self) -> DCMP6_W<'_>

Bit 6 - Digital Comparator 6

pub fn dcmp7(&mut self) -> DCMP7_W<'_>

Bit 7 - Digital Comparator 7

impl W<u32, Reg<u32, __0_MINFLTPER>>

pub fn minfltper(&mut self) -> MINFLTPER_W<'_>

Bits 0:15 - Minimum Fault Period

impl W<u32, Reg<u32, __1_CTL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - PWM Block Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bit 1 - Counter Mode

pub fn debug(&mut self) -> DEBUG_W<'_>

Bit 2 - Debug Mode

pub fn loadupd(&mut self) -> LOADUPD_W<'_>

Bit 3 - Load Register Update Mode

pub fn cmpaupd(&mut self) -> CMPAUPD_W<'_>

Bit 4 - Comparator A Update Mode

pub fn cmpbupd(&mut self) -> CMPBUPD_W<'_>

Bit 5 - Comparator B Update Mode

pub fn genaupd(&mut self) -> GENAUPD_W<'_>

Bits 6:7 - PWMnGENA Update Mode

pub fn genbupd(&mut self) -> GENBUPD_W<'_>

Bits 8:9 - PWMnGENB Update Mode

pub fn dbctlupd(&mut self) -> DBCTLUPD_W<'_>

Bits 10:11 - PWMnDBCTL Update Mode

pub fn dbriseupd(&mut self) -> DBRISEUPD_W<'_>

Bits 12:13 - PWMnDBRISE Update Mode

pub fn dbfallupd(&mut self) -> DBFALLUPD_W<'_>

Bits 14:15 - PWMnDBFALL Update Mode

pub fn fltsrc(&mut self) -> FLTSRC_W<'_>

Bit 16 - Fault Condition Source

pub fn minfltper(&mut self) -> MINFLTPER_W<'_>

Bit 17 - Minimum Fault Period

pub fn latch(&mut self) -> LATCH_W<'_>

Bit 18 - Latch Fault Input

impl W<u32, Reg<u32, __1_INTEN>>

pub fn intcntzero(&mut self) -> INTCNTZERO_W<'_>

Bit 0 - Interrupt for Counter=0

pub fn intcntload(&mut self) -> INTCNTLOAD_W<'_>

Bit 1 - Interrupt for Counter=PWMnLOAD

pub fn intcmpau(&mut self) -> INTCMPAU_W<'_>

Bit 2 - Interrupt for Counter=PWMnCMPA Up

pub fn intcmpad(&mut self) -> INTCMPAD_W<'_>

Bit 3 - Interrupt for Counter=PWMnCMPA Down

pub fn intcmpbu(&mut self) -> INTCMPBU_W<'_>

Bit 4 - Interrupt for Counter=PWMnCMPB Up

pub fn intcmpbd(&mut self) -> INTCMPBD_W<'_>

Bit 5 - Interrupt for Counter=PWMnCMPB Down

pub fn trcntzero(&mut self) -> TRCNTZERO_W<'_>

Bit 8 - Trigger for Counter=0

pub fn trcntload(&mut self) -> TRCNTLOAD_W<'_>

Bit 9 - Trigger for Counter=PWMnLOAD

pub fn trcmpau(&mut self) -> TRCMPAU_W<'_>

Bit 10 - Trigger for Counter=PWMnCMPA Up

pub fn trcmpad(&mut self) -> TRCMPAD_W<'_>

Bit 11 - Trigger for Counter=PWMnCMPA Down

pub fn trcmpbu(&mut self) -> TRCMPBU_W<'_>

Bit 12 - Trigger for Counter=PWMnCMPB Up

pub fn trcmpbd(&mut self) -> TRCMPBD_W<'_>

Bit 13 - Trigger for Counter=PWMnCMPB Down

impl W<u32, Reg<u32, __1_ISC>>

pub fn intcntzero(&mut self) -> INTCNTZERO_W<'_>

Bit 0 - Counter=0 Interrupt

pub fn intcntload(&mut self) -> INTCNTLOAD_W<'_>

Bit 1 - Counter=Load Interrupt

pub fn intcmpau(&mut self) -> INTCMPAU_W<'_>

Bit 2 - Comparator A Up Interrupt

pub fn intcmpad(&mut self) -> INTCMPAD_W<'_>

Bit 3 - Comparator A Down Interrupt

pub fn intcmpbu(&mut self) -> INTCMPBU_W<'_>

Bit 4 - Comparator B Up Interrupt

pub fn intcmpbd(&mut self) -> INTCMPBD_W<'_>

Bit 5 - Comparator B Down Interrupt

impl W<u32, Reg<u32, __1_LOAD>>

pub fn load(&mut self) -> LOAD_W<'_>

Bits 0:15 - Counter Load Value

impl W<u32, Reg<u32, __1_CMPA>>

pub fn compa(&mut self) -> COMPA_W<'_>

Bits 0:15 - Comparator A Value

impl W<u32, Reg<u32, __1_CMPB>>

pub fn compb(&mut self) -> COMPB_W<'_>

Bits 0:15 - Comparator B Value

impl W<u32, Reg<u32, __1_GENA>>

pub fn actzero(&mut self) -> ACTZERO_W<'_>

Bits 0:1 - Action for Counter=0

pub fn actload(&mut self) -> ACTLOAD_W<'_>

Bits 2:3 - Action for Counter=LOAD

pub fn actcmpau(&mut self) -> ACTCMPAU_W<'_>

Bits 4:5 - Action for Comparator A Up

pub fn actcmpad(&mut self) -> ACTCMPAD_W<'_>

Bits 6:7 - Action for Comparator A Down

pub fn actcmpbu(&mut self) -> ACTCMPBU_W<'_>

Bits 8:9 - Action for Comparator B Up

pub fn actcmpbd(&mut self) -> ACTCMPBD_W<'_>

Bits 10:11 - Action for Comparator B Down

impl W<u32, Reg<u32, __1_GENB>>

pub fn actzero(&mut self) -> ACTZERO_W<'_>

Bits 0:1 - Action for Counter=0

pub fn actload(&mut self) -> ACTLOAD_W<'_>

Bits 2:3 - Action for Counter=LOAD

pub fn actcmpau(&mut self) -> ACTCMPAU_W<'_>

Bits 4:5 - Action for Comparator A Up

pub fn actcmpad(&mut self) -> ACTCMPAD_W<'_>

Bits 6:7 - Action for Comparator A Down

pub fn actcmpbu(&mut self) -> ACTCMPBU_W<'_>

Bits 8:9 - Action for Comparator B Up

pub fn actcmpbd(&mut self) -> ACTCMPBD_W<'_>

Bits 10:11 - Action for Comparator B Down

impl W<u32, Reg<u32, __1_DBCTL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Dead-Band Generator Enable

impl W<u32, Reg<u32, __1_DBRISE>>

pub fn risedelay(&mut self) -> RISEDELAY_W<'_>

Bits 0:11 - Dead-Band Rise Delay

impl W<u32, Reg<u32, __1_DBFALL>>

pub fn falldelay(&mut self) -> FALLDELAY_W<'_>

Bits 0:11 - Dead-Band Fall Delay

impl W<u32, Reg<u32, __1_FLTSRC0>>

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 0 - Fault0 Input

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 1 - Fault1 Input

impl W<u32, Reg<u32, __1_FLTSRC1>>

pub fn dcmp0(&mut self) -> DCMP0_W<'_>

Bit 0 - Digital Comparator 0

pub fn dcmp1(&mut self) -> DCMP1_W<'_>

Bit 1 - Digital Comparator 1

pub fn dcmp2(&mut self) -> DCMP2_W<'_>

Bit 2 - Digital Comparator 2

pub fn dcmp3(&mut self) -> DCMP3_W<'_>

Bit 3 - Digital Comparator 3

pub fn dcmp4(&mut self) -> DCMP4_W<'_>

Bit 4 - Digital Comparator 4

pub fn dcmp5(&mut self) -> DCMP5_W<'_>

Bit 5 - Digital Comparator 5

pub fn dcmp6(&mut self) -> DCMP6_W<'_>

Bit 6 - Digital Comparator 6

pub fn dcmp7(&mut self) -> DCMP7_W<'_>

Bit 7 - Digital Comparator 7

impl W<u32, Reg<u32, __1_MINFLTPER>>

pub fn mfp(&mut self) -> MFP_W<'_>

Bits 0:15 - Minimum Fault Period

impl W<u32, Reg<u32, __2_CTL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - PWM Block Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bit 1 - Counter Mode

pub fn debug(&mut self) -> DEBUG_W<'_>

Bit 2 - Debug Mode

pub fn loadupd(&mut self) -> LOADUPD_W<'_>

Bit 3 - Load Register Update Mode

pub fn cmpaupd(&mut self) -> CMPAUPD_W<'_>

Bit 4 - Comparator A Update Mode

pub fn cmpbupd(&mut self) -> CMPBUPD_W<'_>

Bit 5 - Comparator B Update Mode

pub fn genaupd(&mut self) -> GENAUPD_W<'_>

Bits 6:7 - PWMnGENA Update Mode

pub fn genbupd(&mut self) -> GENBUPD_W<'_>

Bits 8:9 - PWMnGENB Update Mode

pub fn dbctlupd(&mut self) -> DBCTLUPD_W<'_>

Bits 10:11 - PWMnDBCTL Update Mode

pub fn dbriseupd(&mut self) -> DBRISEUPD_W<'_>

Bits 12:13 - PWMnDBRISE Update Mode

pub fn dbfallupd(&mut self) -> DBFALLUPD_W<'_>

Bits 14:15 - PWMnDBFALL Update Mode

pub fn fltsrc(&mut self) -> FLTSRC_W<'_>

Bit 16 - Fault Condition Source

pub fn minfltper(&mut self) -> MINFLTPER_W<'_>

Bit 17 - Minimum Fault Period

pub fn latch(&mut self) -> LATCH_W<'_>

Bit 18 - Latch Fault Input

impl W<u32, Reg<u32, __2_INTEN>>

pub fn intcntzero(&mut self) -> INTCNTZERO_W<'_>

Bit 0 - Interrupt for Counter=0

pub fn intcntload(&mut self) -> INTCNTLOAD_W<'_>

Bit 1 - Interrupt for Counter=PWMnLOAD

pub fn intcmpau(&mut self) -> INTCMPAU_W<'_>

Bit 2 - Interrupt for Counter=PWMnCMPA Up

pub fn intcmpad(&mut self) -> INTCMPAD_W<'_>

Bit 3 - Interrupt for Counter=PWMnCMPA Down

pub fn intcmpbu(&mut self) -> INTCMPBU_W<'_>

Bit 4 - Interrupt for Counter=PWMnCMPB Up

pub fn intcmpbd(&mut self) -> INTCMPBD_W<'_>

Bit 5 - Interrupt for Counter=PWMnCMPB Down

pub fn trcntzero(&mut self) -> TRCNTZERO_W<'_>

Bit 8 - Trigger for Counter=0

pub fn trcntload(&mut self) -> TRCNTLOAD_W<'_>

Bit 9 - Trigger for Counter=PWMnLOAD

pub fn trcmpau(&mut self) -> TRCMPAU_W<'_>

Bit 10 - Trigger for Counter=PWMnCMPA Up

pub fn trcmpad(&mut self) -> TRCMPAD_W<'_>

Bit 11 - Trigger for Counter=PWMnCMPA Down

pub fn trcmpbu(&mut self) -> TRCMPBU_W<'_>

Bit 12 - Trigger for Counter=PWMnCMPB Up

pub fn trcmpbd(&mut self) -> TRCMPBD_W<'_>

Bit 13 - Trigger for Counter=PWMnCMPB Down

impl W<u32, Reg<u32, __2_ISC>>

pub fn intcntzero(&mut self) -> INTCNTZERO_W<'_>

Bit 0 - Counter=0 Interrupt

pub fn intcntload(&mut self) -> INTCNTLOAD_W<'_>

Bit 1 - Counter=Load Interrupt

pub fn intcmpau(&mut self) -> INTCMPAU_W<'_>

Bit 2 - Comparator A Up Interrupt

pub fn intcmpad(&mut self) -> INTCMPAD_W<'_>

Bit 3 - Comparator A Down Interrupt

pub fn intcmpbu(&mut self) -> INTCMPBU_W<'_>

Bit 4 - Comparator B Up Interrupt

pub fn intcmpbd(&mut self) -> INTCMPBD_W<'_>

Bit 5 - Comparator B Down Interrupt

impl W<u32, Reg<u32, __2_LOAD>>

pub fn load(&mut self) -> LOAD_W<'_>

Bits 0:15 - Counter Load Value

impl W<u32, Reg<u32, __2_CMPA>>

pub fn compa(&mut self) -> COMPA_W<'_>

Bits 0:15 - Comparator A Value

impl W<u32, Reg<u32, __2_CMPB>>

pub fn compb(&mut self) -> COMPB_W<'_>

Bits 0:15 - Comparator B Value

impl W<u32, Reg<u32, __2_GENA>>

pub fn actzero(&mut self) -> ACTZERO_W<'_>

Bits 0:1 - Action for Counter=0

pub fn actload(&mut self) -> ACTLOAD_W<'_>

Bits 2:3 - Action for Counter=LOAD

pub fn actcmpau(&mut self) -> ACTCMPAU_W<'_>

Bits 4:5 - Action for Comparator A Up

pub fn actcmpad(&mut self) -> ACTCMPAD_W<'_>

Bits 6:7 - Action for Comparator A Down

pub fn actcmpbu(&mut self) -> ACTCMPBU_W<'_>

Bits 8:9 - Action for Comparator B Up

pub fn actcmpbd(&mut self) -> ACTCMPBD_W<'_>

Bits 10:11 - Action for Comparator B Down

impl W<u32, Reg<u32, __2_GENB>>

pub fn actzero(&mut self) -> ACTZERO_W<'_>

Bits 0:1 - Action for Counter=0

pub fn actload(&mut self) -> ACTLOAD_W<'_>

Bits 2:3 - Action for Counter=LOAD

pub fn actcmpau(&mut self) -> ACTCMPAU_W<'_>

Bits 4:5 - Action for Comparator A Up

pub fn actcmpad(&mut self) -> ACTCMPAD_W<'_>

Bits 6:7 - Action for Comparator A Down

pub fn actcmpbu(&mut self) -> ACTCMPBU_W<'_>

Bits 8:9 - Action for Comparator B Up

pub fn actcmpbd(&mut self) -> ACTCMPBD_W<'_>

Bits 10:11 - Action for Comparator B Down

impl W<u32, Reg<u32, __2_DBCTL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Dead-Band Generator Enable

impl W<u32, Reg<u32, __2_DBRISE>>

pub fn risedelay(&mut self) -> RISEDELAY_W<'_>

Bits 0:11 - Dead-Band Rise Delay

impl W<u32, Reg<u32, __2_DBFALL>>

pub fn falldelay(&mut self) -> FALLDELAY_W<'_>

Bits 0:11 - Dead-Band Fall Delay

impl W<u32, Reg<u32, __2_FLTSRC0>>

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 0 - Fault0 Input

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 1 - Fault1 Input

impl W<u32, Reg<u32, __2_FLTSRC1>>

pub fn dcmp0(&mut self) -> DCMP0_W<'_>

Bit 0 - Digital Comparator 0

pub fn dcmp1(&mut self) -> DCMP1_W<'_>

Bit 1 - Digital Comparator 1

pub fn dcmp2(&mut self) -> DCMP2_W<'_>

Bit 2 - Digital Comparator 2

pub fn dcmp3(&mut self) -> DCMP3_W<'_>

Bit 3 - Digital Comparator 3

pub fn dcmp4(&mut self) -> DCMP4_W<'_>

Bit 4 - Digital Comparator 4

pub fn dcmp5(&mut self) -> DCMP5_W<'_>

Bit 5 - Digital Comparator 5

pub fn dcmp6(&mut self) -> DCMP6_W<'_>

Bit 6 - Digital Comparator 6

pub fn dcmp7(&mut self) -> DCMP7_W<'_>

Bit 7 - Digital Comparator 7

impl W<u32, Reg<u32, __2_MINFLTPER>>

pub fn mfp(&mut self) -> MFP_W<'_>

Bits 0:15 - Minimum Fault Period

impl W<u32, Reg<u32, __3_CTL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - PWM Block Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bit 1 - Counter Mode

pub fn debug(&mut self) -> DEBUG_W<'_>

Bit 2 - Debug Mode

pub fn loadupd(&mut self) -> LOADUPD_W<'_>

Bit 3 - Load Register Update Mode

pub fn cmpaupd(&mut self) -> CMPAUPD_W<'_>

Bit 4 - Comparator A Update Mode

pub fn cmpbupd(&mut self) -> CMPBUPD_W<'_>

Bit 5 - Comparator B Update Mode

pub fn genaupd(&mut self) -> GENAUPD_W<'_>

Bits 6:7 - PWMnGENA Update Mode

pub fn genbupd(&mut self) -> GENBUPD_W<'_>

Bits 8:9 - PWMnGENB Update Mode

pub fn dbctlupd(&mut self) -> DBCTLUPD_W<'_>

Bits 10:11 - PWMnDBCTL Update Mode

pub fn dbriseupd(&mut self) -> DBRISEUPD_W<'_>

Bits 12:13 - PWMnDBRISE Update Mode

pub fn dbfallupd(&mut self) -> DBFALLUPD_W<'_>

Bits 14:15 - PWMnDBFALL Update Mode

pub fn fltsrc(&mut self) -> FLTSRC_W<'_>

Bit 16 - Fault Condition Source

pub fn minfltper(&mut self) -> MINFLTPER_W<'_>

Bit 17 - Minimum Fault Period

pub fn latch(&mut self) -> LATCH_W<'_>

Bit 18 - Latch Fault Input

impl W<u32, Reg<u32, __3_INTEN>>

pub fn intcntzero(&mut self) -> INTCNTZERO_W<'_>

Bit 0 - Interrupt for Counter=0

pub fn intcntload(&mut self) -> INTCNTLOAD_W<'_>

Bit 1 - Interrupt for Counter=PWMnLOAD

pub fn intcmpau(&mut self) -> INTCMPAU_W<'_>

Bit 2 - Interrupt for Counter=PWMnCMPA Up

pub fn intcmpad(&mut self) -> INTCMPAD_W<'_>

Bit 3 - Interrupt for Counter=PWMnCMPA Down

pub fn intcmpbu(&mut self) -> INTCMPBU_W<'_>

Bit 4 - Interrupt for Counter=PWMnCMPB Up

pub fn intcmpbd(&mut self) -> INTCMPBD_W<'_>

Bit 5 - Interrupt for Counter=PWMnCMPB Down

pub fn trcntzero(&mut self) -> TRCNTZERO_W<'_>

Bit 8 - Trigger for Counter=0

pub fn trcntload(&mut self) -> TRCNTLOAD_W<'_>

Bit 9 - Trigger for Counter=PWMnLOAD

pub fn trcmpau(&mut self) -> TRCMPAU_W<'_>

Bit 10 - Trigger for Counter=PWMnCMPA Up

pub fn trcmpad(&mut self) -> TRCMPAD_W<'_>

Bit 11 - Trigger for Counter=PWMnCMPA Down

pub fn trcmpbu(&mut self) -> TRCMPBU_W<'_>

Bit 12 - Trigger for Counter=PWMnCMPB Up

pub fn trcmpbd(&mut self) -> TRCMPBD_W<'_>

Bit 13 - Trigger for Counter=PWMnCMPB Down

impl W<u32, Reg<u32, __3_ISC>>

pub fn intcntzero(&mut self) -> INTCNTZERO_W<'_>

Bit 0 - Counter=0 Interrupt

pub fn intcntload(&mut self) -> INTCNTLOAD_W<'_>

Bit 1 - Counter=Load Interrupt

pub fn intcmpau(&mut self) -> INTCMPAU_W<'_>

Bit 2 - Comparator A Up Interrupt

pub fn intcmpad(&mut self) -> INTCMPAD_W<'_>

Bit 3 - Comparator A Down Interrupt

pub fn intcmpbu(&mut self) -> INTCMPBU_W<'_>

Bit 4 - Comparator B Up Interrupt

pub fn intcmpbd(&mut self) -> INTCMPBD_W<'_>

Bit 5 - Comparator B Down Interrupt

impl W<u32, Reg<u32, __3_LOAD>>

pub fn load(&mut self) -> LOAD_W<'_>

Bits 0:15 - Counter Load Value

impl W<u32, Reg<u32, __3_CMPA>>

pub fn compa(&mut self) -> COMPA_W<'_>

Bits 0:15 - Comparator A Value

impl W<u32, Reg<u32, __3_CMPB>>

pub fn compb(&mut self) -> COMPB_W<'_>

Bits 0:15 - Comparator B Value

impl W<u32, Reg<u32, __3_GENA>>

pub fn actzero(&mut self) -> ACTZERO_W<'_>

Bits 0:1 - Action for Counter=0

pub fn actload(&mut self) -> ACTLOAD_W<'_>

Bits 2:3 - Action for Counter=LOAD

pub fn actcmpau(&mut self) -> ACTCMPAU_W<'_>

Bits 4:5 - Action for Comparator A Up

pub fn actcmpad(&mut self) -> ACTCMPAD_W<'_>

Bits 6:7 - Action for Comparator A Down

pub fn actcmpbu(&mut self) -> ACTCMPBU_W<'_>

Bits 8:9 - Action for Comparator B Up

pub fn actcmpbd(&mut self) -> ACTCMPBD_W<'_>

Bits 10:11 - Action for Comparator B Down

impl W<u32, Reg<u32, __3_GENB>>

pub fn actzero(&mut self) -> ACTZERO_W<'_>

Bits 0:1 - Action for Counter=0

pub fn actload(&mut self) -> ACTLOAD_W<'_>

Bits 2:3 - Action for Counter=LOAD

pub fn actcmpau(&mut self) -> ACTCMPAU_W<'_>

Bits 4:5 - Action for Comparator A Up

pub fn actcmpad(&mut self) -> ACTCMPAD_W<'_>

Bits 6:7 - Action for Comparator A Down

pub fn actcmpbu(&mut self) -> ACTCMPBU_W<'_>

Bits 8:9 - Action for Comparator B Up

pub fn actcmpbd(&mut self) -> ACTCMPBD_W<'_>

Bits 10:11 - Action for Comparator B Down

impl W<u32, Reg<u32, __3_DBCTL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Dead-Band Generator Enable

impl W<u32, Reg<u32, __3_DBRISE>>

pub fn risedelay(&mut self) -> RISEDELAY_W<'_>

Bits 0:11 - Dead-Band Rise Delay

impl W<u32, Reg<u32, __3_DBFALL>>

pub fn falldelay(&mut self) -> FALLDELAY_W<'_>

Bits 0:11 - Dead-Band Fall Delay

impl W<u32, Reg<u32, __3_FLTSRC0>>

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 0 - Fault0 Input

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 1 - Fault1 Input

impl W<u32, Reg<u32, __3_FLTSRC1>>

pub fn dcmp0(&mut self) -> DCMP0_W<'_>

Bit 0 - Digital Comparator 0

pub fn dcmp1(&mut self) -> DCMP1_W<'_>

Bit 1 - Digital Comparator 1

pub fn dcmp2(&mut self) -> DCMP2_W<'_>

Bit 2 - Digital Comparator 2

pub fn dcmp3(&mut self) -> DCMP3_W<'_>

Bit 3 - Digital Comparator 3

pub fn dcmp4(&mut self) -> DCMP4_W<'_>

Bit 4 - Digital Comparator 4

pub fn dcmp5(&mut self) -> DCMP5_W<'_>

Bit 5 - Digital Comparator 5

pub fn dcmp6(&mut self) -> DCMP6_W<'_>

Bit 6 - Digital Comparator 6

pub fn dcmp7(&mut self) -> DCMP7_W<'_>

Bit 7 - Digital Comparator 7

impl W<u32, Reg<u32, __3_MINFLTPER>>

pub fn mfp(&mut self) -> MFP_W<'_>

Bits 0:15 - Minimum Fault Period

impl W<u32, Reg<u32, __0_FLTSEN>>

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 0 - Fault0 Sense

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 1 - Fault1 Sense

impl W<u32, Reg<u32, __0_FLTSTAT0>>

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 0 - Fault Input 0

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 1 - Fault Input 1

impl W<u32, Reg<u32, __0_FLTSTAT1>>

pub fn dcmp0(&mut self) -> DCMP0_W<'_>

Bit 0 - Digital Comparator 0 Trigger

pub fn dcmp1(&mut self) -> DCMP1_W<'_>

Bit 1 - Digital Comparator 1 Trigger

pub fn dcmp2(&mut self) -> DCMP2_W<'_>

Bit 2 - Digital Comparator 2 Trigger

pub fn dcmp3(&mut self) -> DCMP3_W<'_>

Bit 3 - Digital Comparator 3 Trigger

pub fn dcmp4(&mut self) -> DCMP4_W<'_>

Bit 4 - Digital Comparator 4 Trigger

pub fn dcmp5(&mut self) -> DCMP5_W<'_>

Bit 5 - Digital Comparator 5 Trigger

pub fn dcmp6(&mut self) -> DCMP6_W<'_>

Bit 6 - Digital Comparator 6 Trigger

pub fn dcmp7(&mut self) -> DCMP7_W<'_>

Bit 7 - Digital Comparator 7 Trigger

impl W<u32, Reg<u32, __1_FLTSEN>>

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 0 - Fault0 Sense

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 1 - Fault1 Sense

impl W<u32, Reg<u32, __1_FLTSTAT0>>

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 0 - Fault Input 0

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 1 - Fault Input 1

impl W<u32, Reg<u32, __1_FLTSTAT1>>

pub fn dcmp0(&mut self) -> DCMP0_W<'_>

Bit 0 - Digital Comparator 0 Trigger

pub fn dcmp1(&mut self) -> DCMP1_W<'_>

Bit 1 - Digital Comparator 1 Trigger

pub fn dcmp2(&mut self) -> DCMP2_W<'_>

Bit 2 - Digital Comparator 2 Trigger

pub fn dcmp3(&mut self) -> DCMP3_W<'_>

Bit 3 - Digital Comparator 3 Trigger

pub fn dcmp4(&mut self) -> DCMP4_W<'_>

Bit 4 - Digital Comparator 4 Trigger

pub fn dcmp5(&mut self) -> DCMP5_W<'_>

Bit 5 - Digital Comparator 5 Trigger

pub fn dcmp6(&mut self) -> DCMP6_W<'_>

Bit 6 - Digital Comparator 6 Trigger

pub fn dcmp7(&mut self) -> DCMP7_W<'_>

Bit 7 - Digital Comparator 7 Trigger

impl W<u32, Reg<u32, __2_FLTSTAT0>>

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 0 - Fault Input 0

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 1 - Fault Input 1

impl W<u32, Reg<u32, __2_FLTSTAT1>>

pub fn dcmp0(&mut self) -> DCMP0_W<'_>

Bit 0 - Digital Comparator 0 Trigger

pub fn dcmp1(&mut self) -> DCMP1_W<'_>

Bit 1 - Digital Comparator 1 Trigger

pub fn dcmp2(&mut self) -> DCMP2_W<'_>

Bit 2 - Digital Comparator 2 Trigger

pub fn dcmp3(&mut self) -> DCMP3_W<'_>

Bit 3 - Digital Comparator 3 Trigger

pub fn dcmp4(&mut self) -> DCMP4_W<'_>

Bit 4 - Digital Comparator 4 Trigger

pub fn dcmp5(&mut self) -> DCMP5_W<'_>

Bit 5 - Digital Comparator 5 Trigger

pub fn dcmp6(&mut self) -> DCMP6_W<'_>

Bit 6 - Digital Comparator 6 Trigger

pub fn dcmp7(&mut self) -> DCMP7_W<'_>

Bit 7 - Digital Comparator 7 Trigger

impl W<u32, Reg<u32, __3_FLTSTAT0>>

pub fn fault0(&mut self) -> FAULT0_W<'_>

Bit 0 - Fault Input 0

pub fn fault1(&mut self) -> FAULT1_W<'_>

Bit 1 - Fault Input 1

impl W<u32, Reg<u32, __3_FLTSTAT1>>

pub fn dcmp0(&mut self) -> DCMP0_W<'_>

Bit 0 - Digital Comparator 0 Trigger

pub fn dcmp1(&mut self) -> DCMP1_W<'_>

Bit 1 - Digital Comparator 1 Trigger

pub fn dcmp2(&mut self) -> DCMP2_W<'_>

Bit 2 - Digital Comparator 2 Trigger

pub fn dcmp3(&mut self) -> DCMP3_W<'_>

Bit 3 - Digital Comparator 3 Trigger

pub fn dcmp4(&mut self) -> DCMP4_W<'_>

Bit 4 - Digital Comparator 4 Trigger

pub fn dcmp5(&mut self) -> DCMP5_W<'_>

Bit 5 - Digital Comparator 5 Trigger

pub fn dcmp6(&mut self) -> DCMP6_W<'_>

Bit 6 - Digital Comparator 6 Trigger

pub fn dcmp7(&mut self) -> DCMP7_W<'_>

Bit 7 - Digital Comparator 7 Trigger

impl W<u32, Reg<u32, _CTL>>

pub fn enable(&mut self) -> ENABLE_W<'_>

Bit 0 - Enable QEI

pub fn swap(&mut self) -> SWAP_W<'_>

Bit 1 - Swap Signals

pub fn sigmode(&mut self) -> SIGMODE_W<'_>

Bit 2 - Signal Mode

pub fn capmode(&mut self) -> CAPMODE_W<'_>

Bit 3 - Capture Mode

pub fn resmode(&mut self) -> RESMODE_W<'_>

Bit 4 - Reset Mode

pub fn velen(&mut self) -> VELEN_W<'_>

Bit 5 - Capture Velocity

pub fn veldiv(&mut self) -> VELDIV_W<'_>

Bits 6:8 - Predivide Velocity

pub fn inva(&mut self) -> INVA_W<'_>

Bit 9 - Invert PhA

pub fn invb(&mut self) -> INVB_W<'_>

Bit 10 - Invert PhB

pub fn invi(&mut self) -> INVI_W<'_>

Bit 11 - Invert Index Pulse

pub fn stallen(&mut self) -> STALLEN_W<'_>

Bit 12 - Stall QEI

pub fn filten(&mut self) -> FILTEN_W<'_>

Bit 13 - Enable Input Filter

pub fn filtcnt(&mut self) -> FILTCNT_W<'_>

Bits 16:19 - Input Filter Prescale Count

impl W<u32, Reg<u32, _INTEN>>

pub fn index(&mut self) -> INDEX_W<'_>

Bit 0 - Index Pulse Detected Interrupt Enable

pub fn timer(&mut self) -> TIMER_W<'_>

Bit 1 - Timer Expires Interrupt Enable

pub fn dir(&mut self) -> DIR_W<'_>

Bit 2 - Direction Change Interrupt Enable

pub fn error(&mut self) -> ERROR_W<'_>

Bit 3 - Phase Error Interrupt Enable

impl W<u32, Reg<u32, _ISC>>

pub fn index(&mut self) -> INDEX_W<'_>

Bit 0 - Index Pulse Interrupt

pub fn timer(&mut self) -> TIMER_W<'_>

Bit 1 - Velocity Timer Expired Interrupt

pub fn dir(&mut self) -> DIR_W<'_>

Bit 2 - Direction Change Interrupt

pub fn error(&mut self) -> ERROR_W<'_>

Bit 3 - Phase Error Interrupt

impl W<u32, Reg<u32, _CFG>>

pub fn cfg(&mut self) -> CFG_W<'_>

Bits 0:2 - GPTM Configuration

impl W<u32, Reg<u32, _TAMR>>

pub fn tamr(&mut self) -> TAMR_W<'_>

Bits 0:1 - GPTM Timer A Mode

pub fn tacmr(&mut self) -> TACMR_W<'_>

Bit 2 - GPTM Timer A Capture Mode

pub fn taams(&mut self) -> TAAMS_W<'_>

Bit 3 - GPTM Timer A Alternate Mode Select

pub fn tacdir(&mut self) -> TACDIR_W<'_>

Bit 4 - GPTM Timer A Count Direction

pub fn tamie(&mut self) -> TAMIE_W<'_>

Bit 5 - GPTM Timer A Match Interrupt Enable

pub fn tawot(&mut self) -> TAWOT_W<'_>

Bit 6 - GPTM Timer A Wait-on-Trigger

pub fn tasnaps(&mut self) -> TASNAPS_W<'_>

Bit 7 - GPTM Timer A Snap-Shot Mode

pub fn taild(&mut self) -> TAILD_W<'_>

Bit 8 - GPTM Timer A Interval Load Write

pub fn tapwmie(&mut self) -> TAPWMIE_W<'_>

Bit 9 - GPTM Timer A PWM Interrupt Enable

pub fn tamrsu(&mut self) -> TAMRSU_W<'_>

Bit 10 - GPTM Timer A Match Register Update

pub fn taplo(&mut self) -> TAPLO_W<'_>

Bit 11 - GPTM Timer A PWM Legacy Operation

impl W<u32, Reg<u32, _TBMR>>

pub fn tbmr(&mut self) -> TBMR_W<'_>

Bits 0:1 - GPTM Timer B Mode

pub fn tbcmr(&mut self) -> TBCMR_W<'_>

Bit 2 - GPTM Timer B Capture Mode

pub fn tbams(&mut self) -> TBAMS_W<'_>

Bit 3 - GPTM Timer B Alternate Mode Select

pub fn tbcdir(&mut self) -> TBCDIR_W<'_>

Bit 4 - GPTM Timer B Count Direction

pub fn tbmie(&mut self) -> TBMIE_W<'_>

Bit 5 - GPTM Timer B Match Interrupt Enable

pub fn tbwot(&mut self) -> TBWOT_W<'_>

Bit 6 - GPTM Timer B Wait-on-Trigger

pub fn tbsnaps(&mut self) -> TBSNAPS_W<'_>

Bit 7 - GPTM Timer B Snap-Shot Mode

pub fn tbild(&mut self) -> TBILD_W<'_>

Bit 8 - GPTM Timer B Interval Load Write

pub fn tbpwmie(&mut self) -> TBPWMIE_W<'_>

Bit 9 - GPTM Timer B PWM Interrupt Enable

pub fn tbmrsu(&mut self) -> TBMRSU_W<'_>

Bit 10 - GPTM Timer B Match Register Update

pub fn tbplo(&mut self) -> TBPLO_W<'_>

Bit 11 - GPTM Timer B PWM Legacy Operation

impl W<u32, Reg<u32, _CTL>>

pub fn taen(&mut self) -> TAEN_W<'_>

Bit 0 - GPTM Timer A Enable

pub fn tastall(&mut self) -> TASTALL_W<'_>

Bit 1 - GPTM Timer A Stall Enable

pub fn taevent(&mut self) -> TAEVENT_W<'_>

Bits 2:3 - GPTM Timer A Event Mode

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 4 - GPTM RTC Stall Enable

pub fn taote(&mut self) -> TAOTE_W<'_>

Bit 5 - GPTM Timer A Output Trigger Enable

pub fn tapwml(&mut self) -> TAPWML_W<'_>

Bit 6 - GPTM Timer A PWM Output Level

pub fn tben(&mut self) -> TBEN_W<'_>

Bit 8 - GPTM Timer B Enable

pub fn tbstall(&mut self) -> TBSTALL_W<'_>

Bit 9 - GPTM Timer B Stall Enable

pub fn tbevent(&mut self) -> TBEVENT_W<'_>

Bits 10:11 - GPTM Timer B Event Mode

pub fn tbote(&mut self) -> TBOTE_W<'_>

Bit 13 - GPTM Timer B Output Trigger Enable

pub fn tbpwml(&mut self) -> TBPWML_W<'_>

Bit 14 - GPTM Timer B PWM Output Level

impl W<u32, Reg<u32, _SYNC>>

pub fn synct0(&mut self) -> SYNCT0_W<'_>

Bits 0:1 - Synchronize GPTM Timer 0

pub fn synct1(&mut self) -> SYNCT1_W<'_>

Bits 2:3 - Synchronize GPTM Timer 1

pub fn synct2(&mut self) -> SYNCT2_W<'_>

Bits 4:5 - Synchronize GPTM Timer 2

pub fn synct3(&mut self) -> SYNCT3_W<'_>

Bits 6:7 - Synchronize GPTM Timer 3

pub fn synct4(&mut self) -> SYNCT4_W<'_>

Bits 8:9 - Synchronize GPTM Timer 4

pub fn synct5(&mut self) -> SYNCT5_W<'_>

Bits 10:11 - Synchronize GPTM Timer 5

pub fn syncwt0(&mut self) -> SYNCWT0_W<'_>

Bits 12:13 - Synchronize GPTM 32/64-Bit Timer 0

pub fn syncwt1(&mut self) -> SYNCWT1_W<'_>

Bits 14:15 - Synchronize GPTM 32/64-Bit Timer 1

pub fn syncwt2(&mut self) -> SYNCWT2_W<'_>

Bits 16:17 - Synchronize GPTM 32/64-Bit Timer 2

pub fn syncwt3(&mut self) -> SYNCWT3_W<'_>

Bits 18:19 - Synchronize GPTM 32/64-Bit Timer 3

pub fn syncwt4(&mut self) -> SYNCWT4_W<'_>

Bits 20:21 - Synchronize GPTM 32/64-Bit Timer 4

pub fn syncwt5(&mut self) -> SYNCWT5_W<'_>

Bits 22:23 - Synchronize GPTM 32/64-Bit Timer 5

impl W<u32, Reg<u32, _IMR>>

pub fn tatoim(&mut self) -> TATOIM_W<'_>

Bit 0 - GPTM Timer A Time-Out Interrupt Mask

pub fn camim(&mut self) -> CAMIM_W<'_>

Bit 1 - GPTM Timer A Capture Mode Match Interrupt Mask

pub fn caeim(&mut self) -> CAEIM_W<'_>

Bit 2 - GPTM Timer A Capture Mode Event Interrupt Mask

pub fn rtcim(&mut self) -> RTCIM_W<'_>

Bit 3 - GPTM RTC Interrupt Mask

pub fn tamim(&mut self) -> TAMIM_W<'_>

Bit 4 - GPTM Timer A Match Interrupt Mask

pub fn tbtoim(&mut self) -> TBTOIM_W<'_>

Bit 8 - GPTM Timer B Time-Out Interrupt Mask

pub fn cbmim(&mut self) -> CBMIM_W<'_>

Bit 9 - GPTM Timer B Capture Mode Match Interrupt Mask

pub fn cbeim(&mut self) -> CBEIM_W<'_>

Bit 10 - GPTM Timer B Capture Mode Event Interrupt Mask

pub fn tbmim(&mut self) -> TBMIM_W<'_>

Bit 11 - GPTM Timer B Match Interrupt Mask

pub fn wueim(&mut self) -> WUEIM_W<'_>

Bit 16 - 32/64-Bit Wide GPTM Write Update Error Interrupt Mask

impl W<u32, Reg<u32, _ICR>>

pub fn tatocint(&mut self) -> TATOCINT_W<'_>

Bit 0 - GPTM Timer A Time-Out Raw Interrupt

pub fn camcint(&mut self) -> CAMCINT_W<'_>

Bit 1 - GPTM Timer A Capture Mode Match Interrupt Clear

pub fn caecint(&mut self) -> CAECINT_W<'_>

Bit 2 - GPTM Timer A Capture Mode Event Interrupt Clear

pub fn rtccint(&mut self) -> RTCCINT_W<'_>

Bit 3 - GPTM RTC Interrupt Clear

pub fn tamcint(&mut self) -> TAMCINT_W<'_>

Bit 4 - GPTM Timer A Match Interrupt Clear

pub fn tbtocint(&mut self) -> TBTOCINT_W<'_>

Bit 8 - GPTM Timer B Time-Out Interrupt Clear

pub fn cbmcint(&mut self) -> CBMCINT_W<'_>

Bit 9 - GPTM Timer B Capture Mode Match Interrupt Clear

pub fn cbecint(&mut self) -> CBECINT_W<'_>

Bit 10 - GPTM Timer B Capture Mode Event Interrupt Clear

pub fn tbmcint(&mut self) -> TBMCINT_W<'_>

Bit 11 - GPTM Timer B Match Interrupt Clear

pub fn wuecint(&mut self) -> WUECINT_W<'_>

Bit 16 - 32/64-Bit Wide GPTM Write Update Error Interrupt Clear

impl W<u32, Reg<u32, _TAMATCHR>>

pub fn tamr(&mut self) -> TAMR_W<'_>

Bits 0:31 - GPTM Timer A Match Register

impl W<u32, Reg<u32, _TBMATCHR>>

pub fn tbmr(&mut self) -> TBMR_W<'_>

Bits 0:31 - GPTM Timer B Match Register

impl W<u32, Reg<u32, _TAPR>>

pub fn tapsr(&mut self) -> TAPSR_W<'_>

Bits 0:7 - GPTM Timer A Prescale

pub fn tapsrh(&mut self) -> TAPSRH_W<'_>

Bits 8:15 - GPTM Timer A Prescale High Byte

impl W<u32, Reg<u32, _TBPR>>

pub fn tbpsr(&mut self) -> TBPSR_W<'_>

Bits 0:7 - GPTM Timer B Prescale

pub fn tbpsrh(&mut self) -> TBPSRH_W<'_>

Bits 8:15 - GPTM Timer B Prescale High Byte

impl W<u32, Reg<u32, _TAPMR>>

pub fn tapsmr(&mut self) -> TAPSMR_W<'_>

Bits 0:7 - GPTM TimerA Prescale Match

pub fn tapsmrh(&mut self) -> TAPSMRH_W<'_>

Bits 8:15 - GPTM Timer A Prescale Match High Byte

impl W<u32, Reg<u32, _TBPMR>>

pub fn tbpsmr(&mut self) -> TBPSMR_W<'_>

Bits 0:7 - GPTM TimerB Prescale Match

pub fn tbpsmrh(&mut self) -> TBPSMRH_W<'_>

Bits 8:15 - GPTM Timer B Prescale Match High Byte

impl W<u32, Reg<u32, _CFG>>

pub fn cfg(&mut self) -> CFG_W<'_>

Bits 0:2 - GPTM Configuration

impl W<u32, Reg<u32, _TAMR>>

pub fn tamr(&mut self) -> TAMR_W<'_>

Bits 0:1 - GPTM Timer A Mode

pub fn tacmr(&mut self) -> TACMR_W<'_>

Bit 2 - GPTM Timer A Capture Mode

pub fn taams(&mut self) -> TAAMS_W<'_>

Bit 3 - GPTM Timer A Alternate Mode Select

pub fn tacdir(&mut self) -> TACDIR_W<'_>

Bit 4 - GPTM Timer A Count Direction

pub fn tamie(&mut self) -> TAMIE_W<'_>

Bit 5 - GPTM Timer A Match Interrupt Enable

pub fn tawot(&mut self) -> TAWOT_W<'_>

Bit 6 - GPTM Timer A Wait-on-Trigger

pub fn tasnaps(&mut self) -> TASNAPS_W<'_>

Bit 7 - GPTM Timer A Snap-Shot Mode

pub fn taild(&mut self) -> TAILD_W<'_>

Bit 8 - GPTM Timer A Interval Load Write

pub fn tapwmie(&mut self) -> TAPWMIE_W<'_>

Bit 9 - GPTM Timer A PWM Interrupt Enable

pub fn tamrsu(&mut self) -> TAMRSU_W<'_>

Bit 10 - GPTM Timer A Match Register Update

pub fn taplo(&mut self) -> TAPLO_W<'_>

Bit 11 - GPTM Timer A PWM Legacy Operation

impl W<u32, Reg<u32, _TBMR>>

pub fn tbmr(&mut self) -> TBMR_W<'_>

Bits 0:1 - GPTM Timer B Mode

pub fn tbcmr(&mut self) -> TBCMR_W<'_>

Bit 2 - GPTM Timer B Capture Mode

pub fn tbams(&mut self) -> TBAMS_W<'_>

Bit 3 - GPTM Timer B Alternate Mode Select

pub fn tbcdir(&mut self) -> TBCDIR_W<'_>

Bit 4 - GPTM Timer B Count Direction

pub fn tbmie(&mut self) -> TBMIE_W<'_>

Bit 5 - GPTM Timer B Match Interrupt Enable

pub fn tbwot(&mut self) -> TBWOT_W<'_>

Bit 6 - GPTM Timer B Wait-on-Trigger

pub fn tbsnaps(&mut self) -> TBSNAPS_W<'_>

Bit 7 - GPTM Timer B Snap-Shot Mode

pub fn tbild(&mut self) -> TBILD_W<'_>

Bit 8 - GPTM Timer B Interval Load Write

pub fn tbpwmie(&mut self) -> TBPWMIE_W<'_>

Bit 9 - GPTM Timer B PWM Interrupt Enable

pub fn tbmrsu(&mut self) -> TBMRSU_W<'_>

Bit 10 - GPTM Timer B Match Register Update

pub fn tbplo(&mut self) -> TBPLO_W<'_>

Bit 11 - GPTM Timer B PWM Legacy Operation

impl W<u32, Reg<u32, _CTL>>

pub fn taen(&mut self) -> TAEN_W<'_>

Bit 0 - GPTM Timer A Enable

pub fn tastall(&mut self) -> TASTALL_W<'_>

Bit 1 - GPTM Timer A Stall Enable

pub fn taevent(&mut self) -> TAEVENT_W<'_>

Bits 2:3 - GPTM Timer A Event Mode

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 4 - GPTM RTC Stall Enable

pub fn taote(&mut self) -> TAOTE_W<'_>

Bit 5 - GPTM Timer A Output Trigger Enable

pub fn tapwml(&mut self) -> TAPWML_W<'_>

Bit 6 - GPTM Timer A PWM Output Level

pub fn tben(&mut self) -> TBEN_W<'_>

Bit 8 - GPTM Timer B Enable

pub fn tbstall(&mut self) -> TBSTALL_W<'_>

Bit 9 - GPTM Timer B Stall Enable

pub fn tbevent(&mut self) -> TBEVENT_W<'_>

Bits 10:11 - GPTM Timer B Event Mode

pub fn tbote(&mut self) -> TBOTE_W<'_>

Bit 13 - GPTM Timer B Output Trigger Enable

pub fn tbpwml(&mut self) -> TBPWML_W<'_>

Bit 14 - GPTM Timer B PWM Output Level

impl W<u32, Reg<u32, _SYNC>>

pub fn synct0(&mut self) -> SYNCT0_W<'_>

Bits 0:1 - Synchronize GPTM Timer 0

pub fn synct1(&mut self) -> SYNCT1_W<'_>

Bits 2:3 - Synchronize GPTM Timer 1

pub fn synct2(&mut self) -> SYNCT2_W<'_>

Bits 4:5 - Synchronize GPTM Timer 2

pub fn synct3(&mut self) -> SYNCT3_W<'_>

Bits 6:7 - Synchronize GPTM Timer 3

pub fn synct4(&mut self) -> SYNCT4_W<'_>

Bits 8:9 - Synchronize GPTM Timer 4

pub fn synct5(&mut self) -> SYNCT5_W<'_>

Bits 10:11 - Synchronize GPTM Timer 5

pub fn syncwt0(&mut self) -> SYNCWT0_W<'_>

Bits 12:13 - Synchronize GPTM 32/64-Bit Timer 0

pub fn syncwt1(&mut self) -> SYNCWT1_W<'_>

Bits 14:15 - Synchronize GPTM 32/64-Bit Timer 1

pub fn syncwt2(&mut self) -> SYNCWT2_W<'_>

Bits 16:17 - Synchronize GPTM 32/64-Bit Timer 2

pub fn syncwt3(&mut self) -> SYNCWT3_W<'_>

Bits 18:19 - Synchronize GPTM 32/64-Bit Timer 3

pub fn syncwt4(&mut self) -> SYNCWT4_W<'_>

Bits 20:21 - Synchronize GPTM 32/64-Bit Timer 4

pub fn syncwt5(&mut self) -> SYNCWT5_W<'_>

Bits 22:23 - Synchronize GPTM 32/64-Bit Timer 5

impl W<u32, Reg<u32, _IMR>>

pub fn tatoim(&mut self) -> TATOIM_W<'_>

Bit 0 - GPTM Timer A Time-Out Interrupt Mask

pub fn camim(&mut self) -> CAMIM_W<'_>

Bit 1 - GPTM Timer A Capture Mode Match Interrupt Mask

pub fn caeim(&mut self) -> CAEIM_W<'_>

Bit 2 - GPTM Timer A Capture Mode Event Interrupt Mask

pub fn rtcim(&mut self) -> RTCIM_W<'_>

Bit 3 - GPTM RTC Interrupt Mask

pub fn tamim(&mut self) -> TAMIM_W<'_>

Bit 4 - GPTM Timer A Match Interrupt Mask

pub fn tbtoim(&mut self) -> TBTOIM_W<'_>

Bit 8 - GPTM Timer B Time-Out Interrupt Mask

pub fn cbmim(&mut self) -> CBMIM_W<'_>

Bit 9 - GPTM Timer B Capture Mode Match Interrupt Mask

pub fn cbeim(&mut self) -> CBEIM_W<'_>

Bit 10 - GPTM Timer B Capture Mode Event Interrupt Mask

pub fn tbmim(&mut self) -> TBMIM_W<'_>

Bit 11 - GPTM Timer B Match Interrupt Mask

pub fn wueim(&mut self) -> WUEIM_W<'_>

Bit 16 - 32/64-Bit Wide GPTM Write Update Error Interrupt Mask

impl W<u32, Reg<u32, _ICR>>

pub fn tatocint(&mut self) -> TATOCINT_W<'_>

Bit 0 - GPTM Timer A Time-Out Raw Interrupt

pub fn camcint(&mut self) -> CAMCINT_W<'_>

Bit 1 - GPTM Timer A Capture Mode Match Interrupt Clear

pub fn caecint(&mut self) -> CAECINT_W<'_>

Bit 2 - GPTM Timer A Capture Mode Event Interrupt Clear

pub fn rtccint(&mut self) -> RTCCINT_W<'_>

Bit 3 - GPTM RTC Interrupt Clear

pub fn tamcint(&mut self) -> TAMCINT_W<'_>

Bit 4 - GPTM Timer A Match Interrupt Clear

pub fn tbtocint(&mut self) -> TBTOCINT_W<'_>

Bit 8 - GPTM Timer B Time-Out Interrupt Clear

pub fn cbmcint(&mut self) -> CBMCINT_W<'_>

Bit 9 - GPTM Timer B Capture Mode Match Interrupt Clear

pub fn cbecint(&mut self) -> CBECINT_W<'_>

Bit 10 - GPTM Timer B Capture Mode Event Interrupt Clear

pub fn tbmcint(&mut self) -> TBMCINT_W<'_>

Bit 11 - GPTM Timer B Match Interrupt Clear

pub fn wuecint(&mut self) -> WUECINT_W<'_>

Bit 16 - 32/64-Bit Wide GPTM Write Update Error Interrupt Clear

impl W<u32, Reg<u32, _TAMATCHR>>

pub fn tamr(&mut self) -> TAMR_W<'_>

Bits 0:31 - GPTM Timer A Match Register

impl W<u32, Reg<u32, _TBMATCHR>>

pub fn tbmr(&mut self) -> TBMR_W<'_>

Bits 0:31 - GPTM Timer B Match Register

impl W<u32, Reg<u32, _TAPR>>

pub fn tapsr(&mut self) -> TAPSR_W<'_>

Bits 0:7 - GPTM Timer A Prescale

pub fn tapsrh(&mut self) -> TAPSRH_W<'_>

Bits 8:15 - GPTM Timer A Prescale High Byte

impl W<u32, Reg<u32, _TBPR>>

pub fn tbpsr(&mut self) -> TBPSR_W<'_>

Bits 0:7 - GPTM Timer B Prescale

pub fn tbpsrh(&mut self) -> TBPSRH_W<'_>

Bits 8:15 - GPTM Timer B Prescale High Byte

impl W<u32, Reg<u32, _TAPMR>>

pub fn tapsmr(&mut self) -> TAPSMR_W<'_>

Bits 0:7 - GPTM TimerA Prescale Match

pub fn tapsmrh(&mut self) -> TAPSMRH_W<'_>

Bits 8:15 - GPTM Timer A Prescale Match High Byte

impl W<u32, Reg<u32, _TBPMR>>

pub fn tbpsmr(&mut self) -> TBPSMR_W<'_>

Bits 0:7 - GPTM TimerB Prescale Match

pub fn tbpsmrh(&mut self) -> TBPSMRH_W<'_>

Bits 8:15 - GPTM Timer B Prescale Match High Byte

impl W<u32, Reg<u32, _ACTSS>>

pub fn asen0(&mut self) -> ASEN0_W<'_>

Bit 0 - ADC SS0 Enable

pub fn asen1(&mut self) -> ASEN1_W<'_>

Bit 1 - ADC SS1 Enable

pub fn asen2(&mut self) -> ASEN2_W<'_>

Bit 2 - ADC SS2 Enable

pub fn asen3(&mut self) -> ASEN3_W<'_>

Bit 3 - ADC SS3 Enable

pub fn busy(&mut self) -> BUSY_W<'_>

Bit 16 - ADC Busy

impl W<u32, Reg<u32, _IM>>

pub fn mask0(&mut self) -> MASK0_W<'_>

Bit 0 - SS0 Interrupt Mask

pub fn mask1(&mut self) -> MASK1_W<'_>

Bit 1 - SS1 Interrupt Mask

pub fn mask2(&mut self) -> MASK2_W<'_>

Bit 2 - SS2 Interrupt Mask

pub fn mask3(&mut self) -> MASK3_W<'_>

Bit 3 - SS3 Interrupt Mask

pub fn dconss0(&mut self) -> DCONSS0_W<'_>

Bit 16 - Digital Comparator Interrupt on SS0

pub fn dconss1(&mut self) -> DCONSS1_W<'_>

Bit 17 - Digital Comparator Interrupt on SS1

pub fn dconss2(&mut self) -> DCONSS2_W<'_>

Bit 18 - Digital Comparator Interrupt on SS2

pub fn dconss3(&mut self) -> DCONSS3_W<'_>

Bit 19 - Digital Comparator Interrupt on SS3

impl W<u32, Reg<u32, _ISC>>

pub fn in0(&mut self) -> IN0_W<'_>

Bit 0 - SS0 Interrupt Status and Clear

pub fn in1(&mut self) -> IN1_W<'_>

Bit 1 - SS1 Interrupt Status and Clear

pub fn in2(&mut self) -> IN2_W<'_>

Bit 2 - SS2 Interrupt Status and Clear

pub fn in3(&mut self) -> IN3_W<'_>

Bit 3 - SS3 Interrupt Status and Clear

pub fn dcinss0(&mut self) -> DCINSS0_W<'_>

Bit 16 - Digital Comparator Interrupt Status on SS0

pub fn dcinss1(&mut self) -> DCINSS1_W<'_>

Bit 17 - Digital Comparator Interrupt Status on SS1

pub fn dcinss2(&mut self) -> DCINSS2_W<'_>

Bit 18 - Digital Comparator Interrupt Status on SS2

pub fn dcinss3(&mut self) -> DCINSS3_W<'_>

Bit 19 - Digital Comparator Interrupt Status on SS3

impl W<u32, Reg<u32, _OSTAT>>

pub fn ov0(&mut self) -> OV0_W<'_>

Bit 0 - SS0 FIFO Overflow

pub fn ov1(&mut self) -> OV1_W<'_>

Bit 1 - SS1 FIFO Overflow

pub fn ov2(&mut self) -> OV2_W<'_>

Bit 2 - SS2 FIFO Overflow

pub fn ov3(&mut self) -> OV3_W<'_>

Bit 3 - SS3 FIFO Overflow

impl W<u32, Reg<u32, _EMUX>>

pub fn em0(&mut self) -> EM0_W<'_>

Bits 0:3 - SS0 Trigger Select

pub fn em1(&mut self) -> EM1_W<'_>

Bits 4:7 - SS1 Trigger Select

pub fn em2(&mut self) -> EM2_W<'_>

Bits 8:11 - SS2 Trigger Select

pub fn em3(&mut self) -> EM3_W<'_>

Bits 12:15 - SS3 Trigger Select

impl W<u32, Reg<u32, _USTAT>>

pub fn uv0(&mut self) -> UV0_W<'_>

Bit 0 - SS0 FIFO Underflow

pub fn uv1(&mut self) -> UV1_W<'_>

Bit 1 - SS1 FIFO Underflow

pub fn uv2(&mut self) -> UV2_W<'_>

Bit 2 - SS2 FIFO Underflow

pub fn uv3(&mut self) -> UV3_W<'_>

Bit 3 - SS3 FIFO Underflow

impl W<u32, Reg<u32, _TSSEL>>

pub fn ps0(&mut self) -> PS0_W<'_>

Bits 4:5 - Generator 0 PWM Module Trigger Select

pub fn ps1(&mut self) -> PS1_W<'_>

Bits 12:13 - Generator 1 PWM Module Trigger Select

pub fn ps2(&mut self) -> PS2_W<'_>

Bits 20:21 - Generator 2 PWM Module Trigger Select

pub fn ps3(&mut self) -> PS3_W<'_>

Bits 28:29 - Generator 3 PWM Module Trigger Select

impl W<u32, Reg<u32, _SSPRI>>

pub fn ss0(&mut self) -> SS0_W<'_>

Bits 0:1 - SS0 Priority

pub fn ss1(&mut self) -> SS1_W<'_>

Bits 4:5 - SS1 Priority

pub fn ss2(&mut self) -> SS2_W<'_>

Bits 8:9 - SS2 Priority

pub fn ss3(&mut self) -> SS3_W<'_>

Bits 12:13 - SS3 Priority

impl W<u32, Reg<u32, _SPC>>

pub fn phase(&mut self) -> PHASE_W<'_>

Bits 0:3 - Phase Difference

impl W<u32, Reg<u32, _PSSI>>

pub fn ss0(&mut self) -> SS0_W<'_>

Bit 0 - SS0 Initiate

pub fn ss1(&mut self) -> SS1_W<'_>

Bit 1 - SS1 Initiate

pub fn ss2(&mut self) -> SS2_W<'_>

Bit 2 - SS2 Initiate

pub fn ss3(&mut self) -> SS3_W<'_>

Bit 3 - SS3 Initiate

pub fn syncwait(&mut self) -> SYNCWAIT_W<'_>

Bit 27 - Synchronize Wait

pub fn gsync(&mut self) -> GSYNC_W<'_>

Bit 31 - Global Synchronize

impl W<u32, Reg<u32, _SAC>>

pub fn avg(&mut self) -> AVG_W<'_>

Bits 0:2 - Hardware Averaging Control

impl W<u32, Reg<u32, _DCISC>>

pub fn dcint0(&mut self) -> DCINT0_W<'_>

Bit 0 - Digital Comparator 0 Interrupt Status and Clear

pub fn dcint1(&mut self) -> DCINT1_W<'_>

Bit 1 - Digital Comparator 1 Interrupt Status and Clear

pub fn dcint2(&mut self) -> DCINT2_W<'_>

Bit 2 - Digital Comparator 2 Interrupt Status and Clear

pub fn dcint3(&mut self) -> DCINT3_W<'_>

Bit 3 - Digital Comparator 3 Interrupt Status and Clear

pub fn dcint4(&mut self) -> DCINT4_W<'_>

Bit 4 - Digital Comparator 4 Interrupt Status and Clear

pub fn dcint5(&mut self) -> DCINT5_W<'_>

Bit 5 - Digital Comparator 5 Interrupt Status and Clear

pub fn dcint6(&mut self) -> DCINT6_W<'_>

Bit 6 - Digital Comparator 6 Interrupt Status and Clear

pub fn dcint7(&mut self) -> DCINT7_W<'_>

Bit 7 - Digital Comparator 7 Interrupt Status and Clear

impl W<u32, Reg<u32, _CTL>>

pub fn vref(&mut self) -> VREF_W<'_>

Bit 0 - Voltage Reference Select

impl W<u32, Reg<u32, _SSMUX0>>

pub fn mux0(&mut self) -> MUX0_W<'_>

Bits 0:3 - 1st Sample Input Select

pub fn mux1(&mut self) -> MUX1_W<'_>

Bits 4:7 - 2nd Sample Input Select

pub fn mux2(&mut self) -> MUX2_W<'_>

Bits 8:11 - 3rd Sample Input Select

pub fn mux3(&mut self) -> MUX3_W<'_>

Bits 12:15 - 4th Sample Input Select

pub fn mux4(&mut self) -> MUX4_W<'_>

Bits 16:19 - 5th Sample Input Select

pub fn mux5(&mut self) -> MUX5_W<'_>

Bits 20:23 - 6th Sample Input Select

pub fn mux6(&mut self) -> MUX6_W<'_>

Bits 24:27 - 7th Sample Input Select

pub fn mux7(&mut self) -> MUX7_W<'_>

Bits 28:31 - 8th Sample Input Select

impl W<u32, Reg<u32, _SSCTL0>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - 1st Sample Differential Input Select

pub fn end0(&mut self) -> END0_W<'_>

Bit 1 - 1st Sample is End of Sequence

pub fn ie0(&mut self) -> IE0_W<'_>

Bit 2 - 1st Sample Interrupt Enable

pub fn ts0(&mut self) -> TS0_W<'_>

Bit 3 - 1st Sample Temp Sensor Select

pub fn d1(&mut self) -> D1_W<'_>

Bit 4 - 2nd Sample Differential Input Select

pub fn end1(&mut self) -> END1_W<'_>

Bit 5 - 2nd Sample is End of Sequence

pub fn ie1(&mut self) -> IE1_W<'_>

Bit 6 - 2nd Sample Interrupt Enable

pub fn ts1(&mut self) -> TS1_W<'_>

Bit 7 - 2nd Sample Temp Sensor Select

pub fn d2(&mut self) -> D2_W<'_>

Bit 8 - 3rd Sample Differential Input Select

pub fn end2(&mut self) -> END2_W<'_>

Bit 9 - 3rd Sample is End of Sequence

pub fn ie2(&mut self) -> IE2_W<'_>

Bit 10 - 3rd Sample Interrupt Enable

pub fn ts2(&mut self) -> TS2_W<'_>

Bit 11 - 3rd Sample Temp Sensor Select

pub fn d3(&mut self) -> D3_W<'_>

Bit 12 - 4th Sample Differential Input Select

pub fn end3(&mut self) -> END3_W<'_>

Bit 13 - 4th Sample is End of Sequence

pub fn ie3(&mut self) -> IE3_W<'_>

Bit 14 - 4th Sample Interrupt Enable

pub fn ts3(&mut self) -> TS3_W<'_>

Bit 15 - 4th Sample Temp Sensor Select

pub fn d4(&mut self) -> D4_W<'_>

Bit 16 - 5th Sample Differential Input Select

pub fn end4(&mut self) -> END4_W<'_>

Bit 17 - 5th Sample is End of Sequence

pub fn ie4(&mut self) -> IE4_W<'_>

Bit 18 - 5th Sample Interrupt Enable

pub fn ts4(&mut self) -> TS4_W<'_>

Bit 19 - 5th Sample Temp Sensor Select

pub fn d5(&mut self) -> D5_W<'_>

Bit 20 - 6th Sample Differential Input Select

pub fn end5(&mut self) -> END5_W<'_>

Bit 21 - 6th Sample is End of Sequence

pub fn ie5(&mut self) -> IE5_W<'_>

Bit 22 - 6th Sample Interrupt Enable

pub fn ts5(&mut self) -> TS5_W<'_>

Bit 23 - 6th Sample Temp Sensor Select

pub fn d6(&mut self) -> D6_W<'_>

Bit 24 - 7th Sample Differential Input Select

pub fn end6(&mut self) -> END6_W<'_>

Bit 25 - 7th Sample is End of Sequence

pub fn ie6(&mut self) -> IE6_W<'_>

Bit 26 - 7th Sample Interrupt Enable

pub fn ts6(&mut self) -> TS6_W<'_>

Bit 27 - 7th Sample Temp Sensor Select

pub fn d7(&mut self) -> D7_W<'_>

Bit 28 - 8th Sample Differential Input Select

pub fn end7(&mut self) -> END7_W<'_>

Bit 29 - 8th Sample is End of Sequence

pub fn ie7(&mut self) -> IE7_W<'_>

Bit 30 - 8th Sample Interrupt Enable

pub fn ts7(&mut self) -> TS7_W<'_>

Bit 31 - 8th Sample Temp Sensor Select

impl W<u32, Reg<u32, _SSOP0>>

pub fn s0dcop(&mut self) -> S0DCOP_W<'_>

Bit 0 - Sample 0 Digital Comparator Operation

pub fn s1dcop(&mut self) -> S1DCOP_W<'_>

Bit 4 - Sample 1 Digital Comparator Operation

pub fn s2dcop(&mut self) -> S2DCOP_W<'_>

Bit 8 - Sample 2 Digital Comparator Operation

pub fn s3dcop(&mut self) -> S3DCOP_W<'_>

Bit 12 - Sample 3 Digital Comparator Operation

pub fn s4dcop(&mut self) -> S4DCOP_W<'_>

Bit 16 - Sample 4 Digital Comparator Operation

pub fn s5dcop(&mut self) -> S5DCOP_W<'_>

Bit 20 - Sample 5 Digital Comparator Operation

pub fn s6dcop(&mut self) -> S6DCOP_W<'_>

Bit 24 - Sample 6 Digital Comparator Operation

pub fn s7dcop(&mut self) -> S7DCOP_W<'_>

Bit 28 - Sample 7 Digital Comparator Operation

impl W<u32, Reg<u32, _SSDC0>>

pub fn s0dcsel(&mut self) -> S0DCSEL_W<'_>

Bits 0:3 - Sample 0 Digital Comparator Select

pub fn s1dcsel(&mut self) -> S1DCSEL_W<'_>

Bits 4:7 - Sample 1 Digital Comparator Select

pub fn s2dcsel(&mut self) -> S2DCSEL_W<'_>

Bits 8:11 - Sample 2 Digital Comparator Select

pub fn s3dcsel(&mut self) -> S3DCSEL_W<'_>

Bits 12:15 - Sample 3 Digital Comparator Select

pub fn s4dcsel(&mut self) -> S4DCSEL_W<'_>

Bits 16:19 - Sample 4 Digital Comparator Select

pub fn s5dcsel(&mut self) -> S5DCSEL_W<'_>

Bits 20:23 - Sample 5 Digital Comparator Select

pub fn s6dcsel(&mut self) -> S6DCSEL_W<'_>

Bits 24:27 - Sample 6 Digital Comparator Select

pub fn s7dcsel(&mut self) -> S7DCSEL_W<'_>

Bits 28:31 - Sample 7 Digital Comparator Select

impl W<u32, Reg<u32, _SSMUX1>>

pub fn mux0(&mut self) -> MUX0_W<'_>

Bits 0:3 - 1st Sample Input Select

pub fn mux1(&mut self) -> MUX1_W<'_>

Bits 4:7 - 2nd Sample Input Select

pub fn mux2(&mut self) -> MUX2_W<'_>

Bits 8:11 - 3rd Sample Input Select

pub fn mux3(&mut self) -> MUX3_W<'_>

Bits 12:15 - 4th Sample Input Select

impl W<u32, Reg<u32, _SSCTL1>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - 1st Sample Differential Input Select

pub fn end0(&mut self) -> END0_W<'_>

Bit 1 - 1st Sample is End of Sequence

pub fn ie0(&mut self) -> IE0_W<'_>

Bit 2 - 1st Sample Interrupt Enable

pub fn ts0(&mut self) -> TS0_W<'_>

Bit 3 - 1st Sample Temp Sensor Select

pub fn d1(&mut self) -> D1_W<'_>

Bit 4 - 2nd Sample Differential Input Select

pub fn end1(&mut self) -> END1_W<'_>

Bit 5 - 2nd Sample is End of Sequence

pub fn ie1(&mut self) -> IE1_W<'_>

Bit 6 - 2nd Sample Interrupt Enable

pub fn ts1(&mut self) -> TS1_W<'_>

Bit 7 - 2nd Sample Temp Sensor Select

pub fn d2(&mut self) -> D2_W<'_>

Bit 8 - 3rd Sample Differential Input Select

pub fn end2(&mut self) -> END2_W<'_>

Bit 9 - 3rd Sample is End of Sequence

pub fn ie2(&mut self) -> IE2_W<'_>

Bit 10 - 3rd Sample Interrupt Enable

pub fn ts2(&mut self) -> TS2_W<'_>

Bit 11 - 3rd Sample Temp Sensor Select

pub fn d3(&mut self) -> D3_W<'_>

Bit 12 - 4th Sample Differential Input Select

pub fn end3(&mut self) -> END3_W<'_>

Bit 13 - 4th Sample is End of Sequence

pub fn ie3(&mut self) -> IE3_W<'_>

Bit 14 - 4th Sample Interrupt Enable

pub fn ts3(&mut self) -> TS3_W<'_>

Bit 15 - 4th Sample Temp Sensor Select

impl W<u32, Reg<u32, _SSOP1>>

pub fn s0dcop(&mut self) -> S0DCOP_W<'_>

Bit 0 - Sample 0 Digital Comparator Operation

pub fn s1dcop(&mut self) -> S1DCOP_W<'_>

Bit 4 - Sample 1 Digital Comparator Operation

pub fn s2dcop(&mut self) -> S2DCOP_W<'_>

Bit 8 - Sample 2 Digital Comparator Operation

pub fn s3dcop(&mut self) -> S3DCOP_W<'_>

Bit 12 - Sample 3 Digital Comparator Operation

impl W<u32, Reg<u32, _SSDC1>>

pub fn s0dcsel(&mut self) -> S0DCSEL_W<'_>

Bits 0:3 - Sample 0 Digital Comparator Select

pub fn s1dcsel(&mut self) -> S1DCSEL_W<'_>

Bits 4:7 - Sample 1 Digital Comparator Select

pub fn s2dcsel(&mut self) -> S2DCSEL_W<'_>

Bits 8:11 - Sample 2 Digital Comparator Select

pub fn s3dcsel(&mut self) -> S3DCSEL_W<'_>

Bits 12:15 - Sample 3 Digital Comparator Select

impl W<u32, Reg<u32, _SSMUX2>>

pub fn mux0(&mut self) -> MUX0_W<'_>

Bits 0:3 - 1st Sample Input Select

pub fn mux1(&mut self) -> MUX1_W<'_>

Bits 4:7 - 2nd Sample Input Select

pub fn mux2(&mut self) -> MUX2_W<'_>

Bits 8:11 - 3rd Sample Input Select

pub fn mux3(&mut self) -> MUX3_W<'_>

Bits 12:15 - 4th Sample Input Select

impl W<u32, Reg<u32, _SSCTL2>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - 1st Sample Differential Input Select

pub fn end0(&mut self) -> END0_W<'_>

Bit 1 - 1st Sample is End of Sequence

pub fn ie0(&mut self) -> IE0_W<'_>

Bit 2 - 1st Sample Interrupt Enable

pub fn ts0(&mut self) -> TS0_W<'_>

Bit 3 - 1st Sample Temp Sensor Select

pub fn d1(&mut self) -> D1_W<'_>

Bit 4 - 2nd Sample Differential Input Select

pub fn end1(&mut self) -> END1_W<'_>

Bit 5 - 2nd Sample is End of Sequence

pub fn ie1(&mut self) -> IE1_W<'_>

Bit 6 - 2nd Sample Interrupt Enable

pub fn ts1(&mut self) -> TS1_W<'_>

Bit 7 - 2nd Sample Temp Sensor Select

pub fn d2(&mut self) -> D2_W<'_>

Bit 8 - 3rd Sample Differential Input Select

pub fn end2(&mut self) -> END2_W<'_>

Bit 9 - 3rd Sample is End of Sequence

pub fn ie2(&mut self) -> IE2_W<'_>

Bit 10 - 3rd Sample Interrupt Enable

pub fn ts2(&mut self) -> TS2_W<'_>

Bit 11 - 3rd Sample Temp Sensor Select

pub fn d3(&mut self) -> D3_W<'_>

Bit 12 - 4th Sample Differential Input Select

pub fn end3(&mut self) -> END3_W<'_>

Bit 13 - 4th Sample is End of Sequence

pub fn ie3(&mut self) -> IE3_W<'_>

Bit 14 - 4th Sample Interrupt Enable

pub fn ts3(&mut self) -> TS3_W<'_>

Bit 15 - 4th Sample Temp Sensor Select

impl W<u32, Reg<u32, _SSOP2>>

pub fn s0dcop(&mut self) -> S0DCOP_W<'_>

Bit 0 - Sample 0 Digital Comparator Operation

pub fn s1dcop(&mut self) -> S1DCOP_W<'_>

Bit 4 - Sample 1 Digital Comparator Operation

pub fn s2dcop(&mut self) -> S2DCOP_W<'_>

Bit 8 - Sample 2 Digital Comparator Operation

pub fn s3dcop(&mut self) -> S3DCOP_W<'_>

Bit 12 - Sample 3 Digital Comparator Operation

impl W<u32, Reg<u32, _SSDC2>>

pub fn s0dcsel(&mut self) -> S0DCSEL_W<'_>

Bits 0:3 - Sample 0 Digital Comparator Select

pub fn s1dcsel(&mut self) -> S1DCSEL_W<'_>

Bits 4:7 - Sample 1 Digital Comparator Select

pub fn s2dcsel(&mut self) -> S2DCSEL_W<'_>

Bits 8:11 - Sample 2 Digital Comparator Select

pub fn s3dcsel(&mut self) -> S3DCSEL_W<'_>

Bits 12:15 - Sample 3 Digital Comparator Select

impl W<u32, Reg<u32, _SSMUX3>>

pub fn mux0(&mut self) -> MUX0_W<'_>

Bits 0:3 - 1st Sample Input Select

impl W<u32, Reg<u32, _SSCTL3>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - Sample Differential Input Select

pub fn end0(&mut self) -> END0_W<'_>

Bit 1 - End of Sequence

pub fn ie0(&mut self) -> IE0_W<'_>

Bit 2 - Sample Interrupt Enable

pub fn ts0(&mut self) -> TS0_W<'_>

Bit 3 - 1st Sample Temp Sensor Select

impl W<u32, Reg<u32, _SSOP3>>

pub fn s0dcop(&mut self) -> S0DCOP_W<'_>

Bit 0 - Sample 0 Digital Comparator Operation

impl W<u32, Reg<u32, _SSDC3>>

pub fn s0dcsel(&mut self) -> S0DCSEL_W<'_>

Bits 0:3 - Sample 0 Digital Comparator Select

impl W<u32, Reg<u32, _DCRIC>>

pub fn dcint0(&mut self) -> DCINT0_W<'_>

Bit 0 - Digital Comparator Interrupt 0

pub fn dcint1(&mut self) -> DCINT1_W<'_>

Bit 1 - Digital Comparator Interrupt 1

pub fn dcint2(&mut self) -> DCINT2_W<'_>

Bit 2 - Digital Comparator Interrupt 2

pub fn dcint3(&mut self) -> DCINT3_W<'_>

Bit 3 - Digital Comparator Interrupt 3

pub fn dcint4(&mut self) -> DCINT4_W<'_>

Bit 4 - Digital Comparator Interrupt 4

pub fn dcint5(&mut self) -> DCINT5_W<'_>

Bit 5 - Digital Comparator Interrupt 5

pub fn dcint6(&mut self) -> DCINT6_W<'_>

Bit 6 - Digital Comparator Interrupt 6

pub fn dcint7(&mut self) -> DCINT7_W<'_>

Bit 7 - Digital Comparator Interrupt 7

pub fn dctrig0(&mut self) -> DCTRIG0_W<'_>

Bit 16 - Digital Comparator Trigger 0

pub fn dctrig1(&mut self) -> DCTRIG1_W<'_>

Bit 17 - Digital Comparator Trigger 1

pub fn dctrig2(&mut self) -> DCTRIG2_W<'_>

Bit 18 - Digital Comparator Trigger 2

pub fn dctrig3(&mut self) -> DCTRIG3_W<'_>

Bit 19 - Digital Comparator Trigger 3

pub fn dctrig4(&mut self) -> DCTRIG4_W<'_>

Bit 20 - Digital Comparator Trigger 4

pub fn dctrig5(&mut self) -> DCTRIG5_W<'_>

Bit 21 - Digital Comparator Trigger 5

pub fn dctrig6(&mut self) -> DCTRIG6_W<'_>

Bit 22 - Digital Comparator Trigger 6

pub fn dctrig7(&mut self) -> DCTRIG7_W<'_>

Bit 23 - Digital Comparator Trigger 7

impl W<u32, Reg<u32, _DCCTL0>>

pub fn cim(&mut self) -> CIM_W<'_>

Bits 0:1 - Comparison Interrupt Mode

pub fn cic(&mut self) -> CIC_W<'_>

Bits 2:3 - Comparison Interrupt Condition

pub fn cie(&mut self) -> CIE_W<'_>

Bit 4 - Comparison Interrupt Enable

pub fn ctm(&mut self) -> CTM_W<'_>

Bits 8:9 - Comparison Trigger Mode

pub fn ctc(&mut self) -> CTC_W<'_>

Bits 10:11 - Comparison Trigger Condition

pub fn cte(&mut self) -> CTE_W<'_>

Bit 12 - Comparison Trigger Enable

impl W<u32, Reg<u32, _DCCTL1>>

pub fn cim(&mut self) -> CIM_W<'_>

Bits 0:1 - Comparison Interrupt Mode

pub fn cic(&mut self) -> CIC_W<'_>

Bits 2:3 - Comparison Interrupt Condition

pub fn cie(&mut self) -> CIE_W<'_>

Bit 4 - Comparison Interrupt Enable

pub fn ctm(&mut self) -> CTM_W<'_>

Bits 8:9 - Comparison Trigger Mode

pub fn ctc(&mut self) -> CTC_W<'_>

Bits 10:11 - Comparison Trigger Condition

pub fn cte(&mut self) -> CTE_W<'_>

Bit 12 - Comparison Trigger Enable

impl W<u32, Reg<u32, _DCCTL2>>

pub fn cim(&mut self) -> CIM_W<'_>

Bits 0:1 - Comparison Interrupt Mode

pub fn cic(&mut self) -> CIC_W<'_>

Bits 2:3 - Comparison Interrupt Condition

pub fn cie(&mut self) -> CIE_W<'_>

Bit 4 - Comparison Interrupt Enable

pub fn ctm(&mut self) -> CTM_W<'_>

Bits 8:9 - Comparison Trigger Mode

pub fn ctc(&mut self) -> CTC_W<'_>

Bits 10:11 - Comparison Trigger Condition

pub fn cte(&mut self) -> CTE_W<'_>

Bit 12 - Comparison Trigger Enable

impl W<u32, Reg<u32, _DCCTL3>>

pub fn cim(&mut self) -> CIM_W<'_>

Bits 0:1 - Comparison Interrupt Mode

pub fn cic(&mut self) -> CIC_W<'_>

Bits 2:3 - Comparison Interrupt Condition

pub fn cie(&mut self) -> CIE_W<'_>

Bit 4 - Comparison Interrupt Enable

pub fn ctm(&mut self) -> CTM_W<'_>

Bits 8:9 - Comparison Trigger Mode

pub fn ctc(&mut self) -> CTC_W<'_>

Bits 10:11 - Comparison Trigger Condition

pub fn cte(&mut self) -> CTE_W<'_>

Bit 12 - Comparison Trigger Enable

impl W<u32, Reg<u32, _DCCTL4>>

pub fn cim(&mut self) -> CIM_W<'_>

Bits 0:1 - Comparison Interrupt Mode

pub fn cic(&mut self) -> CIC_W<'_>

Bits 2:3 - Comparison Interrupt Condition

pub fn cie(&mut self) -> CIE_W<'_>

Bit 4 - Comparison Interrupt Enable

pub fn ctm(&mut self) -> CTM_W<'_>

Bits 8:9 - Comparison Trigger Mode

pub fn ctc(&mut self) -> CTC_W<'_>

Bits 10:11 - Comparison Trigger Condition

pub fn cte(&mut self) -> CTE_W<'_>

Bit 12 - Comparison Trigger Enable

impl W<u32, Reg<u32, _DCCTL5>>

pub fn cim(&mut self) -> CIM_W<'_>

Bits 0:1 - Comparison Interrupt Mode

pub fn cic(&mut self) -> CIC_W<'_>

Bits 2:3 - Comparison Interrupt Condition

pub fn cie(&mut self) -> CIE_W<'_>

Bit 4 - Comparison Interrupt Enable

pub fn ctm(&mut self) -> CTM_W<'_>

Bits 8:9 - Comparison Trigger Mode

pub fn ctc(&mut self) -> CTC_W<'_>

Bits 10:11 - Comparison Trigger Condition

pub fn cte(&mut self) -> CTE_W<'_>

Bit 12 - Comparison Trigger Enable

impl W<u32, Reg<u32, _DCCTL6>>

pub fn cim(&mut self) -> CIM_W<'_>

Bits 0:1 - Comparison Interrupt Mode

pub fn cic(&mut self) -> CIC_W<'_>

Bits 2:3 - Comparison Interrupt Condition

pub fn cie(&mut self) -> CIE_W<'_>

Bit 4 - Comparison Interrupt Enable

pub fn ctm(&mut self) -> CTM_W<'_>

Bits 8:9 - Comparison Trigger Mode

pub fn ctc(&mut self) -> CTC_W<'_>

Bits 10:11 - Comparison Trigger Condition

pub fn cte(&mut self) -> CTE_W<'_>

Bit 12 - Comparison Trigger Enable

impl W<u32, Reg<u32, _DCCTL7>>

pub fn cim(&mut self) -> CIM_W<'_>

Bits 0:1 - Comparison Interrupt Mode

pub fn cic(&mut self) -> CIC_W<'_>

Bits 2:3 - Comparison Interrupt Condition

pub fn cie(&mut self) -> CIE_W<'_>

Bit 4 - Comparison Interrupt Enable

pub fn ctm(&mut self) -> CTM_W<'_>

Bits 8:9 - Comparison Trigger Mode

pub fn ctc(&mut self) -> CTC_W<'_>

Bits 10:11 - Comparison Trigger Condition

pub fn cte(&mut self) -> CTE_W<'_>

Bit 12 - Comparison Trigger Enable

impl W<u32, Reg<u32, _DCCMP0>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bits 0:11 - Compare 0

pub fn comp1(&mut self) -> COMP1_W<'_>

Bits 16:27 - Compare 1

impl W<u32, Reg<u32, _DCCMP1>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bits 0:11 - Compare 0

pub fn comp1(&mut self) -> COMP1_W<'_>

Bits 16:27 - Compare 1

impl W<u32, Reg<u32, _DCCMP2>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bits 0:11 - Compare 0

pub fn comp1(&mut self) -> COMP1_W<'_>

Bits 16:27 - Compare 1

impl W<u32, Reg<u32, _DCCMP3>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bits 0:11 - Compare 0

pub fn comp1(&mut self) -> COMP1_W<'_>

Bits 16:27 - Compare 1

impl W<u32, Reg<u32, _DCCMP4>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bits 0:11 - Compare 0

pub fn comp1(&mut self) -> COMP1_W<'_>

Bits 16:27 - Compare 1

impl W<u32, Reg<u32, _DCCMP5>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bits 0:11 - Compare 0

pub fn comp1(&mut self) -> COMP1_W<'_>

Bits 16:27 - Compare 1

impl W<u32, Reg<u32, _DCCMP6>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bits 0:11 - Compare 0

pub fn comp1(&mut self) -> COMP1_W<'_>

Bits 16:27 - Compare 1

impl W<u32, Reg<u32, _DCCMP7>>

pub fn comp0(&mut self) -> COMP0_W<'_>

Bits 0:11 - Compare 0

pub fn comp1(&mut self) -> COMP1_W<'_>

Bits 16:27 - Compare 1

impl W<u32, Reg<u32, _PC>>

pub fn sr(&mut self) -> SR_W<'_>

Bits 0:3 - ADC Sample Rate

impl W<u32, Reg<u32, _CC>>

pub fn cs(&mut self) -> CS_W<'_>

Bits 0:3 - ADC Clock Source

impl W<u32, Reg<u32, _ACMIS>>

pub fn in0(&mut self) -> IN0_W<'_>

Bit 0 - Comparator 0 Masked Interrupt Status

pub fn in1(&mut self) -> IN1_W<'_>

Bit 1 - Comparator 1 Masked Interrupt Status

impl W<u32, Reg<u32, _ACINTEN>>

pub fn in0(&mut self) -> IN0_W<'_>

Bit 0 - Comparator 0 Interrupt Enable

pub fn in1(&mut self) -> IN1_W<'_>

Bit 1 - Comparator 1 Interrupt Enable

impl W<u32, Reg<u32, _ACREFCTL>>

pub fn vref(&mut self) -> VREF_W<'_>

Bits 0:3 - Resistor Ladder Voltage Ref

pub fn rng(&mut self) -> RNG_W<'_>

Bit 8 - Resistor Ladder Range

pub fn en(&mut self) -> EN_W<'_>

Bit 9 - Resistor Ladder Enable

impl W<u32, Reg<u32, _ACCTL0>>

pub fn cinv(&mut self) -> CINV_W<'_>

Bit 1 - Comparator Output Invert

pub fn isen(&mut self) -> ISEN_W<'_>

Bits 2:3 - Interrupt Sense

pub fn islval(&mut self) -> ISLVAL_W<'_>

Bit 4 - Interrupt Sense Level Value

pub fn tsen(&mut self) -> TSEN_W<'_>

Bits 5:6 - Trigger Sense

pub fn tslval(&mut self) -> TSLVAL_W<'_>

Bit 7 - Trigger Sense Level Value

pub fn asrcp(&mut self) -> ASRCP_W<'_>

Bits 9:10 - Analog Source Positive

pub fn toen(&mut self) -> TOEN_W<'_>

Bit 11 - Trigger Output Enable

impl W<u32, Reg<u32, _ACCTL1>>

pub fn cinv(&mut self) -> CINV_W<'_>

Bit 1 - Comparator Output Invert

pub fn isen(&mut self) -> ISEN_W<'_>

Bits 2:3 - Interrupt Sense

pub fn islval(&mut self) -> ISLVAL_W<'_>

Bit 4 - Interrupt Sense Level Value

pub fn tsen(&mut self) -> TSEN_W<'_>

Bits 5:6 - Trigger Sense

pub fn tslval(&mut self) -> TSLVAL_W<'_>

Bit 7 - Trigger Sense Level Value

pub fn asrcp(&mut self) -> ASRCP_W<'_>

Bits 9:10 - Analog Source Positive

pub fn toen(&mut self) -> TOEN_W<'_>

Bit 11 - Trigger Output Enable

impl W<u32, Reg<u32, _CTL>>

pub fn init(&mut self) -> INIT_W<'_>

Bit 0 - Initialization

pub fn ie(&mut self) -> IE_W<'_>

Bit 1 - CAN Interrupt Enable

pub fn sie(&mut self) -> SIE_W<'_>

Bit 2 - Status Interrupt Enable

pub fn eie(&mut self) -> EIE_W<'_>

Bit 3 - Error Interrupt Enable

pub fn dar(&mut self) -> DAR_W<'_>

Bit 5 - Disable Automatic-Retransmission

pub fn cce(&mut self) -> CCE_W<'_>

Bit 6 - Configuration Change Enable

pub fn test(&mut self) -> TEST_W<'_>

Bit 7 - Test Mode Enable

impl W<u32, Reg<u32, _STS>>

pub fn lec(&mut self) -> LEC_W<'_>

Bits 0:2 - Last Error Code

pub fn txok(&mut self) -> TXOK_W<'_>

Bit 3 - Transmitted a Message Successfully

pub fn rxok(&mut self) -> RXOK_W<'_>

Bit 4 - Received a Message Successfully

pub fn epass(&mut self) -> EPASS_W<'_>

Bit 5 - Error Passive

pub fn ewarn(&mut self) -> EWARN_W<'_>

Bit 6 - Warning Status

pub fn boff(&mut self) -> BOFF_W<'_>

Bit 7 - Bus-Off Status

impl W<u32, Reg<u32, _BIT>>

pub fn brp(&mut self) -> BRP_W<'_>

Bits 0:5 - Baud Rate Prescaler

pub fn sjw(&mut self) -> SJW_W<'_>

Bits 6:7 - (Re)Synchronization Jump Width

pub fn tseg1(&mut self) -> TSEG1_W<'_>

Bits 8:11 - Time Segment Before Sample Point

pub fn tseg2(&mut self) -> TSEG2_W<'_>

Bits 12:14 - Time Segment after Sample Point

impl W<u32, Reg<u32, _TST>>

pub fn basic(&mut self) -> BASIC_W<'_>

Bit 2 - Basic Mode

pub fn silent(&mut self) -> SILENT_W<'_>

Bit 3 - Silent Mode

pub fn lback(&mut self) -> LBACK_W<'_>

Bit 4 - Loopback Mode

pub fn tx(&mut self) -> TX_W<'_>

Bits 5:6 - Transmit Control

pub fn rx(&mut self) -> RX_W<'_>

Bit 7 - Receive Observation

impl W<u32, Reg<u32, _BRPE>>

pub fn brpe(&mut self) -> BRPE_W<'_>

Bits 0:3 - Baud Rate Prescaler Extension

impl W<u32, Reg<u32, _IF1CRQ>>

pub fn mnum(&mut self) -> MNUM_W<'_>

Bits 0:5 - Message Number

pub fn busy(&mut self) -> BUSY_W<'_>

Bit 15 - Busy Flag

impl W<u32, Reg<u32, _IF1CMSK>>

pub fn datab(&mut self) -> DATAB_W<'_>

Bit 0 - Access Data Byte 4 to 7

pub fn dataa(&mut self) -> DATAA_W<'_>

Bit 1 - Access Data Byte 0 to 3

pub fn newdat(&mut self) -> NEWDAT_W<'_>

Bit 2 - Access New Data

pub fn txrqst(&mut self) -> TXRQST_W<'_>

Bit 2 - Access Transmission Request

pub fn clrintpnd(&mut self) -> CLRINTPND_W<'_>

Bit 3 - Clear Interrupt Pending Bit

pub fn control(&mut self) -> CONTROL_W<'_>

Bit 4 - Access Control Bits

pub fn arb(&mut self) -> ARB_W<'_>

Bit 5 - Access Arbitration Bits

pub fn mask(&mut self) -> MASK_W<'_>

Bit 6 - Access Mask Bits

pub fn wrnrd(&mut self) -> WRNRD_W<'_>

Bit 7 - Write, Not Read

impl W<u32, Reg<u32, _IF1MSK1>>

pub fn idmsk(&mut self) -> IDMSK_W<'_>

Bits 0:15 - Identifier Mask

impl W<u32, Reg<u32, _IF1MSK2>>

pub fn idmsk(&mut self) -> IDMSK_W<'_>

Bits 0:12 - Identifier Mask

pub fn mdir(&mut self) -> MDIR_W<'_>

Bit 14 - Mask Message Direction

pub fn mxtd(&mut self) -> MXTD_W<'_>

Bit 15 - Mask Extended Identifier

impl W<u32, Reg<u32, _IF1ARB1>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:15 - Message Identifier

impl W<u32, Reg<u32, _IF1ARB2>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:12 - Message Identifier

pub fn dir(&mut self) -> DIR_W<'_>

Bit 13 - Message Direction

pub fn xtd(&mut self) -> XTD_W<'_>

Bit 14 - Extended Identifier

pub fn msgval(&mut self) -> MSGVAL_W<'_>

Bit 15 - Message Valid

impl W<u32, Reg<u32, _IF1MCTL>>

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - Data Length Code

pub fn eob(&mut self) -> EOB_W<'_>

Bit 7 - End of Buffer

pub fn txrqst(&mut self) -> TXRQST_W<'_>

Bit 8 - Transmit Request

pub fn rmten(&mut self) -> RMTEN_W<'_>

Bit 9 - Remote Enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 10 - Receive Interrupt Enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 11 - Transmit Interrupt Enable

pub fn umask(&mut self) -> UMASK_W<'_>

Bit 12 - Use Acceptance Mask

pub fn intpnd(&mut self) -> INTPND_W<'_>

Bit 13 - Interrupt Pending

pub fn msglst(&mut self) -> MSGLST_W<'_>

Bit 14 - Message Lost

pub fn newdat(&mut self) -> NEWDAT_W<'_>

Bit 15 - New Data

impl W<u32, Reg<u32, _IF1DA1>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Data

impl W<u32, Reg<u32, _IF1DA2>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Data

impl W<u32, Reg<u32, _IF1DB1>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Data

impl W<u32, Reg<u32, _IF1DB2>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Data

impl W<u32, Reg<u32, _IF2CRQ>>

pub fn mnum(&mut self) -> MNUM_W<'_>

Bits 0:5 - Message Number

pub fn busy(&mut self) -> BUSY_W<'_>

Bit 15 - Busy Flag

impl W<u32, Reg<u32, _IF2CMSK>>

pub fn datab(&mut self) -> DATAB_W<'_>

Bit 0 - Access Data Byte 4 to 7

pub fn dataa(&mut self) -> DATAA_W<'_>

Bit 1 - Access Data Byte 0 to 3

pub fn newdat(&mut self) -> NEWDAT_W<'_>

Bit 2 - Access New Data

pub fn txrqst(&mut self) -> TXRQST_W<'_>

Bit 2 - Access Transmission Request

pub fn clrintpnd(&mut self) -> CLRINTPND_W<'_>

Bit 3 - Clear Interrupt Pending Bit

pub fn control(&mut self) -> CONTROL_W<'_>

Bit 4 - Access Control Bits

pub fn arb(&mut self) -> ARB_W<'_>

Bit 5 - Access Arbitration Bits

pub fn mask(&mut self) -> MASK_W<'_>

Bit 6 - Access Mask Bits

pub fn wrnrd(&mut self) -> WRNRD_W<'_>

Bit 7 - Write, Not Read

impl W<u32, Reg<u32, _IF2MSK1>>

pub fn idmsk(&mut self) -> IDMSK_W<'_>

Bits 0:15 - Identifier Mask

impl W<u32, Reg<u32, _IF2MSK2>>

pub fn idmsk(&mut self) -> IDMSK_W<'_>

Bits 0:12 - Identifier Mask

pub fn mdir(&mut self) -> MDIR_W<'_>

Bit 14 - Mask Message Direction

pub fn mxtd(&mut self) -> MXTD_W<'_>

Bit 15 - Mask Extended Identifier

impl W<u32, Reg<u32, _IF2ARB1>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:15 - Message Identifier

impl W<u32, Reg<u32, _IF2ARB2>>

pub fn id(&mut self) -> ID_W<'_>

Bits 0:12 - Message Identifier

pub fn dir(&mut self) -> DIR_W<'_>

Bit 13 - Message Direction

pub fn xtd(&mut self) -> XTD_W<'_>

Bit 14 - Extended Identifier

pub fn msgval(&mut self) -> MSGVAL_W<'_>

Bit 15 - Message Valid

impl W<u32, Reg<u32, _IF2MCTL>>

pub fn dlc(&mut self) -> DLC_W<'_>

Bits 0:3 - Data Length Code

pub fn eob(&mut self) -> EOB_W<'_>

Bit 7 - End of Buffer

pub fn txrqst(&mut self) -> TXRQST_W<'_>

Bit 8 - Transmit Request

pub fn rmten(&mut self) -> RMTEN_W<'_>

Bit 9 - Remote Enable

pub fn rxie(&mut self) -> RXIE_W<'_>

Bit 10 - Receive Interrupt Enable

pub fn txie(&mut self) -> TXIE_W<'_>

Bit 11 - Transmit Interrupt Enable

pub fn umask(&mut self) -> UMASK_W<'_>

Bit 12 - Use Acceptance Mask

pub fn intpnd(&mut self) -> INTPND_W<'_>

Bit 13 - Interrupt Pending

pub fn msglst(&mut self) -> MSGLST_W<'_>

Bit 14 - Message Lost

pub fn newdat(&mut self) -> NEWDAT_W<'_>

Bit 15 - New Data

impl W<u32, Reg<u32, _IF2DA1>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Data

impl W<u32, Reg<u32, _IF2DA2>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Data

impl W<u32, Reg<u32, _IF2DB1>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Data

impl W<u32, Reg<u32, _IF2DB2>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:15 - Data

impl W<u8, Reg<u8, _FADDR>>

pub fn faddr(&mut self) -> FADDR_W<'_>

Bits 0:6 - Function Address

impl W<u8, Reg<u8, _POWER>>

pub fn pwrdnphy(&mut self) -> PWRDNPHY_W<'_>

Bit 0 - Power Down PHY

pub fn suspend(&mut self) -> SUSPEND_W<'_>

Bit 1 - SUSPEND Mode

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 2 - RESUME Signaling

pub fn reset(&mut self) -> RESET_W<'_>

Bit 3 - RESET Signaling

pub fn softconn(&mut self) -> SOFTCONN_W<'_>

Bit 6 - Soft Connect/Disconnect

pub fn isoup(&mut self) -> ISOUP_W<'_>

Bit 7 - Isochronous Update

impl W<u16, Reg<u16, _TXIE>>

pub fn ep0(&mut self) -> EP0_W<'_>

Bit 0 - TX and RX Endpoint 0 Interrupt Enable

pub fn ep1(&mut self) -> EP1_W<'_>

Bit 1 - TX Endpoint 1 Interrupt Enable

pub fn ep2(&mut self) -> EP2_W<'_>

Bit 2 - TX Endpoint 2 Interrupt Enable

pub fn ep3(&mut self) -> EP3_W<'_>

Bit 3 - TX Endpoint 3 Interrupt Enable

pub fn ep4(&mut self) -> EP4_W<'_>

Bit 4 - TX Endpoint 4 Interrupt Enable

pub fn ep5(&mut self) -> EP5_W<'_>

Bit 5 - TX Endpoint 5 Interrupt Enable

pub fn ep6(&mut self) -> EP6_W<'_>

Bit 6 - TX Endpoint 6 Interrupt Enable

pub fn ep7(&mut self) -> EP7_W<'_>

Bit 7 - TX Endpoint 7 Interrupt Enable

impl W<u16, Reg<u16, _RXIE>>

pub fn ep1(&mut self) -> EP1_W<'_>

Bit 1 - RX Endpoint 1 Interrupt Enable

pub fn ep2(&mut self) -> EP2_W<'_>

Bit 2 - RX Endpoint 2 Interrupt Enable

pub fn ep3(&mut self) -> EP3_W<'_>

Bit 3 - RX Endpoint 3 Interrupt Enable

pub fn ep4(&mut self) -> EP4_W<'_>

Bit 4 - RX Endpoint 4 Interrupt Enable

pub fn ep5(&mut self) -> EP5_W<'_>

Bit 5 - RX Endpoint 5 Interrupt Enable

pub fn ep6(&mut self) -> EP6_W<'_>

Bit 6 - RX Endpoint 6 Interrupt Enable

pub fn ep7(&mut self) -> EP7_W<'_>

Bit 7 - RX Endpoint 7 Interrupt Enable

impl W<u8, Reg<u8, _IE>>

pub fn suspnd(&mut self) -> SUSPND_W<'_>

Bit 0 - Enable SUSPEND Interrupt

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 1 - Enable RESUME Interrupt

pub fn babble(&mut self) -> BABBLE_W<'_>

Bit 2 - Enable Babble Interrupt

pub fn reset(&mut self) -> RESET_W<'_>

Bit 2 - Enable RESET Interrupt

pub fn sof(&mut self) -> SOF_W<'_>

Bit 3 - Enable Start-of-Frame Interrupt

pub fn conn(&mut self) -> CONN_W<'_>

Bit 4 - Enable Connect Interrupt

pub fn discon(&mut self) -> DISCON_W<'_>

Bit 5 - Enable Disconnect Interrupt

pub fn sesreq(&mut self) -> SESREQ_W<'_>

Bit 6 - Enable Session Request (OTG only)

pub fn vbuserr(&mut self) -> VBUSERR_W<'_>

Bit 7 - Enable VBUS Error Interrupt (OTG only)

impl W<u8, Reg<u8, _EPIDX>>

pub fn epidx(&mut self) -> EPIDX_W<'_>

Bits 0:3 - Endpoint Index

impl W<u8, Reg<u8, _TEST>>

pub fn forcefs(&mut self) -> FORCEFS_W<'_>

Bit 5 - Force Full-Speed Mode

pub fn fifoacc(&mut self) -> FIFOACC_W<'_>

Bit 6 - FIFO Access

pub fn forceh(&mut self) -> FORCEH_W<'_>

Bit 7 - Force Host Mode

impl W<u32, Reg<u32, _FIFO0>>

pub fn epdata(&mut self) -> EPDATA_W<'_>

Bits 0:31 - Endpoint Data

impl W<u32, Reg<u32, _FIFO1>>

pub fn epdata(&mut self) -> EPDATA_W<'_>

Bits 0:31 - Endpoint Data

impl W<u32, Reg<u32, _FIFO2>>

pub fn epdata(&mut self) -> EPDATA_W<'_>

Bits 0:31 - Endpoint Data

impl W<u32, Reg<u32, _FIFO3>>

pub fn epdata(&mut self) -> EPDATA_W<'_>

Bits 0:31 - Endpoint Data

impl W<u32, Reg<u32, _FIFO4>>

pub fn epdata(&mut self) -> EPDATA_W<'_>

Bits 0:31 - Endpoint Data

impl W<u32, Reg<u32, _FIFO5>>

pub fn epdata(&mut self) -> EPDATA_W<'_>

Bits 0:31 - Endpoint Data

impl W<u32, Reg<u32, _FIFO6>>

pub fn epdata(&mut self) -> EPDATA_W<'_>

Bits 0:31 - Endpoint Data

impl W<u32, Reg<u32, _FIFO7>>

pub fn epdata(&mut self) -> EPDATA_W<'_>

Bits 0:31 - Endpoint Data

impl W<u8, Reg<u8, _DEVCTL>>

pub fn session(&mut self) -> SESSION_W<'_>

Bit 0 - Session Start/End (OTG only)

pub fn hostreq(&mut self) -> HOSTREQ_W<'_>

Bit 1 - Host Request (OTG only)

pub fn host(&mut self) -> HOST_W<'_>

Bit 2 - Host Mode

pub fn vbus(&mut self) -> VBUS_W<'_>

Bits 3:4 - VBUS Level (OTG only)

pub fn lsdev(&mut self) -> LSDEV_W<'_>

Bit 5 - Low-Speed Device Detected

pub fn fsdev(&mut self) -> FSDEV_W<'_>

Bit 6 - Full-Speed Device Detected

pub fn dev(&mut self) -> DEV_W<'_>

Bit 7 - Device Mode (OTG only)

impl W<u8, Reg<u8, _TXFIFOSZ>>

pub fn size(&mut self) -> SIZE_W<'_>

Bits 0:3 - Max Packet Size

pub fn dpb(&mut self) -> DPB_W<'_>

Bit 4 - Double Packet Buffer Support

impl W<u8, Reg<u8, _RXFIFOSZ>>

pub fn size(&mut self) -> SIZE_W<'_>

Bits 0:3 - Max Packet Size

pub fn dpb(&mut self) -> DPB_W<'_>

Bit 4 - Double Packet Buffer Support

impl W<u16, Reg<u16, _TXFIFOADD>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:8 - Transmit/Receive Start Address

impl W<u16, Reg<u16, _RXFIFOADD>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:8 - Transmit/Receive Start Address

impl W<u8, Reg<u8, _CONTIM>>

pub fn wtid(&mut self) -> WTID_W<'_>

Bits 0:3 - Wait ID

pub fn wtcon(&mut self) -> WTCON_W<'_>

Bits 4:7 - Connect Wait

impl W<u8, Reg<u8, _VPLEN>>

pub fn vplen(&mut self) -> VPLEN_W<'_>

Bits 0:7 - VBUS Pulse Length

impl W<u8, Reg<u8, _FSEOF>>

pub fn fseofg(&mut self) -> FSEOFG_W<'_>

Bits 0:7 - Full-Speed End-of-Frame Gap

impl W<u8, Reg<u8, _LSEOF>>

pub fn lseofg(&mut self) -> LSEOFG_W<'_>

Bits 0:7 - Low-Speed End-of-Frame Gap

impl W<u8, Reg<u8, _TXFUNCADDR0>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Device Address

impl W<u8, Reg<u8, _TXHUBADDR0>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Hub Address

impl W<u8, Reg<u8, _TXHUBPORT0>>

pub fn port(&mut self) -> PORT_W<'_>

Bits 0:6 - Hub Port

impl W<u8, Reg<u8, _TXFUNCADDR1>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Device Address

impl W<u8, Reg<u8, _TXHUBADDR1>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Hub Address

impl W<u8, Reg<u8, _TXHUBPORT1>>

pub fn port(&mut self) -> PORT_W<'_>

Bits 0:6 - Hub Port

impl W<u8, Reg<u8, _RXFUNCADDR1>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Device Address

impl W<u8, Reg<u8, _RXHUBADDR1>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Hub Address

impl W<u8, Reg<u8, _RXHUBPORT1>>

pub fn port(&mut self) -> PORT_W<'_>

Bits 0:6 - Hub Port

impl W<u8, Reg<u8, _TXFUNCADDR2>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Device Address

impl W<u8, Reg<u8, _TXHUBADDR2>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Hub Address

impl W<u8, Reg<u8, _TXHUBPORT2>>

pub fn port(&mut self) -> PORT_W<'_>

Bits 0:6 - Hub Port

impl W<u8, Reg<u8, _RXFUNCADDR2>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Device Address

impl W<u8, Reg<u8, _RXHUBADDR2>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Hub Address

impl W<u8, Reg<u8, _RXHUBPORT2>>

pub fn port(&mut self) -> PORT_W<'_>

Bits 0:6 - Hub Port

impl W<u8, Reg<u8, _TXFUNCADDR3>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Device Address

impl W<u8, Reg<u8, _TXHUBADDR3>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Hub Address

impl W<u8, Reg<u8, _TXHUBPORT3>>

pub fn port(&mut self) -> PORT_W<'_>

Bits 0:6 - Hub Port

impl W<u8, Reg<u8, _RXFUNCADDR3>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Device Address

impl W<u8, Reg<u8, _RXHUBADDR3>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Hub Address

impl W<u8, Reg<u8, _RXHUBPORT3>>

pub fn port(&mut self) -> PORT_W<'_>

Bits 0:6 - Hub Port

impl W<u8, Reg<u8, _TXFUNCADDR4>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Device Address

impl W<u8, Reg<u8, _TXHUBADDR4>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Hub Address

impl W<u8, Reg<u8, _TXHUBPORT4>>

pub fn port(&mut self) -> PORT_W<'_>

Bits 0:6 - Hub Port

impl W<u8, Reg<u8, _RXFUNCADDR4>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Device Address

impl W<u8, Reg<u8, _RXHUBADDR4>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Hub Address

impl W<u8, Reg<u8, _RXHUBPORT4>>

pub fn port(&mut self) -> PORT_W<'_>

Bits 0:6 - Hub Port

impl W<u8, Reg<u8, _TXFUNCADDR5>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Device Address

impl W<u8, Reg<u8, _TXHUBADDR5>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Hub Address

impl W<u8, Reg<u8, _TXHUBPORT5>>

pub fn port(&mut self) -> PORT_W<'_>

Bits 0:6 - Hub Port

impl W<u8, Reg<u8, _RXFUNCADDR5>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Device Address

impl W<u8, Reg<u8, _RXHUBADDR5>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Hub Address

impl W<u8, Reg<u8, _RXHUBPORT5>>

pub fn port(&mut self) -> PORT_W<'_>

Bits 0:6 - Hub Port

impl W<u8, Reg<u8, _TXFUNCADDR6>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Device Address

impl W<u8, Reg<u8, _TXHUBADDR6>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Hub Address

impl W<u8, Reg<u8, _TXHUBPORT6>>

pub fn port(&mut self) -> PORT_W<'_>

Bits 0:6 - Hub Port

impl W<u8, Reg<u8, _RXFUNCADDR6>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Device Address

impl W<u8, Reg<u8, _RXHUBADDR6>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Hub Address

impl W<u8, Reg<u8, _RXHUBPORT6>>

pub fn port(&mut self) -> PORT_W<'_>

Bits 0:6 - Hub Port

impl W<u8, Reg<u8, _TXFUNCADDR7>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Device Address

impl W<u8, Reg<u8, _TXHUBADDR7>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Hub Address

impl W<u8, Reg<u8, _TXHUBPORT7>>

pub fn port(&mut self) -> PORT_W<'_>

Bits 0:6 - Hub Port

impl W<u8, Reg<u8, _RXFUNCADDR7>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Device Address

impl W<u8, Reg<u8, _RXHUBADDR7>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 0:6 - Hub Address

impl W<u8, Reg<u8, _RXHUBPORT7>>

pub fn port(&mut self) -> PORT_W<'_>

Bits 0:6 - Hub Port

impl W<u8, Reg<u8, _CSRL0>>

pub fn rxrdy(&mut self) -> RXRDY_W<'_>

Bit 0 - Receive Packet Ready

pub fn txrdy(&mut self) -> TXRDY_W<'_>

Bit 1 - Transmit Packet Ready

pub fn stalled(&mut self) -> STALLED_W<'_>

Bit 2 - Endpoint Stalled

pub fn dataend(&mut self) -> DATAEND_W<'_>

Bit 3 - Data End

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 3 - Setup Packet

pub fn setend(&mut self) -> SETEND_W<'_>

Bit 4 - Setup End

pub fn error(&mut self) -> ERROR_W<'_>

Bit 4 - Error

pub fn reqpkt(&mut self) -> REQPKT_W<'_>

Bit 5 - Request Packet

pub fn stall(&mut self) -> STALL_W<'_>

Bit 5 - Send Stall

pub fn status(&mut self) -> STATUS_W<'_>

Bit 6 - STATUS Packet

pub fn rxrdyc(&mut self) -> RXRDYC_W<'_>

Bit 6 - RXRDY Clear

pub fn nakto(&mut self) -> NAKTO_W<'_>

Bit 7 - NAK Timeout

pub fn setendc(&mut self) -> SETENDC_W<'_>

Bit 7 - Setup End Clear

impl W<u8, Reg<u8, _CSRH0>>

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 0 - Flush FIFO

pub fn dt(&mut self) -> DT_W<'_>

Bit 1 - Data Toggle

pub fn dtwe(&mut self) -> DTWE_W<'_>

Bit 2 - Data Toggle Write Enable

impl W<u8, Reg<u8, _TYPE0>>

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 6:7 - Operating Speed

impl W<u8, Reg<u8, _NAKLMT>>

pub fn naklmt(&mut self) -> NAKLMT_W<'_>

Bits 0:4 - EP0 NAK Limit

impl W<u16, Reg<u16, _TXMAXP1>>

pub fn maxload(&mut self) -> MAXLOAD_W<'_>

Bits 0:10 - Maximum Payload

impl W<u8, Reg<u8, _TXCSRL1>>

pub fn txrdy(&mut self) -> TXRDY_W<'_>

Bit 0 - Transmit Packet Ready

pub fn fifone(&mut self) -> FIFONE_W<'_>

Bit 1 - FIFO Not Empty

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Error

pub fn undrn(&mut self) -> UNDRN_W<'_>

Bit 2 - Underrun

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 3 - Flush FIFO

pub fn stall(&mut self) -> STALL_W<'_>

Bit 4 - Send STALL

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 4 - Setup Packet

pub fn stalled(&mut self) -> STALLED_W<'_>

Bit 5 - Endpoint Stalled

pub fn clrdt(&mut self) -> CLRDT_W<'_>

Bit 6 - Clear Data Toggle

pub fn nakto(&mut self) -> NAKTO_W<'_>

Bit 7 - NAK Timeout

impl W<u8, Reg<u8, _TXCSRH1>>

pub fn dt(&mut self) -> DT_W<'_>

Bit 0 - Data Toggle

pub fn dtwe(&mut self) -> DTWE_W<'_>

Bit 1 - Data Toggle Write Enable

pub fn dmamod(&mut self) -> DMAMOD_W<'_>

Bit 2 - DMA Request Mode

pub fn fdt(&mut self) -> FDT_W<'_>

Bit 3 - Force Data Toggle

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 4 - DMA Request Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bit 5 - Mode

pub fn iso(&mut self) -> ISO_W<'_>

Bit 6 - Isochronous Transfers

pub fn autoset(&mut self) -> AUTOSET_W<'_>

Bit 7 - Auto Set

impl W<u16, Reg<u16, _RXMAXP1>>

pub fn maxload(&mut self) -> MAXLOAD_W<'_>

Bits 0:10 - Maximum Payload

impl W<u8, Reg<u8, _RXCSRL1>>

pub fn rxrdy(&mut self) -> RXRDY_W<'_>

Bit 0 - Receive Packet Ready

pub fn full(&mut self) -> FULL_W<'_>

Bit 1 - FIFO Full

pub fn over(&mut self) -> OVER_W<'_>

Bit 2 - Overrun

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Error

pub fn dataerr(&mut self) -> DATAERR_W<'_>

Bit 3 - Data Error

pub fn nakto(&mut self) -> NAKTO_W<'_>

Bit 3 - NAK Timeout

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 4 - Flush FIFO

pub fn stall(&mut self) -> STALL_W<'_>

Bit 5 - Send STALL

pub fn reqpkt(&mut self) -> REQPKT_W<'_>

Bit 5 - Request Packet

pub fn stalled(&mut self) -> STALLED_W<'_>

Bit 6 - Endpoint Stalled

pub fn clrdt(&mut self) -> CLRDT_W<'_>

Bit 7 - Clear Data Toggle

impl W<u8, Reg<u8, _RXCSRH1>>

pub fn dt(&mut self) -> DT_W<'_>

Bit 1 - Data Toggle

pub fn dtwe(&mut self) -> DTWE_W<'_>

Bit 2 - Data Toggle Write Enable

pub fn dmamod(&mut self) -> DMAMOD_W<'_>

Bit 3 - DMA Request Mode

pub fn disnyet(&mut self) -> DISNYET_W<'_>

Bit 4 - Disable NYET

pub fn piderr(&mut self) -> PIDERR_W<'_>

Bit 4 - PID Error

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 5 - DMA Request Enable

pub fn autorq(&mut self) -> AUTORQ_W<'_>

Bit 6 - Auto Request

pub fn iso(&mut self) -> ISO_W<'_>

Bit 6 - Isochronous Transfers

pub fn autocl(&mut self) -> AUTOCL_W<'_>

Bit 7 - Auto Clear

impl W<u8, Reg<u8, _TXTYPE1>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:3 - Target Endpoint Number

pub fn proto(&mut self) -> PROTO_W<'_>

Bits 4:5 - Protocol

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 6:7 - Operating Speed

impl W<u8, Reg<u8, _TXINTERVAL1>>

pub fn txpoll(&mut self) -> TXPOLL_W<'_>

Bits 0:7 - TX Polling

impl W<u8, Reg<u8, _RXTYPE1>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:3 - Target Endpoint Number

pub fn proto(&mut self) -> PROTO_W<'_>

Bits 4:5 - Protocol

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 6:7 - Operating Speed

impl W<u8, Reg<u8, _RXINTERVAL1>>

pub fn txpoll(&mut self) -> TXPOLL_W<'_>

Bits 0:7 - RX Polling

impl W<u16, Reg<u16, _TXMAXP2>>

pub fn maxload(&mut self) -> MAXLOAD_W<'_>

Bits 0:10 - Maximum Payload

impl W<u8, Reg<u8, _TXCSRL2>>

pub fn txrdy(&mut self) -> TXRDY_W<'_>

Bit 0 - Transmit Packet Ready

pub fn fifone(&mut self) -> FIFONE_W<'_>

Bit 1 - FIFO Not Empty

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Error

pub fn undrn(&mut self) -> UNDRN_W<'_>

Bit 2 - Underrun

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 3 - Flush FIFO

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 4 - Setup Packet

pub fn stall(&mut self) -> STALL_W<'_>

Bit 4 - Send STALL

pub fn stalled(&mut self) -> STALLED_W<'_>

Bit 5 - Endpoint Stalled

pub fn clrdt(&mut self) -> CLRDT_W<'_>

Bit 6 - Clear Data Toggle

pub fn nakto(&mut self) -> NAKTO_W<'_>

Bit 7 - NAK Timeout

impl W<u8, Reg<u8, _TXCSRH2>>

pub fn dt(&mut self) -> DT_W<'_>

Bit 0 - Data Toggle

pub fn dtwe(&mut self) -> DTWE_W<'_>

Bit 1 - Data Toggle Write Enable

pub fn dmamod(&mut self) -> DMAMOD_W<'_>

Bit 2 - DMA Request Mode

pub fn fdt(&mut self) -> FDT_W<'_>

Bit 3 - Force Data Toggle

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 4 - DMA Request Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bit 5 - Mode

pub fn iso(&mut self) -> ISO_W<'_>

Bit 6 - Isochronous Transfers

pub fn autoset(&mut self) -> AUTOSET_W<'_>

Bit 7 - Auto Set

impl W<u16, Reg<u16, _RXMAXP2>>

pub fn maxload(&mut self) -> MAXLOAD_W<'_>

Bits 0:10 - Maximum Payload

impl W<u8, Reg<u8, _RXCSRL2>>

pub fn rxrdy(&mut self) -> RXRDY_W<'_>

Bit 0 - Receive Packet Ready

pub fn full(&mut self) -> FULL_W<'_>

Bit 1 - FIFO Full

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Error

pub fn over(&mut self) -> OVER_W<'_>

Bit 2 - Overrun

pub fn dataerr(&mut self) -> DATAERR_W<'_>

Bit 3 - Data Error

pub fn nakto(&mut self) -> NAKTO_W<'_>

Bit 3 - NAK Timeout

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 4 - Flush FIFO

pub fn reqpkt(&mut self) -> REQPKT_W<'_>

Bit 5 - Request Packet

pub fn stall(&mut self) -> STALL_W<'_>

Bit 5 - Send STALL

pub fn stalled(&mut self) -> STALLED_W<'_>

Bit 6 - Endpoint Stalled

pub fn clrdt(&mut self) -> CLRDT_W<'_>

Bit 7 - Clear Data Toggle

impl W<u8, Reg<u8, _RXCSRH2>>

pub fn dt(&mut self) -> DT_W<'_>

Bit 1 - Data Toggle

pub fn dtwe(&mut self) -> DTWE_W<'_>

Bit 2 - Data Toggle Write Enable

pub fn dmamod(&mut self) -> DMAMOD_W<'_>

Bit 3 - DMA Request Mode

pub fn disnyet(&mut self) -> DISNYET_W<'_>

Bit 4 - Disable NYET

pub fn piderr(&mut self) -> PIDERR_W<'_>

Bit 4 - PID Error

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 5 - DMA Request Enable

pub fn autorq(&mut self) -> AUTORQ_W<'_>

Bit 6 - Auto Request

pub fn iso(&mut self) -> ISO_W<'_>

Bit 6 - Isochronous Transfers

pub fn autocl(&mut self) -> AUTOCL_W<'_>

Bit 7 - Auto Clear

impl W<u8, Reg<u8, _TXTYPE2>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:3 - Target Endpoint Number

pub fn proto(&mut self) -> PROTO_W<'_>

Bits 4:5 - Protocol

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 6:7 - Operating Speed

impl W<u8, Reg<u8, _TXINTERVAL2>>

pub fn txpoll(&mut self) -> TXPOLL_W<'_>

Bits 0:7 - TX Polling

impl W<u8, Reg<u8, _RXTYPE2>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:3 - Target Endpoint Number

pub fn proto(&mut self) -> PROTO_W<'_>

Bits 4:5 - Protocol

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 6:7 - Operating Speed

impl W<u8, Reg<u8, _RXINTERVAL2>>

pub fn txpoll(&mut self) -> TXPOLL_W<'_>

Bits 0:7 - RX Polling

impl W<u16, Reg<u16, _TXMAXP3>>

pub fn maxload(&mut self) -> MAXLOAD_W<'_>

Bits 0:10 - Maximum Payload

impl W<u8, Reg<u8, _TXCSRL3>>

pub fn txrdy(&mut self) -> TXRDY_W<'_>

Bit 0 - Transmit Packet Ready

pub fn fifone(&mut self) -> FIFONE_W<'_>

Bit 1 - FIFO Not Empty

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Error

pub fn undrn(&mut self) -> UNDRN_W<'_>

Bit 2 - Underrun

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 3 - Flush FIFO

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 4 - Setup Packet

pub fn stall(&mut self) -> STALL_W<'_>

Bit 4 - Send STALL

pub fn stalled(&mut self) -> STALLED_W<'_>

Bit 5 - Endpoint Stalled

pub fn clrdt(&mut self) -> CLRDT_W<'_>

Bit 6 - Clear Data Toggle

pub fn nakto(&mut self) -> NAKTO_W<'_>

Bit 7 - NAK Timeout

impl W<u8, Reg<u8, _TXCSRH3>>

pub fn dt(&mut self) -> DT_W<'_>

Bit 0 - Data Toggle

pub fn dtwe(&mut self) -> DTWE_W<'_>

Bit 1 - Data Toggle Write Enable

pub fn dmamod(&mut self) -> DMAMOD_W<'_>

Bit 2 - DMA Request Mode

pub fn fdt(&mut self) -> FDT_W<'_>

Bit 3 - Force Data Toggle

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 4 - DMA Request Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bit 5 - Mode

pub fn iso(&mut self) -> ISO_W<'_>

Bit 6 - Isochronous Transfers

pub fn autoset(&mut self) -> AUTOSET_W<'_>

Bit 7 - Auto Set

impl W<u16, Reg<u16, _RXMAXP3>>

pub fn maxload(&mut self) -> MAXLOAD_W<'_>

Bits 0:10 - Maximum Payload

impl W<u8, Reg<u8, _RXCSRL3>>

pub fn rxrdy(&mut self) -> RXRDY_W<'_>

Bit 0 - Receive Packet Ready

pub fn full(&mut self) -> FULL_W<'_>

Bit 1 - FIFO Full

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Error

pub fn over(&mut self) -> OVER_W<'_>

Bit 2 - Overrun

pub fn dataerr(&mut self) -> DATAERR_W<'_>

Bit 3 - Data Error

pub fn nakto(&mut self) -> NAKTO_W<'_>

Bit 3 - NAK Timeout

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 4 - Flush FIFO

pub fn stall(&mut self) -> STALL_W<'_>

Bit 5 - Send STALL

pub fn reqpkt(&mut self) -> REQPKT_W<'_>

Bit 5 - Request Packet

pub fn stalled(&mut self) -> STALLED_W<'_>

Bit 6 - Endpoint Stalled

pub fn clrdt(&mut self) -> CLRDT_W<'_>

Bit 7 - Clear Data Toggle

impl W<u8, Reg<u8, _RXCSRH3>>

pub fn dt(&mut self) -> DT_W<'_>

Bit 1 - Data Toggle

pub fn dtwe(&mut self) -> DTWE_W<'_>

Bit 2 - Data Toggle Write Enable

pub fn dmamod(&mut self) -> DMAMOD_W<'_>

Bit 3 - DMA Request Mode

pub fn disnyet(&mut self) -> DISNYET_W<'_>

Bit 4 - Disable NYET

pub fn piderr(&mut self) -> PIDERR_W<'_>

Bit 4 - PID Error

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 5 - DMA Request Enable

pub fn autorq(&mut self) -> AUTORQ_W<'_>

Bit 6 - Auto Request

pub fn iso(&mut self) -> ISO_W<'_>

Bit 6 - Isochronous Transfers

pub fn autocl(&mut self) -> AUTOCL_W<'_>

Bit 7 - Auto Clear

impl W<u8, Reg<u8, _TXTYPE3>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:3 - Target Endpoint Number

pub fn proto(&mut self) -> PROTO_W<'_>

Bits 4:5 - Protocol

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 6:7 - Operating Speed

impl W<u8, Reg<u8, _TXINTERVAL3>>

pub fn txpoll(&mut self) -> TXPOLL_W<'_>

Bits 0:7 - TX Polling

impl W<u8, Reg<u8, _RXTYPE3>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:3 - Target Endpoint Number

pub fn proto(&mut self) -> PROTO_W<'_>

Bits 4:5 - Protocol

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 6:7 - Operating Speed

impl W<u8, Reg<u8, _RXINTERVAL3>>

pub fn txpoll(&mut self) -> TXPOLL_W<'_>

Bits 0:7 - RX Polling

impl W<u16, Reg<u16, _TXMAXP4>>

pub fn maxload(&mut self) -> MAXLOAD_W<'_>

Bits 0:10 - Maximum Payload

impl W<u8, Reg<u8, _TXCSRL4>>

pub fn txrdy(&mut self) -> TXRDY_W<'_>

Bit 0 - Transmit Packet Ready

pub fn fifone(&mut self) -> FIFONE_W<'_>

Bit 1 - FIFO Not Empty

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Error

pub fn undrn(&mut self) -> UNDRN_W<'_>

Bit 2 - Underrun

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 3 - Flush FIFO

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 4 - Setup Packet

pub fn stall(&mut self) -> STALL_W<'_>

Bit 4 - Send STALL

pub fn stalled(&mut self) -> STALLED_W<'_>

Bit 5 - Endpoint Stalled

pub fn clrdt(&mut self) -> CLRDT_W<'_>

Bit 6 - Clear Data Toggle

pub fn nakto(&mut self) -> NAKTO_W<'_>

Bit 7 - NAK Timeout

impl W<u8, Reg<u8, _TXCSRH4>>

pub fn dt(&mut self) -> DT_W<'_>

Bit 0 - Data Toggle

pub fn dtwe(&mut self) -> DTWE_W<'_>

Bit 1 - Data Toggle Write Enable

pub fn dmamod(&mut self) -> DMAMOD_W<'_>

Bit 2 - DMA Request Mode

pub fn fdt(&mut self) -> FDT_W<'_>

Bit 3 - Force Data Toggle

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 4 - DMA Request Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bit 5 - Mode

pub fn iso(&mut self) -> ISO_W<'_>

Bit 6 - Isochronous Transfers

pub fn autoset(&mut self) -> AUTOSET_W<'_>

Bit 7 - Auto Set

impl W<u16, Reg<u16, _RXMAXP4>>

pub fn maxload(&mut self) -> MAXLOAD_W<'_>

Bits 0:10 - Maximum Payload

impl W<u8, Reg<u8, _RXCSRL4>>

pub fn rxrdy(&mut self) -> RXRDY_W<'_>

Bit 0 - Receive Packet Ready

pub fn full(&mut self) -> FULL_W<'_>

Bit 1 - FIFO Full

pub fn over(&mut self) -> OVER_W<'_>

Bit 2 - Overrun

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Error

pub fn nakto(&mut self) -> NAKTO_W<'_>

Bit 3 - NAK Timeout

pub fn dataerr(&mut self) -> DATAERR_W<'_>

Bit 3 - Data Error

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 4 - Flush FIFO

pub fn stall(&mut self) -> STALL_W<'_>

Bit 5 - Send STALL

pub fn reqpkt(&mut self) -> REQPKT_W<'_>

Bit 5 - Request Packet

pub fn stalled(&mut self) -> STALLED_W<'_>

Bit 6 - Endpoint Stalled

pub fn clrdt(&mut self) -> CLRDT_W<'_>

Bit 7 - Clear Data Toggle

impl W<u8, Reg<u8, _RXCSRH4>>

pub fn dt(&mut self) -> DT_W<'_>

Bit 1 - Data Toggle

pub fn dtwe(&mut self) -> DTWE_W<'_>

Bit 2 - Data Toggle Write Enable

pub fn dmamod(&mut self) -> DMAMOD_W<'_>

Bit 3 - DMA Request Mode

pub fn disnyet(&mut self) -> DISNYET_W<'_>

Bit 4 - Disable NYET

pub fn piderr(&mut self) -> PIDERR_W<'_>

Bit 4 - PID Error

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 5 - DMA Request Enable

pub fn autorq(&mut self) -> AUTORQ_W<'_>

Bit 6 - Auto Request

pub fn iso(&mut self) -> ISO_W<'_>

Bit 6 - Isochronous Transfers

pub fn autocl(&mut self) -> AUTOCL_W<'_>

Bit 7 - Auto Clear

impl W<u8, Reg<u8, _TXTYPE4>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:3 - Target Endpoint Number

pub fn proto(&mut self) -> PROTO_W<'_>

Bits 4:5 - Protocol

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 6:7 - Operating Speed

impl W<u8, Reg<u8, _TXINTERVAL4>>

pub fn txpoll(&mut self) -> TXPOLL_W<'_>

Bits 0:7 - TX Polling

impl W<u8, Reg<u8, _RXTYPE4>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:3 - Target Endpoint Number

pub fn proto(&mut self) -> PROTO_W<'_>

Bits 4:5 - Protocol

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 6:7 - Operating Speed

impl W<u8, Reg<u8, _RXINTERVAL4>>

pub fn txpoll(&mut self) -> TXPOLL_W<'_>

Bits 0:7 - RX Polling

impl W<u16, Reg<u16, _TXMAXP5>>

pub fn maxload(&mut self) -> MAXLOAD_W<'_>

Bits 0:10 - Maximum Payload

impl W<u8, Reg<u8, _TXCSRL5>>

pub fn txrdy(&mut self) -> TXRDY_W<'_>

Bit 0 - Transmit Packet Ready

pub fn fifone(&mut self) -> FIFONE_W<'_>

Bit 1 - FIFO Not Empty

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Error

pub fn undrn(&mut self) -> UNDRN_W<'_>

Bit 2 - Underrun

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 3 - Flush FIFO

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 4 - Setup Packet

pub fn stall(&mut self) -> STALL_W<'_>

Bit 4 - Send STALL

pub fn stalled(&mut self) -> STALLED_W<'_>

Bit 5 - Endpoint Stalled

pub fn clrdt(&mut self) -> CLRDT_W<'_>

Bit 6 - Clear Data Toggle

pub fn nakto(&mut self) -> NAKTO_W<'_>

Bit 7 - NAK Timeout

impl W<u8, Reg<u8, _TXCSRH5>>

pub fn dt(&mut self) -> DT_W<'_>

Bit 0 - Data Toggle

pub fn dtwe(&mut self) -> DTWE_W<'_>

Bit 1 - Data Toggle Write Enable

pub fn dmamod(&mut self) -> DMAMOD_W<'_>

Bit 2 - DMA Request Mode

pub fn fdt(&mut self) -> FDT_W<'_>

Bit 3 - Force Data Toggle

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 4 - DMA Request Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bit 5 - Mode

pub fn iso(&mut self) -> ISO_W<'_>

Bit 6 - Isochronous Transfers

pub fn autoset(&mut self) -> AUTOSET_W<'_>

Bit 7 - Auto Set

impl W<u16, Reg<u16, _RXMAXP5>>

pub fn maxload(&mut self) -> MAXLOAD_W<'_>

Bits 0:10 - Maximum Payload

impl W<u8, Reg<u8, _RXCSRL5>>

pub fn rxrdy(&mut self) -> RXRDY_W<'_>

Bit 0 - Receive Packet Ready

pub fn full(&mut self) -> FULL_W<'_>

Bit 1 - FIFO Full

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Error

pub fn over(&mut self) -> OVER_W<'_>

Bit 2 - Overrun

pub fn nakto(&mut self) -> NAKTO_W<'_>

Bit 3 - NAK Timeout

pub fn dataerr(&mut self) -> DATAERR_W<'_>

Bit 3 - Data Error

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 4 - Flush FIFO

pub fn stall(&mut self) -> STALL_W<'_>

Bit 5 - Send STALL

pub fn reqpkt(&mut self) -> REQPKT_W<'_>

Bit 5 - Request Packet

pub fn stalled(&mut self) -> STALLED_W<'_>

Bit 6 - Endpoint Stalled

pub fn clrdt(&mut self) -> CLRDT_W<'_>

Bit 7 - Clear Data Toggle

impl W<u8, Reg<u8, _RXCSRH5>>

pub fn dt(&mut self) -> DT_W<'_>

Bit 1 - Data Toggle

pub fn dtwe(&mut self) -> DTWE_W<'_>

Bit 2 - Data Toggle Write Enable

pub fn dmamod(&mut self) -> DMAMOD_W<'_>

Bit 3 - DMA Request Mode

pub fn disnyet(&mut self) -> DISNYET_W<'_>

Bit 4 - Disable NYET

pub fn piderr(&mut self) -> PIDERR_W<'_>

Bit 4 - PID Error

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 5 - DMA Request Enable

pub fn autorq(&mut self) -> AUTORQ_W<'_>

Bit 6 - Auto Request

pub fn iso(&mut self) -> ISO_W<'_>

Bit 6 - Isochronous Transfers

pub fn autocl(&mut self) -> AUTOCL_W<'_>

Bit 7 - Auto Clear

impl W<u8, Reg<u8, _TXTYPE5>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:3 - Target Endpoint Number

pub fn proto(&mut self) -> PROTO_W<'_>

Bits 4:5 - Protocol

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 6:7 - Operating Speed

impl W<u8, Reg<u8, _TXINTERVAL5>>

pub fn txpoll(&mut self) -> TXPOLL_W<'_>

Bits 0:7 - TX Polling

impl W<u8, Reg<u8, _RXTYPE5>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:3 - Target Endpoint Number

pub fn proto(&mut self) -> PROTO_W<'_>

Bits 4:5 - Protocol

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 6:7 - Operating Speed

impl W<u8, Reg<u8, _RXINTERVAL5>>

pub fn txpoll(&mut self) -> TXPOLL_W<'_>

Bits 0:7 - RX Polling

impl W<u16, Reg<u16, _TXMAXP6>>

pub fn maxload(&mut self) -> MAXLOAD_W<'_>

Bits 0:10 - Maximum Payload

impl W<u8, Reg<u8, _TXCSRL6>>

pub fn txrdy(&mut self) -> TXRDY_W<'_>

Bit 0 - Transmit Packet Ready

pub fn fifone(&mut self) -> FIFONE_W<'_>

Bit 1 - FIFO Not Empty

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Error

pub fn undrn(&mut self) -> UNDRN_W<'_>

Bit 2 - Underrun

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 3 - Flush FIFO

pub fn stall(&mut self) -> STALL_W<'_>

Bit 4 - Send STALL

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 4 - Setup Packet

pub fn stalled(&mut self) -> STALLED_W<'_>

Bit 5 - Endpoint Stalled

pub fn clrdt(&mut self) -> CLRDT_W<'_>

Bit 6 - Clear Data Toggle

pub fn nakto(&mut self) -> NAKTO_W<'_>

Bit 7 - NAK Timeout

impl W<u8, Reg<u8, _TXCSRH6>>

pub fn dt(&mut self) -> DT_W<'_>

Bit 0 - Data Toggle

pub fn dtwe(&mut self) -> DTWE_W<'_>

Bit 1 - Data Toggle Write Enable

pub fn dmamod(&mut self) -> DMAMOD_W<'_>

Bit 2 - DMA Request Mode

pub fn fdt(&mut self) -> FDT_W<'_>

Bit 3 - Force Data Toggle

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 4 - DMA Request Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bit 5 - Mode

pub fn iso(&mut self) -> ISO_W<'_>

Bit 6 - Isochronous Transfers

pub fn autoset(&mut self) -> AUTOSET_W<'_>

Bit 7 - Auto Set

impl W<u16, Reg<u16, _RXMAXP6>>

pub fn maxload(&mut self) -> MAXLOAD_W<'_>

Bits 0:10 - Maximum Payload

impl W<u8, Reg<u8, _RXCSRL6>>

pub fn rxrdy(&mut self) -> RXRDY_W<'_>

Bit 0 - Receive Packet Ready

pub fn full(&mut self) -> FULL_W<'_>

Bit 1 - FIFO Full

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Error

pub fn over(&mut self) -> OVER_W<'_>

Bit 2 - Overrun

pub fn nakto(&mut self) -> NAKTO_W<'_>

Bit 3 - NAK Timeout

pub fn dataerr(&mut self) -> DATAERR_W<'_>

Bit 3 - Data Error

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 4 - Flush FIFO

pub fn reqpkt(&mut self) -> REQPKT_W<'_>

Bit 5 - Request Packet

pub fn stall(&mut self) -> STALL_W<'_>

Bit 5 - Send STALL

pub fn stalled(&mut self) -> STALLED_W<'_>

Bit 6 - Endpoint Stalled

pub fn clrdt(&mut self) -> CLRDT_W<'_>

Bit 7 - Clear Data Toggle

impl W<u8, Reg<u8, _RXCSRH6>>

pub fn dt(&mut self) -> DT_W<'_>

Bit 1 - Data Toggle

pub fn dtwe(&mut self) -> DTWE_W<'_>

Bit 2 - Data Toggle Write Enable

pub fn dmamod(&mut self) -> DMAMOD_W<'_>

Bit 3 - DMA Request Mode

pub fn disnyet(&mut self) -> DISNYET_W<'_>

Bit 4 - Disable NYET

pub fn piderr(&mut self) -> PIDERR_W<'_>

Bit 4 - PID Error

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 5 - DMA Request Enable

pub fn autorq(&mut self) -> AUTORQ_W<'_>

Bit 6 - Auto Request

pub fn iso(&mut self) -> ISO_W<'_>

Bit 6 - Isochronous Transfers

pub fn autocl(&mut self) -> AUTOCL_W<'_>

Bit 7 - Auto Clear

impl W<u8, Reg<u8, _TXTYPE6>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:3 - Target Endpoint Number

pub fn proto(&mut self) -> PROTO_W<'_>

Bits 4:5 - Protocol

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 6:7 - Operating Speed

impl W<u8, Reg<u8, _TXINTERVAL6>>

pub fn txpoll(&mut self) -> TXPOLL_W<'_>

Bits 0:7 - TX Polling

impl W<u8, Reg<u8, _RXTYPE6>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:3 - Target Endpoint Number

pub fn proto(&mut self) -> PROTO_W<'_>

Bits 4:5 - Protocol

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 6:7 - Operating Speed

impl W<u8, Reg<u8, _RXINTERVAL6>>

pub fn txpoll(&mut self) -> TXPOLL_W<'_>

Bits 0:7 - RX Polling

impl W<u16, Reg<u16, _TXMAXP7>>

pub fn maxload(&mut self) -> MAXLOAD_W<'_>

Bits 0:10 - Maximum Payload

impl W<u8, Reg<u8, _TXCSRL7>>

pub fn txrdy(&mut self) -> TXRDY_W<'_>

Bit 0 - Transmit Packet Ready

pub fn fifone(&mut self) -> FIFONE_W<'_>

Bit 1 - FIFO Not Empty

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Error

pub fn undrn(&mut self) -> UNDRN_W<'_>

Bit 2 - Underrun

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 3 - Flush FIFO

pub fn stall(&mut self) -> STALL_W<'_>

Bit 4 - Send STALL

pub fn setup(&mut self) -> SETUP_W<'_>

Bit 4 - Setup Packet

pub fn stalled(&mut self) -> STALLED_W<'_>

Bit 5 - Endpoint Stalled

pub fn clrdt(&mut self) -> CLRDT_W<'_>

Bit 6 - Clear Data Toggle

pub fn nakto(&mut self) -> NAKTO_W<'_>

Bit 7 - NAK Timeout

impl W<u8, Reg<u8, _TXCSRH7>>

pub fn dt(&mut self) -> DT_W<'_>

Bit 0 - Data Toggle

pub fn dtwe(&mut self) -> DTWE_W<'_>

Bit 1 - Data Toggle Write Enable

pub fn dmamod(&mut self) -> DMAMOD_W<'_>

Bit 2 - DMA Request Mode

pub fn fdt(&mut self) -> FDT_W<'_>

Bit 3 - Force Data Toggle

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 4 - DMA Request Enable

pub fn mode(&mut self) -> MODE_W<'_>

Bit 5 - Mode

pub fn iso(&mut self) -> ISO_W<'_>

Bit 6 - Isochronous Transfers

pub fn autoset(&mut self) -> AUTOSET_W<'_>

Bit 7 - Auto Set

impl W<u16, Reg<u16, _RXMAXP7>>

pub fn maxload(&mut self) -> MAXLOAD_W<'_>

Bits 0:10 - Maximum Payload

impl W<u8, Reg<u8, _RXCSRL7>>

pub fn rxrdy(&mut self) -> RXRDY_W<'_>

Bit 0 - Receive Packet Ready

pub fn full(&mut self) -> FULL_W<'_>

Bit 1 - FIFO Full

pub fn error(&mut self) -> ERROR_W<'_>

Bit 2 - Error

pub fn over(&mut self) -> OVER_W<'_>

Bit 2 - Overrun

pub fn dataerr(&mut self) -> DATAERR_W<'_>

Bit 3 - Data Error

pub fn nakto(&mut self) -> NAKTO_W<'_>

Bit 3 - NAK Timeout

pub fn flush(&mut self) -> FLUSH_W<'_>

Bit 4 - Flush FIFO

pub fn reqpkt(&mut self) -> REQPKT_W<'_>

Bit 5 - Request Packet

pub fn stall(&mut self) -> STALL_W<'_>

Bit 5 - Send STALL

pub fn stalled(&mut self) -> STALLED_W<'_>

Bit 6 - Endpoint Stalled

pub fn clrdt(&mut self) -> CLRDT_W<'_>

Bit 7 - Clear Data Toggle

impl W<u8, Reg<u8, _RXCSRH7>>

pub fn dt(&mut self) -> DT_W<'_>

Bit 1 - Data Toggle

pub fn dtwe(&mut self) -> DTWE_W<'_>

Bit 2 - Data Toggle Write Enable

pub fn dmamod(&mut self) -> DMAMOD_W<'_>

Bit 3 - DMA Request Mode

pub fn piderr(&mut self) -> PIDERR_W<'_>

Bit 4 - PID Error

pub fn disnyet(&mut self) -> DISNYET_W<'_>

Bit 4 - Disable NYET

pub fn dmaen(&mut self) -> DMAEN_W<'_>

Bit 5 - DMA Request Enable

pub fn iso(&mut self) -> ISO_W<'_>

Bit 6 - Isochronous Transfers

pub fn autorq(&mut self) -> AUTORQ_W<'_>

Bit 6 - Auto Request

pub fn autocl(&mut self) -> AUTOCL_W<'_>

Bit 7 - Auto Clear

impl W<u8, Reg<u8, _TXTYPE7>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:3 - Target Endpoint Number

pub fn proto(&mut self) -> PROTO_W<'_>

Bits 4:5 - Protocol

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 6:7 - Operating Speed

impl W<u8, Reg<u8, _TXINTERVAL7>>

pub fn txpoll(&mut self) -> TXPOLL_W<'_>

Bits 0:7 - TX Polling

impl W<u8, Reg<u8, _RXTYPE7>>

pub fn tep(&mut self) -> TEP_W<'_>

Bits 0:3 - Target Endpoint Number

pub fn proto(&mut self) -> PROTO_W<'_>

Bits 4:5 - Protocol

pub fn speed(&mut self) -> SPEED_W<'_>

Bits 6:7 - Operating Speed

impl W<u8, Reg<u8, _RXINTERVAL7>>

pub fn txpoll(&mut self) -> TXPOLL_W<'_>

Bits 0:7 - RX Polling

impl W<u16, Reg<u16, _RQPKTCOUNT4>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Block Transfer Packet Count

impl W<u16, Reg<u16, _RQPKTCOUNT5>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Block Transfer Packet Count

impl W<u16, Reg<u16, _RQPKTCOUNT6>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Block Transfer Packet Count

impl W<u16, Reg<u16, _RQPKTCOUNT7>>

pub fn count(&mut self) -> COUNT_W<'_>

Bits 0:15 - Block Transfer Packet Count

impl W<u16, Reg<u16, _RXDPKTBUFDIS>>

pub fn ep1(&mut self) -> EP1_W<'_>

Bit 1 - EP1 RX Double-Packet Buffer Disable

pub fn ep2(&mut self) -> EP2_W<'_>

Bit 2 - EP2 RX Double-Packet Buffer Disable

pub fn ep3(&mut self) -> EP3_W<'_>

Bit 3 - EP3 RX Double-Packet Buffer Disable

pub fn ep4(&mut self) -> EP4_W<'_>

Bit 4 - EP4 RX Double-Packet Buffer Disable

pub fn ep5(&mut self) -> EP5_W<'_>

Bit 5 - EP5 RX Double-Packet Buffer Disable

pub fn ep6(&mut self) -> EP6_W<'_>

Bit 6 - EP6 RX Double-Packet Buffer Disable

pub fn ep7(&mut self) -> EP7_W<'_>

Bit 7 - EP7 RX Double-Packet Buffer Disable

impl W<u16, Reg<u16, _TXDPKTBUFDIS>>

pub fn ep1(&mut self) -> EP1_W<'_>

Bit 1 - EP1 TX Double-Packet Buffer Disable

pub fn ep2(&mut self) -> EP2_W<'_>

Bit 2 - EP2 TX Double-Packet Buffer Disable

pub fn ep3(&mut self) -> EP3_W<'_>

Bit 3 - EP3 TX Double-Packet Buffer Disable

pub fn ep4(&mut self) -> EP4_W<'_>

Bit 4 - EP4 TX Double-Packet Buffer Disable

pub fn ep5(&mut self) -> EP5_W<'_>

Bit 5 - EP5 TX Double-Packet Buffer Disable

pub fn ep6(&mut self) -> EP6_W<'_>

Bit 6 - EP6 TX Double-Packet Buffer Disable

pub fn ep7(&mut self) -> EP7_W<'_>

Bit 7 - EP7 TX Double-Packet Buffer Disable

impl W<u32, Reg<u32, _EPC>>

pub fn epen(&mut self) -> EPEN_W<'_>

Bits 0:1 - External Power Supply Enable Configuration

pub fn epende(&mut self) -> EPENDE_W<'_>

Bit 2 - EPEN Drive Enable

pub fn pflten(&mut self) -> PFLTEN_W<'_>

Bit 4 - Power Fault Input Enable

pub fn pfltsen_high(&mut self) -> PFLTSEN_HIGH_W<'_>

Bit 5 - Power Fault Sense

pub fn pfltaen(&mut self) -> PFLTAEN_W<'_>

Bit 6 - Power Fault Action Enable

pub fn pfltact(&mut self) -> PFLTACT_W<'_>

Bits 8:9 - Power Fault Action

impl W<u32, Reg<u32, _EPCIM>>

pub fn pf(&mut self) -> PF_W<'_>

Bit 0 - USB Power Fault Interrupt Mask

impl W<u32, Reg<u32, _EPCISC>>

pub fn pf(&mut self) -> PF_W<'_>

Bit 0 - USB Power Fault Interrupt Status and Clear

impl W<u32, Reg<u32, _DRIM>>

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 0 - RESUME Interrupt Mask

impl W<u32, Reg<u32, _DRISC>>

pub fn resume(&mut self) -> RESUME_W<'_>

Bit 0 - RESUME Interrupt Status and Clear

impl W<u32, Reg<u32, _GPCS>>

pub fn devmod(&mut self) -> DEVMOD_W<'_>

Bit 0 - Device Mode

pub fn devmodotg(&mut self) -> DEVMODOTG_W<'_>

Bit 1 - Enable Device Mode

impl W<u32, Reg<u32, _VDC>>

pub fn vbden(&mut self) -> VBDEN_W<'_>

Bit 0 - VBUS Droop Enable

impl W<u32, Reg<u32, _VDCIM>>

pub fn vd(&mut self) -> VD_W<'_>

Bit 0 - VBUS Droop Interrupt Mask

impl W<u32, Reg<u32, _VDCISC>>

pub fn vd(&mut self) -> VD_W<'_>

Bit 0 - VBUS Droop Interrupt Status and Clear

impl W<u32, Reg<u32, _IDVIM>>

pub fn id(&mut self) -> ID_W<'_>

Bit 0 - ID Valid Detect Interrupt Mask

impl W<u32, Reg<u32, _IDVISC>>

pub fn id(&mut self) -> ID_W<'_>

Bit 0 - ID Valid Detect Interrupt Status and Clear

impl W<u32, Reg<u32, _DMASEL>>

pub fn dmaarx(&mut self) -> DMAARX_W<'_>

Bits 0:3 - DMA A RX Select

pub fn dmaatx(&mut self) -> DMAATX_W<'_>

Bits 4:7 - DMA A TX Select

pub fn dmabrx(&mut self) -> DMABRX_W<'_>

Bits 8:11 - DMA B RX Select

pub fn dmabtx(&mut self) -> DMABTX_W<'_>

Bits 12:15 - DMA B TX Select

pub fn dmacrx(&mut self) -> DMACRX_W<'_>

Bits 16:19 - DMA C RX Select

pub fn dmactx(&mut self) -> DMACTX_W<'_>

Bits 20:23 - DMA C TX Select

impl W<u32, Reg<u32, _EEBLOCK>>

pub fn block(&mut self) -> BLOCK_W<'_>

Bits 0:15 - Current Block

impl W<u32, Reg<u32, _EEOFFSET>>

pub fn offset(&mut self) -> OFFSET_W<'_>

Bits 0:3 - Current Address Offset

impl W<u32, Reg<u32, _EERDWR>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - EEPROM Read or Write Data

impl W<u32, Reg<u32, _EERDWRINC>>

pub fn value(&mut self) -> VALUE_W<'_>

Bits 0:31 - EEPROM Read or Write Data with Increment

impl W<u32, Reg<u32, _EESUPP>>

pub fn eretry(&mut self) -> ERETRY_W<'_>

Bit 2 - Erase Must Be Retried

pub fn pretry(&mut self) -> PRETRY_W<'_>

Bit 3 - Programming Must Be Retried

impl W<u32, Reg<u32, _EEUNLOCK>>

pub fn unlock(&mut self) -> UNLOCK_W<'_>

Bits 0:31 - EEPROM Unlock

impl W<u32, Reg<u32, _EEPROT>>

pub fn prot(&mut self) -> PROT_W<'_>

Bits 0:2 - Protection Control

pub fn acc(&mut self) -> ACC_W<'_>

Bit 3 - Access Control

impl W<u32, Reg<u32, _EEPASS0>>

pub fn pass(&mut self) -> PASS_W<'_>

Bits 0:31 - Password

impl W<u32, Reg<u32, _EEPASS1>>

pub fn pass(&mut self) -> PASS_W<'_>

Bits 0:31 - Password

impl W<u32, Reg<u32, _EEPASS2>>

pub fn pass(&mut self) -> PASS_W<'_>

Bits 0:31 - Password

impl W<u32, Reg<u32, _EEINT>>

pub fn int(&mut self) -> INT_W<'_>

Bit 0 - Interrupt Enable

impl W<u32, Reg<u32, _EEHIDE>>

pub fn hn(&mut self) -> HN_W<'_>

Bits 1:31 - Hide Block

impl W<u32, Reg<u32, _EEDBGME>>

pub fn me(&mut self) -> ME_W<'_>

Bit 0 - Mass Erase

pub fn key(&mut self) -> KEY_W<'_>

Bits 16:31 - Erase Key

impl W<u32, Reg<u32, _IM>>

pub fn fpidcim(&mut self) -> FPIDCIM_W<'_>

Bit 0 - Floating-Point Input Denormal Exception Interrupt Mask

pub fn fpdzcim(&mut self) -> FPDZCIM_W<'_>

Bit 1 - Floating-Point Divide By 0 Exception Interrupt Mask

pub fn fpiocim(&mut self) -> FPIOCIM_W<'_>

Bit 2 - Floating-Point Invalid Operation Interrupt Mask

pub fn fpufcim(&mut self) -> FPUFCIM_W<'_>

Bit 3 - Floating-Point Underflow Exception Interrupt Mask

pub fn fpofcim(&mut self) -> FPOFCIM_W<'_>

Bit 4 - Floating-Point Overflow Exception Interrupt Mask

pub fn fpixcim(&mut self) -> FPIXCIM_W<'_>

Bit 5 - Floating-Point Inexact Exception Interrupt Mask

impl W<u32, Reg<u32, _IC>>

pub fn fpidcic(&mut self) -> FPIDCIC_W<'_>

Bit 0 - Floating-Point Input Denormal Exception Interrupt Clear

pub fn fpdzcic(&mut self) -> FPDZCIC_W<'_>

Bit 1 - Floating-Point Divide By 0 Exception Interrupt Clear

pub fn fpiocic(&mut self) -> FPIOCIC_W<'_>

Bit 2 - Floating-Point Invalid Operation Interrupt Clear

pub fn fpufcic(&mut self) -> FPUFCIC_W<'_>

Bit 3 - Floating-Point Underflow Exception Interrupt Clear

pub fn fpofcic(&mut self) -> FPOFCIC_W<'_>

Bit 4 - Floating-Point Overflow Exception Interrupt Clear

pub fn fpixcic(&mut self) -> FPIXCIC_W<'_>

Bit 5 - Floating-Point Inexact Exception Interrupt Clear

impl W<u32, Reg<u32, _CTL>>

pub fn rtcen(&mut self) -> RTCEN_W<'_>

Bit 0 - RTC Timer Enable

pub fn hibreq(&mut self) -> HIBREQ_W<'_>

Bit 1 - Hibernation Request

pub fn rtcwen(&mut self) -> RTCWEN_W<'_>

Bit 3 - RTC Wake-up Enable

pub fn pinwen(&mut self) -> PINWEN_W<'_>

Bit 4 - External Wake Pin Enable

pub fn clk32en(&mut self) -> CLK32EN_W<'_>

Bit 6 - Clocking Enable

pub fn vabort(&mut self) -> VABORT_W<'_>

Bit 7 - Power Cut Abort Enable

pub fn vdd3on(&mut self) -> VDD3ON_W<'_>

Bit 8 - VDD Powered

pub fn batwken(&mut self) -> BATWKEN_W<'_>

Bit 9 - Wake on Low Battery

pub fn batchk(&mut self) -> BATCHK_W<'_>

Bit 10 - Check Battery Status

pub fn vbatsel(&mut self) -> VBATSEL_W<'_>

Bits 13:14 - Select for Low-Battery Comparator

pub fn oscbyp(&mut self) -> OSCBYP_W<'_>

Bit 16 - Oscillator Bypass

pub fn oscdrv(&mut self) -> OSCDRV_W<'_>

Bit 17 - Oscillator Drive Capability

pub fn wrc(&mut self) -> WRC_W<'_>

Bit 31 - Write Complete/Capable

impl W<u32, Reg<u32, _IM>>

pub fn rtcalt0(&mut self) -> RTCALT0_W<'_>

Bit 0 - RTC Alert 0 Interrupt Mask

pub fn lowbat(&mut self) -> LOWBAT_W<'_>

Bit 2 - Low Battery Voltage Interrupt Mask

pub fn extw(&mut self) -> EXTW_W<'_>

Bit 3 - External Wake-Up Interrupt Mask

pub fn wc(&mut self) -> WC_W<'_>

Bit 4 - External Write Complete/Capable Interrupt Mask

impl W<u32, Reg<u32, _IC>>

pub fn rtcalt0(&mut self) -> RTCALT0_W<'_>

Bit 0 - RTC Alert0 Masked Interrupt Clear

pub fn lowbat(&mut self) -> LOWBAT_W<'_>

Bit 2 - Low Battery Voltage Interrupt Clear

pub fn extw(&mut self) -> EXTW_W<'_>

Bit 3 - External Wake-Up Interrupt Clear

pub fn wc(&mut self) -> WC_W<'_>

Bit 4 - Write Complete/Capable Interrupt Clear

impl W<u32, Reg<u32, _RTCT>>

pub fn trim(&mut self) -> TRIM_W<'_>

Bits 0:15 - RTC Trim Value

impl W<u32, Reg<u32, _RTCSS>>

pub fn rtcssc(&mut self) -> RTCSSC_W<'_>

Bits 0:14 - RTC Sub Seconds Count

pub fn rtcssm(&mut self) -> RTCSSM_W<'_>

Bits 16:30 - RTC Sub Seconds Match

impl W<u32, Reg<u32, _DATA>>

pub fn rtd(&mut self) -> RTD_W<'_>

Bits 0:31 - Hibernation Module NV Data

impl W<u32, Reg<u32, _FMA>>

pub fn offset(&mut self) -> OFFSET_W<'_>

Bits 0:17 - Address Offset

impl W<u32, Reg<u32, _FMD>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data Value

impl W<u32, Reg<u32, _FMC>>

pub fn write(&mut self) -> WRITE_W<'_>

Bit 0 - Write a Word into Flash Memory

pub fn erase(&mut self) -> ERASE_W<'_>

Bit 1 - Erase a Page of Flash Memory

pub fn merase(&mut self) -> MERASE_W<'_>

Bit 2 - Mass Erase Flash Memory

pub fn comt(&mut self) -> COMT_W<'_>

Bit 3 - Commit Register Value

pub fn wrkey(&mut self) -> WRKEY_W<'_>

Bits 17:31 - FLASH write key

impl W<u32, Reg<u32, _FCIM>>

pub fn amask(&mut self) -> AMASK_W<'_>

Bit 0 - Access Interrupt Mask

pub fn pmask(&mut self) -> PMASK_W<'_>

Bit 1 - Programming Interrupt Mask

pub fn emask(&mut self) -> EMASK_W<'_>

Bit 2 - EEPROM Interrupt Mask

pub fn voltmask(&mut self) -> VOLTMASK_W<'_>

Bit 9 - VOLT Interrupt Mask

pub fn invdmask(&mut self) -> INVDMASK_W<'_>

Bit 10 - Invalid Data Interrupt Mask

pub fn ermask(&mut self) -> ERMASK_W<'_>

Bit 11 - ERVER Interrupt Mask

pub fn progmask(&mut self) -> PROGMASK_W<'_>

Bit 13 - PROGVER Interrupt Mask

impl W<u32, Reg<u32, _FCMISC>>

pub fn amisc(&mut self) -> AMISC_W<'_>

Bit 0 - Access Masked Interrupt Status and Clear

pub fn pmisc(&mut self) -> PMISC_W<'_>

Bit 1 - Programming Masked Interrupt Status and Clear

pub fn emisc(&mut self) -> EMISC_W<'_>

Bit 2 - EEPROM Masked Interrupt Status and Clear

pub fn voltmisc(&mut self) -> VOLTMISC_W<'_>

Bit 9 - VOLT Masked Interrupt Status and Clear

pub fn invdmisc(&mut self) -> INVDMISC_W<'_>

Bit 10 - Invalid Data Masked Interrupt Status and Clear

pub fn ermisc(&mut self) -> ERMISC_W<'_>

Bit 11 - ERVER Masked Interrupt Status and Clear

pub fn progmisc(&mut self) -> PROGMISC_W<'_>

Bit 13 - PROGVER Masked Interrupt Status and Clear

impl W<u32, Reg<u32, _FMC2>>

pub fn wrbuf(&mut self) -> WRBUF_W<'_>

Bit 0 - Buffered Flash Memory Write

pub fn wrkey(&mut self) -> WRKEY_W<'_>

Bits 17:31 - FLASH write key

impl W<u32, Reg<u32, _FWBVAL>>

pub fn fwb(&mut self) -> FWB_W<'_>

Bits 0:31 - Flash Memory Write Buffer

impl W<u32, Reg<u32, _FWBN>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - Data

impl W<u32, Reg<u32, _RMCTL>>

pub fn ba(&mut self) -> BA_W<'_>

Bit 0 - Boot Alias

impl W<u32, Reg<u32, _USERREG0>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - User Data

impl W<u32, Reg<u32, _USERREG1>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - User Data

impl W<u32, Reg<u32, _USERREG2>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - User Data

impl W<u32, Reg<u32, _USERREG3>>

pub fn data(&mut self) -> DATA_W<'_>

Bits 0:31 - User Data

impl W<u32, Reg<u32, _PBORCTL>>

pub fn bor1(&mut self) -> BOR1_W<'_>

Bit 1 - VDD under BOR1 Event Action

pub fn bor0(&mut self) -> BOR0_W<'_>

Bit 2 - VDD under BOR0 Event Action

impl W<u32, Reg<u32, _IMC>>

pub fn bor1im(&mut self) -> BOR1IM_W<'_>

Bit 1 - VDD under BOR1 Interrupt Mask

pub fn mofim(&mut self) -> MOFIM_W<'_>

Bit 3 - Main Oscillator Failure Interrupt Mask

pub fn plllim(&mut self) -> PLLLIM_W<'_>

Bit 6 - PLL Lock Interrupt Mask

pub fn usbplllim(&mut self) -> USBPLLLIM_W<'_>

Bit 7 - USB PLL Lock Interrupt Mask

pub fn moscpupim(&mut self) -> MOSCPUPIM_W<'_>

Bit 8 - MOSC Power Up Interrupt Mask

pub fn vddaim(&mut self) -> VDDAIM_W<'_>

Bit 10 - VDDA Power OK Interrupt Mask

pub fn bor0im(&mut self) -> BOR0IM_W<'_>

Bit 11 - VDD under BOR0 Interrupt Mask

impl W<u32, Reg<u32, _MISC>>

pub fn bor1mis(&mut self) -> BOR1MIS_W<'_>

Bit 1 - VDD under BOR1 Masked Interrupt Status

pub fn mofmis(&mut self) -> MOFMIS_W<'_>

Bit 3 - Main Oscillator Failure Masked Interrupt Status

pub fn plllmis(&mut self) -> PLLLMIS_W<'_>

Bit 6 - PLL Lock Masked Interrupt Status

pub fn usbplllmis(&mut self) -> USBPLLLMIS_W<'_>

Bit 7 - USB PLL Lock Masked Interrupt Status

pub fn moscpupmis(&mut self) -> MOSCPUPMIS_W<'_>

Bit 8 - MOSC Power Up Masked Interrupt Status

pub fn vddamis(&mut self) -> VDDAMIS_W<'_>

Bit 10 - VDDA Power OK Masked Interrupt Status

pub fn bor0mis(&mut self) -> BOR0MIS_W<'_>

Bit 11 - VDD under BOR0 Masked Interrupt Status

impl W<u32, Reg<u32, _RESC>>

pub fn ext(&mut self) -> EXT_W<'_>

Bit 0 - External Reset

pub fn por(&mut self) -> POR_W<'_>

Bit 1 - Power-On Reset

pub fn bor(&mut self) -> BOR_W<'_>

Bit 2 - Brown-Out Reset

pub fn wdt0(&mut self) -> WDT0_W<'_>

Bit 3 - Watchdog Timer 0 Reset

pub fn sw(&mut self) -> SW_W<'_>

Bit 4 - Software Reset

pub fn wdt1(&mut self) -> WDT1_W<'_>

Bit 5 - Watchdog Timer 1 Reset

pub fn moscfail(&mut self) -> MOSCFAIL_W<'_>

Bit 16 - MOSC Failure Reset

impl W<u32, Reg<u32, _RCC>>

pub fn moscdis(&mut self) -> MOSCDIS_W<'_>

Bit 0 - Main Oscillator Disable

pub fn oscsrc(&mut self) -> OSCSRC_W<'_>

Bits 4:5 - Oscillator Source

pub fn xtal(&mut self) -> XTAL_W<'_>

Bits 6:10 - Crystal Value

pub fn bypass(&mut self) -> BYPASS_W<'_>

Bit 11 - PLL Bypass

pub fn pwrdn(&mut self) -> PWRDN_W<'_>

Bit 13 - PLL Power Down

pub fn pwmdiv(&mut self) -> PWMDIV_W<'_>

Bits 17:19 - PWM Unit Clock Divisor

pub fn usepwmdiv(&mut self) -> USEPWMDIV_W<'_>

Bit 20 - Enable PWM Clock Divisor

pub fn usesysdiv(&mut self) -> USESYSDIV_W<'_>

Bit 22 - Enable System Clock Divider

pub fn sysdiv(&mut self) -> SYSDIV_W<'_>

Bits 23:26 - System Clock Divisor

pub fn acg(&mut self) -> ACG_W<'_>

Bit 27 - Auto Clock Gating

impl W<u32, Reg<u32, _GPIOHBCTL>>

pub fn porta(&mut self) -> PORTA_W<'_>

Bit 0 - Port A Advanced High-Performance Bus

pub fn portb(&mut self) -> PORTB_W<'_>

Bit 1 - Port B Advanced High-Performance Bus

pub fn portc(&mut self) -> PORTC_W<'_>

Bit 2 - Port C Advanced High-Performance Bus

pub fn portd(&mut self) -> PORTD_W<'_>

Bit 3 - Port D Advanced High-Performance Bus

pub fn porte(&mut self) -> PORTE_W<'_>

Bit 4 - Port E Advanced High-Performance Bus

pub fn portf(&mut self) -> PORTF_W<'_>

Bit 5 - Port F Advanced High-Performance Bus

impl W<u32, Reg<u32, _RCC2>>

pub fn oscsrc2(&mut self) -> OSCSRC2_W<'_>

Bits 4:6 - Oscillator Source 2

pub fn bypass2(&mut self) -> BYPASS2_W<'_>

Bit 11 - PLL Bypass 2

pub fn pwrdn2(&mut self) -> PWRDN2_W<'_>

Bit 13 - Power-Down PLL 2

pub fn usbpwrdn(&mut self) -> USBPWRDN_W<'_>

Bit 14 - Power-Down USB PLL

pub fn sysdiv2lsb(&mut self) -> SYSDIV2LSB_W<'_>

Bit 22 - Additional LSB for SYSDIV2

pub fn sysdiv2(&mut self) -> SYSDIV2_W<'_>

Bits 23:28 - System Clock Divisor 2

pub fn div400(&mut self) -> DIV400_W<'_>

Bit 30 - Divide PLL as 400 MHz vs. 200 MHz

pub fn usercc2(&mut self) -> USERCC2_W<'_>

Bit 31 - Use RCC2

impl W<u32, Reg<u32, _MOSCCTL>>

pub fn cval(&mut self) -> CVAL_W<'_>

Bit 0 - Clock Validation for MOSC

pub fn moscim(&mut self) -> MOSCIM_W<'_>

Bit 1 - MOSC Failure Action

pub fn noxtal(&mut self) -> NOXTAL_W<'_>

Bit 2 - No Crystal Connected

impl W<u32, Reg<u32, _DSLPCLKCFG>>

pub fn pioscpd(&mut self) -> PIOSCPD_W<'_>

Bit 1 - PIOSC Power Down Request

pub fn o(&mut self) -> O_W<'_>

Bits 4:6 - Clock Source

pub fn d(&mut self) -> D_W<'_>

Bits 23:28 - Divider Field Override

impl W<u32, Reg<u32, _PIOSCCAL>>

pub fn ut(&mut self) -> UT_W<'_>

Bits 0:6 - User Trim Value

pub fn update(&mut self) -> UPDATE_W<'_>

Bit 8 - Update Trim

pub fn cal(&mut self) -> CAL_W<'_>

Bit 9 - Start Calibration

pub fn uten(&mut self) -> UTEN_W<'_>

Bit 31 - Use User Trim Value

impl W<u32, Reg<u32, _PLLFREQ0>>

pub fn mint(&mut self) -> MINT_W<'_>

Bits 0:9 - PLL M Integer Value

pub fn mfrac(&mut self) -> MFRAC_W<'_>

Bits 10:19 - PLL M Fractional Value

impl W<u32, Reg<u32, _PLLFREQ1>>

pub fn n(&mut self) -> N_W<'_>

Bits 0:4 - PLL N Value

pub fn q(&mut self) -> Q_W<'_>

Bits 8:12 - PLL Q Value

impl W<u32, Reg<u32, _SLPPWRCFG>>

pub fn srampm(&mut self) -> SRAMPM_W<'_>

Bits 0:1 - SRAM Power Modes

pub fn flashpm(&mut self) -> FLASHPM_W<'_>

Bits 4:5 - Flash Power Modes

impl W<u32, Reg<u32, _DSLPPWRCFG>>

pub fn srampm(&mut self) -> SRAMPM_W<'_>

Bits 0:1 - SRAM Power Modes

pub fn flashpm(&mut self) -> FLASHPM_W<'_>

Bits 4:5 - Flash Power Modes

impl W<u32, Reg<u32, _LDOSPCTL>>

pub fn vldo(&mut self) -> VLDO_W<'_>

Bits 0:7 - LDO Output Voltage

pub fn vadjen(&mut self) -> VADJEN_W<'_>

Bit 31 - Voltage Adjust Enable

impl W<u32, Reg<u32, _LDODPCTL>>

pub fn vldo(&mut self) -> VLDO_W<'_>

Bits 0:7 - LDO Output Voltage

pub fn vadjen(&mut self) -> VADJEN_W<'_>

Bit 31 - Voltage Adjust Enable

impl W<u32, Reg<u32, _SRWD>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - Watchdog Timer 0 Software Reset

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - Watchdog Timer 1 Software Reset

impl W<u32, Reg<u32, _SRTIMER>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - 16/32-Bit General-Purpose Timer 0 Software Reset

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - 16/32-Bit General-Purpose Timer 1 Software Reset

pub fn r2(&mut self) -> R2_W<'_>

Bit 2 - 16/32-Bit General-Purpose Timer 2 Software Reset

pub fn r3(&mut self) -> R3_W<'_>

Bit 3 - 16/32-Bit General-Purpose Timer 3 Software Reset

pub fn r4(&mut self) -> R4_W<'_>

Bit 4 - 16/32-Bit General-Purpose Timer 4 Software Reset

pub fn r5(&mut self) -> R5_W<'_>

Bit 5 - 16/32-Bit General-Purpose Timer 5 Software Reset

impl W<u32, Reg<u32, _SRGPIO>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - GPIO Port A Software Reset

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - GPIO Port B Software Reset

pub fn r2(&mut self) -> R2_W<'_>

Bit 2 - GPIO Port C Software Reset

pub fn r3(&mut self) -> R3_W<'_>

Bit 3 - GPIO Port D Software Reset

pub fn r4(&mut self) -> R4_W<'_>

Bit 4 - GPIO Port E Software Reset

pub fn r5(&mut self) -> R5_W<'_>

Bit 5 - GPIO Port F Software Reset

impl W<u32, Reg<u32, _SRDMA>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - uDMA Module Software Reset

impl W<u32, Reg<u32, _SRHIB>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - Hibernation Module Software Reset

impl W<u32, Reg<u32, _SRUART>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - UART Module 0 Software Reset

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - UART Module 1 Software Reset

pub fn r2(&mut self) -> R2_W<'_>

Bit 2 - UART Module 2 Software Reset

pub fn r3(&mut self) -> R3_W<'_>

Bit 3 - UART Module 3 Software Reset

pub fn r4(&mut self) -> R4_W<'_>

Bit 4 - UART Module 4 Software Reset

pub fn r5(&mut self) -> R5_W<'_>

Bit 5 - UART Module 5 Software Reset

pub fn r6(&mut self) -> R6_W<'_>

Bit 6 - UART Module 6 Software Reset

pub fn r7(&mut self) -> R7_W<'_>

Bit 7 - UART Module 7 Software Reset

impl W<u32, Reg<u32, _SRSSI>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - SSI Module 0 Software Reset

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - SSI Module 1 Software Reset

pub fn r2(&mut self) -> R2_W<'_>

Bit 2 - SSI Module 2 Software Reset

pub fn r3(&mut self) -> R3_W<'_>

Bit 3 - SSI Module 3 Software Reset

impl W<u32, Reg<u32, _SRI2C>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - I2C Module 0 Software Reset

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - I2C Module 1 Software Reset

pub fn r2(&mut self) -> R2_W<'_>

Bit 2 - I2C Module 2 Software Reset

pub fn r3(&mut self) -> R3_W<'_>

Bit 3 - I2C Module 3 Software Reset

impl W<u32, Reg<u32, _SRUSB>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - USB Module Software Reset

impl W<u32, Reg<u32, _SRCAN>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - CAN Module 0 Software Reset

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - CAN Module 1 Software Reset

impl W<u32, Reg<u32, _SRADC>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - ADC Module 0 Software Reset

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - ADC Module 1 Software Reset

impl W<u32, Reg<u32, _SRACMP>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - Analog Comparator Module 0 Software Reset

impl W<u32, Reg<u32, _SRPWM>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - PWM Module 0 Software Reset

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - PWM Module 1 Software Reset

impl W<u32, Reg<u32, _SRQEI>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - QEI Module 0 Software Reset

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - QEI Module 1 Software Reset

impl W<u32, Reg<u32, _SREEPROM>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - EEPROM Module Software Reset

impl W<u32, Reg<u32, _SRWTIMER>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - 32/64-Bit Wide General-Purpose Timer 0 Software Reset

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - 32/64-Bit Wide General-Purpose Timer 1 Software Reset

pub fn r2(&mut self) -> R2_W<'_>

Bit 2 - 32/64-Bit Wide General-Purpose Timer 2 Software Reset

pub fn r3(&mut self) -> R3_W<'_>

Bit 3 - 32/64-Bit Wide General-Purpose Timer 3 Software Reset

pub fn r4(&mut self) -> R4_W<'_>

Bit 4 - 32/64-Bit Wide General-Purpose Timer 4 Software Reset

pub fn r5(&mut self) -> R5_W<'_>

Bit 5 - 32/64-Bit Wide General-Purpose Timer 5 Software Reset

impl W<u32, Reg<u32, _RCGCWD>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - Watchdog Timer 0 Run Mode Clock Gating Control

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - Watchdog Timer 1 Run Mode Clock Gating Control

impl W<u32, Reg<u32, _RCGCTIMER>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - 16/32-Bit General-Purpose Timer 0 Run Mode Clock Gating Control

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - 16/32-Bit General-Purpose Timer 1 Run Mode Clock Gating Control

pub fn r2(&mut self) -> R2_W<'_>

Bit 2 - 16/32-Bit General-Purpose Timer 2 Run Mode Clock Gating Control

pub fn r3(&mut self) -> R3_W<'_>

Bit 3 - 16/32-Bit General-Purpose Timer 3 Run Mode Clock Gating Control

pub fn r4(&mut self) -> R4_W<'_>

Bit 4 - 16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control

pub fn r5(&mut self) -> R5_W<'_>

Bit 5 - 16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control

impl W<u32, Reg<u32, _RCGCGPIO>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - GPIO Port A Run Mode Clock Gating Control

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - GPIO Port B Run Mode Clock Gating Control

pub fn r2(&mut self) -> R2_W<'_>

Bit 2 - GPIO Port C Run Mode Clock Gating Control

pub fn r3(&mut self) -> R3_W<'_>

Bit 3 - GPIO Port D Run Mode Clock Gating Control

pub fn r4(&mut self) -> R4_W<'_>

Bit 4 - GPIO Port E Run Mode Clock Gating Control

pub fn r5(&mut self) -> R5_W<'_>

Bit 5 - GPIO Port F Run Mode Clock Gating Control

impl W<u32, Reg<u32, _RCGCDMA>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - uDMA Module Run Mode Clock Gating Control

impl W<u32, Reg<u32, _RCGCHIB>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - Hibernation Module Run Mode Clock Gating Control

impl W<u32, Reg<u32, _RCGCUART>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - UART Module 0 Run Mode Clock Gating Control

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - UART Module 1 Run Mode Clock Gating Control

pub fn r2(&mut self) -> R2_W<'_>

Bit 2 - UART Module 2 Run Mode Clock Gating Control

pub fn r3(&mut self) -> R3_W<'_>

Bit 3 - UART Module 3 Run Mode Clock Gating Control

pub fn r4(&mut self) -> R4_W<'_>

Bit 4 - UART Module 4 Run Mode Clock Gating Control

pub fn r5(&mut self) -> R5_W<'_>

Bit 5 - UART Module 5 Run Mode Clock Gating Control

pub fn r6(&mut self) -> R6_W<'_>

Bit 6 - UART Module 6 Run Mode Clock Gating Control

pub fn r7(&mut self) -> R7_W<'_>

Bit 7 - UART Module 7 Run Mode Clock Gating Control

impl W<u32, Reg<u32, _RCGCSSI>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - SSI Module 0 Run Mode Clock Gating Control

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - SSI Module 1 Run Mode Clock Gating Control

pub fn r2(&mut self) -> R2_W<'_>

Bit 2 - SSI Module 2 Run Mode Clock Gating Control

pub fn r3(&mut self) -> R3_W<'_>

Bit 3 - SSI Module 3 Run Mode Clock Gating Control

impl W<u32, Reg<u32, _RCGCI2C>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - I2C Module 0 Run Mode Clock Gating Control

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - I2C Module 1 Run Mode Clock Gating Control

pub fn r2(&mut self) -> R2_W<'_>

Bit 2 - I2C Module 2 Run Mode Clock Gating Control

pub fn r3(&mut self) -> R3_W<'_>

Bit 3 - I2C Module 3 Run Mode Clock Gating Control

impl W<u32, Reg<u32, _RCGCUSB>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - USB Module Run Mode Clock Gating Control

impl W<u32, Reg<u32, _RCGCCAN>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - CAN Module 0 Run Mode Clock Gating Control

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - CAN Module 1 Run Mode Clock Gating Control

impl W<u32, Reg<u32, _RCGCADC>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - ADC Module 0 Run Mode Clock Gating Control

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - ADC Module 1 Run Mode Clock Gating Control

impl W<u32, Reg<u32, _RCGCACMP>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - Analog Comparator Module 0 Run Mode Clock Gating Control

impl W<u32, Reg<u32, _RCGCPWM>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - PWM Module 0 Run Mode Clock Gating Control

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - PWM Module 1 Run Mode Clock Gating Control

impl W<u32, Reg<u32, _RCGCQEI>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - QEI Module 0 Run Mode Clock Gating Control

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - QEI Module 1 Run Mode Clock Gating Control

impl W<u32, Reg<u32, _RCGCEEPROM>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - EEPROM Module Run Mode Clock Gating Control

impl W<u32, Reg<u32, _RCGCWTIMER>>

pub fn r0(&mut self) -> R0_W<'_>

Bit 0 - 32/64-Bit Wide General-Purpose Timer 0 Run Mode Clock Gating Control

pub fn r1(&mut self) -> R1_W<'_>

Bit 1 - 32/64-Bit Wide General-Purpose Timer 1 Run Mode Clock Gating Control

pub fn r2(&mut self) -> R2_W<'_>

Bit 2 - 32/64-Bit Wide General-Purpose Timer 2 Run Mode Clock Gating Control

pub fn r3(&mut self) -> R3_W<'_>

Bit 3 - 32/64-Bit Wide General-Purpose Timer 3 Run Mode Clock Gating Control

pub fn r4(&mut self) -> R4_W<'_>

Bit 4 - 32/64-Bit Wide General-Purpose Timer 4 Run Mode Clock Gating Control

pub fn r5(&mut self) -> R5_W<'_>

Bit 5 - 32/64-Bit Wide General-Purpose Timer 5 Run Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCWD>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - Watchdog Timer 0 Sleep Mode Clock Gating Control

pub fn s1(&mut self) -> S1_W<'_>

Bit 1 - Watchdog Timer 1 Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCTIMER>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - 16/32-Bit General-Purpose Timer 0 Sleep Mode Clock Gating Control

pub fn s1(&mut self) -> S1_W<'_>

Bit 1 - 16/32-Bit General-Purpose Timer 1 Sleep Mode Clock Gating Control

pub fn s2(&mut self) -> S2_W<'_>

Bit 2 - 16/32-Bit General-Purpose Timer 2 Sleep Mode Clock Gating Control

pub fn s3(&mut self) -> S3_W<'_>

Bit 3 - 16/32-Bit General-Purpose Timer 3 Sleep Mode Clock Gating Control

pub fn s4(&mut self) -> S4_W<'_>

Bit 4 - 16/32-Bit General-Purpose Timer 4 Sleep Mode Clock Gating Control

pub fn s5(&mut self) -> S5_W<'_>

Bit 5 - 16/32-Bit General-Purpose Timer 5 Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCGPIO>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - GPIO Port A Sleep Mode Clock Gating Control

pub fn s1(&mut self) -> S1_W<'_>

Bit 1 - GPIO Port B Sleep Mode Clock Gating Control

pub fn s2(&mut self) -> S2_W<'_>

Bit 2 - GPIO Port C Sleep Mode Clock Gating Control

pub fn s3(&mut self) -> S3_W<'_>

Bit 3 - GPIO Port D Sleep Mode Clock Gating Control

pub fn s4(&mut self) -> S4_W<'_>

Bit 4 - GPIO Port E Sleep Mode Clock Gating Control

pub fn s5(&mut self) -> S5_W<'_>

Bit 5 - GPIO Port F Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCDMA>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - uDMA Module Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCHIB>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - Hibernation Module Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCUART>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - UART Module 0 Sleep Mode Clock Gating Control

pub fn s1(&mut self) -> S1_W<'_>

Bit 1 - UART Module 1 Sleep Mode Clock Gating Control

pub fn s2(&mut self) -> S2_W<'_>

Bit 2 - UART Module 2 Sleep Mode Clock Gating Control

pub fn s3(&mut self) -> S3_W<'_>

Bit 3 - UART Module 3 Sleep Mode Clock Gating Control

pub fn s4(&mut self) -> S4_W<'_>

Bit 4 - UART Module 4 Sleep Mode Clock Gating Control

pub fn s5(&mut self) -> S5_W<'_>

Bit 5 - UART Module 5 Sleep Mode Clock Gating Control

pub fn s6(&mut self) -> S6_W<'_>

Bit 6 - UART Module 6 Sleep Mode Clock Gating Control

pub fn s7(&mut self) -> S7_W<'_>

Bit 7 - UART Module 7 Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCSSI>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - SSI Module 0 Sleep Mode Clock Gating Control

pub fn s1(&mut self) -> S1_W<'_>

Bit 1 - SSI Module 1 Sleep Mode Clock Gating Control

pub fn s2(&mut self) -> S2_W<'_>

Bit 2 - SSI Module 2 Sleep Mode Clock Gating Control

pub fn s3(&mut self) -> S3_W<'_>

Bit 3 - SSI Module 3 Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCI2C>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - I2C Module 0 Sleep Mode Clock Gating Control

pub fn s1(&mut self) -> S1_W<'_>

Bit 1 - I2C Module 1 Sleep Mode Clock Gating Control

pub fn s2(&mut self) -> S2_W<'_>

Bit 2 - I2C Module 2 Sleep Mode Clock Gating Control

pub fn s3(&mut self) -> S3_W<'_>

Bit 3 - I2C Module 3 Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCUSB>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - USB Module Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCCAN>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - CAN Module 0 Sleep Mode Clock Gating Control

pub fn s1(&mut self) -> S1_W<'_>

Bit 1 - CAN Module 1 Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCADC>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - ADC Module 0 Sleep Mode Clock Gating Control

pub fn s1(&mut self) -> S1_W<'_>

Bit 1 - ADC Module 1 Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCACMP>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - Analog Comparator Module 0 Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCPWM>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - PWM Module 0 Sleep Mode Clock Gating Control

pub fn s1(&mut self) -> S1_W<'_>

Bit 1 - PWM Module 1 Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCQEI>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - QEI Module 0 Sleep Mode Clock Gating Control

pub fn s1(&mut self) -> S1_W<'_>

Bit 1 - QEI Module 1 Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCEEPROM>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - EEPROM Module Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _SCGCWTIMER>>

pub fn s0(&mut self) -> S0_W<'_>

Bit 0 - 32/64-Bit Wide General-Purpose Timer 0 Sleep Mode Clock Gating Control

pub fn s1(&mut self) -> S1_W<'_>

Bit 1 - 32/64-Bit Wide General-Purpose Timer 1 Sleep Mode Clock Gating Control

pub fn s2(&mut self) -> S2_W<'_>

Bit 2 - 32/64-Bit Wide General-Purpose Timer 2 Sleep Mode Clock Gating Control

pub fn s3(&mut self) -> S3_W<'_>

Bit 3 - 32/64-Bit Wide General-Purpose Timer 3 Sleep Mode Clock Gating Control

pub fn s4(&mut self) -> S4_W<'_>

Bit 4 - 32/64-Bit Wide General-Purpose Timer 4 Sleep Mode Clock Gating Control

pub fn s5(&mut self) -> S5_W<'_>

Bit 5 - 32/64-Bit Wide General-Purpose Timer 5 Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCWD>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - Watchdog Timer 0 Deep-Sleep Mode Clock Gating Control

pub fn d1(&mut self) -> D1_W<'_>

Bit 1 - Watchdog Timer 1 Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCTIMER>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - 16/32-Bit General-Purpose Timer 0 Deep-Sleep Mode Clock Gating Control

pub fn d1(&mut self) -> D1_W<'_>

Bit 1 - 16/32-Bit General-Purpose Timer 1 Deep-Sleep Mode Clock Gating Control

pub fn d2(&mut self) -> D2_W<'_>

Bit 2 - 16/32-Bit General-Purpose Timer 2 Deep-Sleep Mode Clock Gating Control

pub fn d3(&mut self) -> D3_W<'_>

Bit 3 - 16/32-Bit General-Purpose Timer 3 Deep-Sleep Mode Clock Gating Control

pub fn d4(&mut self) -> D4_W<'_>

Bit 4 - 16/32-Bit General-Purpose Timer 4 Deep-Sleep Mode Clock Gating Control

pub fn d5(&mut self) -> D5_W<'_>

Bit 5 - 16/32-Bit General-Purpose Timer 5 Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCGPIO>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - GPIO Port A Deep-Sleep Mode Clock Gating Control

pub fn d1(&mut self) -> D1_W<'_>

Bit 1 - GPIO Port B Deep-Sleep Mode Clock Gating Control

pub fn d2(&mut self) -> D2_W<'_>

Bit 2 - GPIO Port C Deep-Sleep Mode Clock Gating Control

pub fn d3(&mut self) -> D3_W<'_>

Bit 3 - GPIO Port D Deep-Sleep Mode Clock Gating Control

pub fn d4(&mut self) -> D4_W<'_>

Bit 4 - GPIO Port E Deep-Sleep Mode Clock Gating Control

pub fn d5(&mut self) -> D5_W<'_>

Bit 5 - GPIO Port F Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCDMA>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - uDMA Module Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCHIB>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - Hibernation Module Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCUART>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - UART Module 0 Deep-Sleep Mode Clock Gating Control

pub fn d1(&mut self) -> D1_W<'_>

Bit 1 - UART Module 1 Deep-Sleep Mode Clock Gating Control

pub fn d2(&mut self) -> D2_W<'_>

Bit 2 - UART Module 2 Deep-Sleep Mode Clock Gating Control

pub fn d3(&mut self) -> D3_W<'_>

Bit 3 - UART Module 3 Deep-Sleep Mode Clock Gating Control

pub fn d4(&mut self) -> D4_W<'_>

Bit 4 - UART Module 4 Deep-Sleep Mode Clock Gating Control

pub fn d5(&mut self) -> D5_W<'_>

Bit 5 - UART Module 5 Deep-Sleep Mode Clock Gating Control

pub fn d6(&mut self) -> D6_W<'_>

Bit 6 - UART Module 6 Deep-Sleep Mode Clock Gating Control

pub fn d7(&mut self) -> D7_W<'_>

Bit 7 - UART Module 7 Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCSSI>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - SSI Module 0 Deep-Sleep Mode Clock Gating Control

pub fn d1(&mut self) -> D1_W<'_>

Bit 1 - SSI Module 1 Deep-Sleep Mode Clock Gating Control

pub fn d2(&mut self) -> D2_W<'_>

Bit 2 - SSI Module 2 Deep-Sleep Mode Clock Gating Control

pub fn d3(&mut self) -> D3_W<'_>

Bit 3 - SSI Module 3 Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCI2C>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - I2C Module 0 Deep-Sleep Mode Clock Gating Control

pub fn d1(&mut self) -> D1_W<'_>

Bit 1 - I2C Module 1 Deep-Sleep Mode Clock Gating Control

pub fn d2(&mut self) -> D2_W<'_>

Bit 2 - I2C Module 2 Deep-Sleep Mode Clock Gating Control

pub fn d3(&mut self) -> D3_W<'_>

Bit 3 - I2C Module 3 Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCUSB>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - USB Module Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCCAN>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - CAN Module 0 Deep-Sleep Mode Clock Gating Control

pub fn d1(&mut self) -> D1_W<'_>

Bit 1 - CAN Module 1 Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCADC>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - ADC Module 0 Deep-Sleep Mode Clock Gating Control

pub fn d1(&mut self) -> D1_W<'_>

Bit 1 - ADC Module 1 Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCACMP>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - Analog Comparator Module 0 Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCPWM>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - PWM Module 0 Deep-Sleep Mode Clock Gating Control

pub fn d1(&mut self) -> D1_W<'_>

Bit 1 - PWM Module 1 Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCQEI>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - QEI Module 0 Deep-Sleep Mode Clock Gating Control

pub fn d1(&mut self) -> D1_W<'_>

Bit 1 - QEI Module 1 Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCEEPROM>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - EEPROM Module Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _DCGCWTIMER>>

pub fn d0(&mut self) -> D0_W<'_>

Bit 0 - 32/64-Bit Wide General-Purpose Timer 0 Deep-Sleep Mode Clock Gating Control

pub fn d1(&mut self) -> D1_W<'_>

Bit 1 - 32/64-Bit Wide General-Purpose Timer 1 Deep-Sleep Mode Clock Gating Control

pub fn d2(&mut self) -> D2_W<'_>

Bit 2 - 32/64-Bit Wide General-Purpose Timer 2 Deep-Sleep Mode Clock Gating Control

pub fn d3(&mut self) -> D3_W<'_>

Bit 3 - 32/64-Bit Wide General-Purpose Timer 3 Deep-Sleep Mode Clock Gating Control

pub fn d4(&mut self) -> D4_W<'_>

Bit 4 - 32/64-Bit Wide General-Purpose Timer 4 Deep-Sleep Mode Clock Gating Control

pub fn d5(&mut self) -> D5_W<'_>

Bit 5 - 32/64-Bit Wide General-Purpose Timer 5 Deep-Sleep Mode Clock Gating Control

impl W<u32, Reg<u32, _CFG>>

pub fn masten(&mut self) -> MASTEN_W<'_>

Bit 0 - Controller Master Enable

impl W<u32, Reg<u32, _CTLBASE>>

pub fn addr(&mut self) -> ADDR_W<'_>

Bits 10:31 - Channel Control Base Address

impl W<u32, Reg<u32, _USEBURSTSET>>

pub fn set(&mut self) -> SET_W<'_>

Bits 0:31 - Channel [n] Useburst Set

impl W<u32, Reg<u32, _USEBURSTCLR>>

pub fn clr(&mut self) -> CLR_W<'_>

Bits 0:31 - Channel [n] Useburst Clear

impl W<u32, Reg<u32, _REQMASKSET>>

pub fn set(&mut self) -> SET_W<'_>

Bits 0:31 - Channel [n] Request Mask Set

impl W<u32, Reg<u32, _REQMASKCLR>>

pub fn clr(&mut self) -> CLR_W<'_>

Bits 0:31 - Channel [n] Request Mask Clear

impl W<u32, Reg<u32, _ENASET>>

pub fn set(&mut self) -> SET_W<'_>

Bits 0:31 - Channel [n] Enable Set

impl W<u32, Reg<u32, _ENACLR>>

pub fn clr(&mut self) -> CLR_W<'_>

Bits 0:31 - Clear Channel [n] Enable Clear

impl W<u32, Reg<u32, _ALTSET>>

pub fn set(&mut self) -> SET_W<'_>

Bits 0:31 - Channel [n] Alternate Set

impl W<u32, Reg<u32, _ALTCLR>>

pub fn clr(&mut self) -> CLR_W<'_>

Bits 0:31 - Channel [n] Alternate Clear

impl W<u32, Reg<u32, _PRIOSET>>

pub fn set(&mut self) -> SET_W<'_>

Bits 0:31 - Channel [n] Priority Set

impl W<u32, Reg<u32, _PRIOCLR>>

pub fn clr(&mut self) -> CLR_W<'_>

Bits 0:31 - Channel [n] Priority Clear

impl W<u32, Reg<u32, _ERRCLR>>

pub fn errclr(&mut self) -> ERRCLR_W<'_>

Bit 0 - uDMA Bus Error Status

impl W<u32, Reg<u32, _CHASGN>>

pub fn chasgn(&mut self) -> CHASGN_W<'_>

Bits 0:31 - Channel [n] Assignment Select

impl W<u32, Reg<u32, _CHMAP0>>

pub fn ch0sel(&mut self) -> CH0SEL_W<'_>

Bits 0:3 - uDMA Channel 0 Source Select

pub fn ch1sel(&mut self) -> CH1SEL_W<'_>

Bits 4:7 - uDMA Channel 1 Source Select

pub fn ch2sel(&mut self) -> CH2SEL_W<'_>

Bits 8:11 - uDMA Channel 2 Source Select

pub fn ch3sel(&mut self) -> CH3SEL_W<'_>

Bits 12:15 - uDMA Channel 3 Source Select

pub fn ch4sel(&mut self) -> CH4SEL_W<'_>

Bits 16:19 - uDMA Channel 4 Source Select

pub fn ch5sel(&mut self) -> CH5SEL_W<'_>

Bits 20:23 - uDMA Channel 5 Source Select

pub fn ch6sel(&mut self) -> CH6SEL_W<'_>

Bits 24:27 - uDMA Channel 6 Source Select

pub fn ch7sel(&mut self) -> CH7SEL_W<'_>

Bits 28:31 - uDMA Channel 7 Source Select

impl W<u32, Reg<u32, _CHMAP1>>

pub fn ch8sel(&mut self) -> CH8SEL_W<'_>

Bits 0:3 - uDMA Channel 8 Source Select

pub fn ch9sel(&mut self) -> CH9SEL_W<'_>

Bits 4:7 - uDMA Channel 9 Source Select

pub fn ch10sel(&mut self) -> CH10SEL_W<'_>

Bits 8:11 - uDMA Channel 10 Source Select

pub fn ch11sel(&mut self) -> CH11SEL_W<'_>

Bits 12:15 - uDMA Channel 11 Source Select

pub fn ch12sel(&mut self) -> CH12SEL_W<'_>

Bits 16:19 - uDMA Channel 12 Source Select

pub fn ch13sel(&mut self) -> CH13SEL_W<'_>

Bits 20:23 - uDMA Channel 13 Source Select

pub fn ch14sel(&mut self) -> CH14SEL_W<'_>

Bits 24:27 - uDMA Channel 14 Source Select

pub fn ch15sel(&mut self) -> CH15SEL_W<'_>

Bits 28:31 - uDMA Channel 15 Source Select

impl W<u32, Reg<u32, _CHMAP2>>

pub fn ch16sel(&mut self) -> CH16SEL_W<'_>

Bits 0:3 - uDMA Channel 16 Source Select

pub fn ch17sel(&mut self) -> CH17SEL_W<'_>

Bits 4:7 - uDMA Channel 17 Source Select

pub fn ch18sel(&mut self) -> CH18SEL_W<'_>

Bits 8:11 - uDMA Channel 18 Source Select

pub fn ch19sel(&mut self) -> CH19SEL_W<'_>

Bits 12:15 - uDMA Channel 19 Source Select

pub fn ch20sel(&mut self) -> CH20SEL_W<'_>

Bits 16:19 - uDMA Channel 20 Source Select

pub fn ch21sel(&mut self) -> CH21SEL_W<'_>

Bits 20:23 - uDMA Channel 21 Source Select

pub fn ch22sel(&mut self) -> CH22SEL_W<'_>

Bits 24:27 - uDMA Channel 22 Source Select

pub fn ch23sel(&mut self) -> CH23SEL_W<'_>

Bits 28:31 - uDMA Channel 23 Source Select

impl W<u32, Reg<u32, _CHMAP3>>

pub fn ch24sel(&mut self) -> CH24SEL_W<'_>

Bits 0:3 - uDMA Channel 24 Source Select

pub fn ch25sel(&mut self) -> CH25SEL_W<'_>

Bits 4:7 - uDMA Channel 25 Source Select

pub fn ch26sel(&mut self) -> CH26SEL_W<'_>

Bits 8:11 - uDMA Channel 26 Source Select

pub fn ch27sel(&mut self) -> CH27SEL_W<'_>

Bits 12:15 - uDMA Channel 27 Source Select

pub fn ch28sel(&mut self) -> CH28SEL_W<'_>

Bits 16:19 - uDMA Channel 28 Source Select

pub fn ch29sel(&mut self) -> CH29SEL_W<'_>

Bits 20:23 - uDMA Channel 29 Source Select

pub fn ch30sel(&mut self) -> CH30SEL_W<'_>

Bits 24:27 - uDMA Channel 30 Source Select

pub fn ch31sel(&mut self) -> CH31SEL_W<'_>

Bits 28:31 - uDMA Channel 31 Source Select