Struct Fp16 

pub struct Fp16;

IEEE-754 binary16 (“half”): 1 sign, 5 exponent, 10 mantissa, bias 15. Has inf and NaN.

For a faster, inf/NaN-unchecked variant of the same layout see Fp16Fast.

Trait Implementations

impl Clone for Fp16

fn clone(&self) -> Fp16

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for Fp16

impl Debug for Fp16

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for Fp16

impl FloatSpec for Fp16

const BITS: u32 = 16

Total number of significant bits (e.g. 16 for fp16/bf16, 8 for fp8).

const EXP_BITS: u32 = 5

Width of the exponent field in bits.

const MANTISSA_BITS: u32 = 10

Width of the (stored, fractional) mantissa field in bits.

const EXP_BIAS: i32 = 15

Exponent bias (subtracted from the stored exponent to get the true exponent).

const SPECIAL: SpecialEncoding = SpecialEncoding::Ieee

How the maximum-exponent code points encode inf / NaN.

const HAS_SIGN: bool = true

Whether the format has a sign bit. Almost always true.

const SIGN_SHIFT: u32 = _

Bit position of the sign (and of the field block: exp occupies MANTISSA_BITS .. SIGN_SHIFT).

const STORAGE_MASK: u32 = _

Mask of the significant bits within the u32 working register ((1 << BITS) - 1).

const SIGN_MASK: u32 = _

Mask isolating the sign bit (0 when HAS_SIGN is false).

const EXP_FIELD_MAX: u32 = _

All-ones exponent field value ((1 << EXP_BITS) - 1).

const EXP_MASK: u32 = _

Mask isolating the exponent field (already shifted into place).

const MANTISSA_MASK: u32 = _

Mask isolating the mantissa field.

const MANTISSA_SHIFT: u32 = _

Bits the mantissa shifts when aligning to / from f32’s 23-bit field (F32_MANTISSA_BITS - MANTISSA_BITS). Requires MANTISSA_BITS <= 23 (true for every sub-f32 format).

const EXP_REBIAS: i32 = _

Added to the stored exponent going packed -> f32 (subtracted the other way): F32_EXP_BIAS - EXP_BIAS.

const MAX_FINITE_EXP_FIELD: u32 = _

Largest exponent field that still denotes a finite number on the pack (encode) side. For SpecialEncoding::Ieee and Unchecked the all-ones field is the reserved inf/NaN code point, so this is EXP_FIELD_MAX - 1; for the no-reserved-code-point schemes it is EXP_FIELD_MAX. (Note Unchecked unpack still decodes the all-ones exponent as a large normal - it only matters here that an input which would round up onto that reserved code point overflows, and so flushes to zero, matching the hardware vcvtps2ph + flush path.)

const MAX_FINITE_BITS: u32 = _

Bit pattern (sign clear) of the largest finite magnitude - the saturation target.

const INFINITY_BITS: u32 = Self::EXP_MASK

Bit pattern (sign clear) of +inf. Only meaningful when SPECIAL is Ieee.

const NAN_BITS: u32 = _

Canonical quiet-NaN bit pattern (sign clear). Meaningful unless the format has no NaN (SpecialEncoding::Finite).

const OVERFLOW_BITS: u32 = _

Result (sign clear) when a magnitude exceeds the finite range: ±inf for IEEE formats, saturation to the largest finite for the no-inf schemes, and signed zero for Unchecked (which flushes overflow). Used for both overflow of a finite input and for an f32 infinity input.

const NAN_OUT_BITS: u32 = _

Result (sign clear) for an f32 NaN input: the canonical NaN for formats that have one, saturation for SpecialEncoding::Finite (no NaN code point), and signed zero for Unchecked (which flushes NaN).

fn unpack(packed: u32) -> f32

Decode the low BITS bits of packed (one value of this format) into the f32 it represents. Exact: every value of these sub-f32 formats is representable in f32.

fn pack(value: f32) -> u32

Encode value (an f32) into the low BITS bits of the returned u32, rounding the mantissa to nearest, ties to even. Overflow becomes ±inf (or saturates, for the non-IEEE schemes); tiny values become subnormals or signed zero.

impl Hash for Fp16

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PackedFloatRegister<Fp16, ArrayRegister<F32x4V1, 2>> for U16x8V1

Available on x86 or x86-64 only.

fn pack(values: Storage<F>) -> Storage<Self>

where Self: CastRegister<F::Bits>,

fn unpack(values: Storage<Self>) -> Storage<F>

impl PackedFloatRegister<Fp16, ArrayRegister<F32x4V1, 4>> for ArrayRegister<U16x8V1, 2>

Available on x86 or x86-64 only.

fn pack(values: Storage<F>) -> Storage<Self>

where Self: CastRegister<F::Bits>,

fn unpack(values: Storage<Self>) -> Storage<F>

impl PackedFloatRegister<Fp16, ArrayRegister<F32x4V2, 2>> for U16x8V2

Available on x86 or x86-64 only.

fn pack(values: Storage<F>) -> Storage<Self>

where Self: CastRegister<F::Bits>,

fn unpack(values: Storage<Self>) -> Storage<F>

impl PackedFloatRegister<Fp16, ArrayRegister<F32x4V2, 4>> for ArrayRegister<U16x8V2, 2>

Available on x86 or x86-64 only.

fn pack(values: Storage<F>) -> Storage<Self>

where Self: CastRegister<F::Bits>,

fn unpack(values: Storage<Self>) -> Storage<F>

impl PackedFloatRegister<Fp16, ArrayRegister<F32x8V3, 2>> for U16x16V3

Available on crate feature avx2-f16c and (x86 or x86-64) only.

fn unpack(values: Storage<Self>) -> Storage<ArrayRegister<F32x8V3, 2>>

fn pack(values: Storage<ArrayRegister<F32x8V3, 2>>) -> Storage<Self>

impl PackedFloatRegister<Fp16, F32x4V1> for U16x4V1

Available on x86 or x86-64 only.

fn pack(values: Storage<F>) -> Storage<Self>

where Self: CastRegister<F::Bits>,

fn unpack(values: Storage<Self>) -> Storage<F>

impl PackedFloatRegister<Fp16, F32x4V2> for U16x4V2

Available on x86 or x86-64 only.

fn pack(values: Storage<F>) -> Storage<Self>

where Self: CastRegister<F::Bits>,

fn unpack(values: Storage<Self>) -> Storage<F>

impl PackedFloatRegister<Fp16, F32x4V3> for U16x4V3

Available on crate feature avx2-f16c and (x86 or x86-64) only.

fn unpack(values: Storage<Self>) -> Storage<F32x4V3>

fn pack(values: Storage<F32x4V3>) -> Storage<Self>

impl PackedFloatRegister<Fp16, F32x8V3> for U16x8V3

Available on crate feature avx2-f16c and (x86 or x86-64) only.

fn unpack(values: Storage<Self>) -> Storage<F32x8V3>

fn pack(values: Storage<F32x8V3>) -> Storage<Self>

impl PartialEq for Fp16

fn eq(&self, other: &Fp16) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl StructuralPartialEq for Fp16