Struct Bus

pub struct Bus {
    pub apu: Apu,
    pub genie_codes: HashMap<u16, GenieCode>,
    pub input: Input,
    pub open_bus: u8,
    pub ppu: Ppu,
    pub prg_ram_protect: bool,
    pub prg_ram: Memory<Vec<u8>>,
    pub prg_rom: Memory<Vec<u8>>,
    pub ram_state: RamState,
    pub region: NesRegion,
    pub wram: Memory<ConstSlice<u8, 0x0800>>,
}

NES Bus

https://wiki.nesdev.org/w/index.php/CPU_memory_map

|—————–| $FFFF |—————–| | PRG-ROM | | | |—————–| $8000 |—————–| | PRG-RAM or SRAM | | PRG-RAM or SRAM | |—————–| $6000 |—————–| | Expansion | | Expansion | | Modules | | Modules | |—————–| $4020 |—————–| | APU/Input | | | | Registers | | | |- - - - - - - - -| $4000 | | | PPU Mirrors | | I/O Registers | | $2000-$2007 | | | |- - - - - - - - -| $2008 | | | PPU Registers | | | |—————–| $2000 |—————–| | WRAM Mirrors | | | | $0000-$07FF | | | |- - - - - - - - -| $0800 | | | WRAM | | 2K Internal | |- - - - - - - - -| $0200 | Work RAM | | Stack | | | |- - - - - - - - -| $0100 | | | Zero Page | | | |—————–| $0000 |—————–|

Fields

apu: Apu

genie_codes: HashMap<u16, GenieCode>

input: Input

open_bus: u8

ppu: Ppu

prg_ram_protect: bool

prg_ram: Memory<Vec<u8>>

prg_rom: Memory<Vec<u8>>

ram_state: RamState

region: NesRegion

wram: Memory<ConstSlice<u8, 0x0800>>

Implementations

impl Bus

pub fn new(region: NesRegion, ram_state: RamState) -> Self

pub fn load_cart(&mut self, cart: Cart)

pub fn unload_cart(&mut self)

pub fn sram(&self) -> &[u8]

pub fn load_sram(&mut self, sram: Memory<Vec<u8>>)

pub fn wram(&self) -> &[u8]

pub fn add_genie_code(&mut self, genie_code: GenieCode)

Add a Game Genie code to override memory reads/writes.

Errors

Errors if genie code is invalid.

pub fn remove_genie_code(&mut self, code: &str)

Remove a Game Genie code.

pub fn clear_genie_codes(&mut self)

Remove all Game Genie codes.

pub fn audio_samples(&self) -> &[f32]

pub fn clear_audio_samples(&mut self)

Trait Implementations

impl Clock for Bus

fn clock(&mut self) -> u64

Clock component a single time, returning the number of cycles clocked.

impl ClockTo for Bus

fn clock_to(&mut self, clock: u64) -> u64

Clock component to the given master cycle, returning the number of cycles clocked.

impl Clone for Bus

fn clone(&self) -> Bus

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Bus

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Bus

fn default() -> Self

Returns the “default value” for a type.

impl<'de> Deserialize<'de> for Bus

fn deserialize<__D>(__deserializer: __D) -> Result<Self, __D::Error>

where __D: Deserializer<'de>,

Deserialize this value from the given Serde deserializer.

impl Read for Bus

fn read(&mut self, addr: u16) -> u8

Read from the given address.

fn peek(&self, addr: u16) -> u8

Peek from the given address.

fn read_u16(&mut self, addr: u16) -> u16

Read two bytes from the given address.

fn peek_u16(&self, addr: u16) -> u16

Peek two bytes from the given address.

impl Regional for Bus

fn region(&self) -> NesRegion

Return the current region.

fn set_region(&mut self, region: NesRegion)

Set the region.

impl Reset for Bus

fn reset(&mut self, kind: ResetKind)

Reset the component given the ResetKind.

impl Serialize for Bus

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error>

where __S: Serializer,

Serialize this value into the given Serde serializer.

impl Sram for Bus

fn save(&self, path: impl AsRef<Path>) -> Result<()>

Save RAM to a given path.

fn load(&mut self, path: impl AsRef<Path>) -> Result<()>

Load save RAM from a given path.

impl Write for Bus

fn write(&mut self, addr: u16, val: u8)

Write value to the given address.

fn write_u16(&mut self, addr: u16, val: u16)

Write valuetwo bytes to the given address.