Enum RelocKind 

pub enum RelocKind {
    ThmCall,
    ArmCall,
    MovwAbs,
    MovtAbs,
    Abs32,
    AArch64Call26,
    AArch64Jump26,
    AArch64AdrPrelPgHi21,
    AArch64AddAbsLo12Nc,
    RiscvCallPlt,
    RiscvHi20,
    RiscvLo12I,
}

A relocation entry produced during compilation

Records that a BL instruction at offset bytes into the function’s code targets an external symbol (e.g., __meld_dispatch_import). The linker resolves these when combining the Synth object with the Kiln bridge.

Variants

ThmCall

R_ARM_THM_CALL (ELF type 10) — a THUMB BL call site (#167). Correct only for a Thumb-state bl, whose 32-bit placeholder is f7ff fffe (branch-to-self, addend -4 for the +4 pipeline bias).

ArmCall

R_ARM_CALL (ELF type 28) — an ARM-STATE (A32) BL call site (#1040). The A32 analogue of RelocKind::ThmCall, exactly as RelocKind::AArch64Call26 and RelocKind::RiscvCallPlt are the analogues for their ISAs — the ISA is fixed at the site that KNOWS it, never re-derived at the ELF emitter where the information is gone.

Emitting ThmCall for an A32 bl was #1040: a consumer that trusts the declared type patches Thumb halfwords into an ARM-state word (or emits an interwork veneer), producing an invalid instruction. The matching A32 placeholder is ebfffffe (branch-to-self, addend -8 for the +8 pipeline bias) — gas emits exactly that for bl <extern> in ARM mode, and eb000000 (addend 0) lands two instructions past the callee entry, the A32 twin of #174.

MovwAbs

R_ARM_MOVW_ABS_NC — the MOVW half of a symbol-relative address (#237).

MovtAbs

R_ARM_MOVT_ABS — the MOVT half of a symbol-relative address (#237).

Abs32

R_ARM_ABS32 — a 32-bit absolute address held in a .text literal-pool word, loaded via LDR rX, [pc, #off] (#345). The link-survivable replacement for the inline-immediate MOVW/MOVT-ABS pair: ld/bfd patches the data word at link time (S + A, the addend living in the word, REL semantics), which survives placement into a large multi-object image — whereas an inline-instruction MOVW_ABS immediate can be mangled.

AArch64Call26

R_AARCH64_CALL26 (ELF type 283) — an AArch64 BL call site (#851). The AArch64 analogue of RelocKind::ThmCall: the linker patches the 26-bit word-offset immediate of the bl at offset to reach the target symbol. Emitted only by the EM_AARCH64 backend’s .rela.text.

AArch64Jump26

R_AARCH64_JUMP26 (ELF type 282) — an AArch64 B (tail-branch) site (#851 lane L3). Same 26-bit word-offset immediate as RelocKind::AArch64Call26, but for a branch that does NOT set x30: the aarch64 call_indirect funcref table is a .text-resident array of b func_N trampolines, so the dispatch’s blr sets the return address and the trampoline tail-branches into the callee (which returns straight to the dispatcher).

AArch64AdrPrelPgHi21

R_AARCH64_ADR_PREL_PG_HI21 (ELF type 275) — the adrp half of a PC-relative symbol address (#851 lane L3). Patches the 21-bit page delta (immlo[30:29] + immhi[23:5]) so adrp xd, sym reaches the 4 KiB page containing sym. Always paired with an RelocKind::AArch64AddAbsLo12Nc on the next instruction. This pair is how aarch64 reaches a synth-EMITTED region (the globals .data image, the funcref table) with NO dedicated base register — so neither feature adds an embedder precondition alongside x28.

AArch64AddAbsLo12Nc

R_AARCH64_ADD_ABS_LO12_NC (ELF type 277) — the add xd, xd, :lo12:sym half of a PC-relative symbol address (#851 lane L3). Patches the 12-bit immediate field [21:10] with (S + A) & 0xFFF.

RiscvCallPlt

R_RISCV_CALL_PLT (ELF type 19) — a RISC-V auipc+jalr call pair (#871). The RV32 analogue of RelocKind::ThmCall: offset points at the auipc of an 8-byte auipc ra, 0 ; jalr ra, 0(ra) placeholder and the linker patches BOTH instructions’ immediates to reach the target symbol (the modern form; R_RISCV_CALL is deprecated). Emitted only by the EM_RISCV backend’s .rela.text.

RiscvHi20

R_RISCV_HI20 (ELF type 26) — the lui half of an ABSOLUTE symbol address (RQ-63-RVGLOBAL, #242). offset points at a lui rd, 0 placeholder whose 20-bit immediate the linker patches to ((S + A) + 0x800) >> 12. Always paired with an RelocKind::RiscvLo12I on the next instruction. This pair is how RV32 reaches a synth-EMITTED region (the globals .data image, __synth_globals) with NO dedicated base register — the RV32 twin of the aarch64 adrp+add :lo12: pair, so globals add no embedder precondition beside s11. Absolute rather than PC-relative because the RV32 object is always statically host-linked into a fixed-address bare-metal image (the medlow code model), which needs no per-site local symbol.

RiscvLo12I

R_RISCV_LO12_I (ELF type 27) — the addi rd, rd, 0 half of an absolute symbol address (RQ-63-RVGLOBAL). The linker patches the 12-bit I-type immediate with the low bits of S + A.

Trait Implementations

impl Clone for RelocKind

fn clone(&self) -> RelocKind

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for RelocKind

impl Debug for RelocKind

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for RelocKind

impl PartialEq for RelocKind

fn eq(&self, other: &RelocKind) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl StructuralPartialEq for RelocKind